WO2007100551A2 - Very large scale integration of field effect transistors on si nanowires - Google Patents

Very large scale integration of field effect transistors on si nanowires Download PDF

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WO2007100551A2
WO2007100551A2 PCT/US2007/004383 US2007004383W WO2007100551A2 WO 2007100551 A2 WO2007100551 A2 WO 2007100551A2 US 2007004383 W US2007004383 W US 2007004383W WO 2007100551 A2 WO2007100551 A2 WO 2007100551A2
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nanowire
electronic device
nanowires
orthogonal cross
cross dimensions
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PCT/US2007/004383
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French (fr)
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WO2007100551A3 (en
WO2007100551A9 (en
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King-Ning Tu
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The Regents Of The University Of California
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Definitions

  • the present invention relates to electronic devices and more particularly to electronic devices that have nanowire components.
  • DRAM chips Dynamic-random-access-memory chips
  • MOSFET technology has transferred from plain Si wafers to SOI wafers, Silicon-On-Insulator wafers.
  • SOI the transistors are built on a thin film of Si in the SOI.
  • the technology of large scale integration has advanced from a Si wafer to a thin film of Si.
  • step-by-step we shall transfer the technology from a thin film to a wire.
  • An electronic device has a first electrical lead, a nonowire disposed on the first electrical lead, the nanowire comprising at least one semiconductor section between first and second metallic sections, a second electrical lead constructed to be in electrical contact with the first metallic section of the nanowire, and a third electrical lead in electrical contact with the metallic section of the nanowire.
  • the nanowire comprises at least a partial oxide outer layer.
  • An electronic device has a first plurality of electrical leads arranged substantially parallel to each other, a plurality of nanowires arranged substantially parallel to each other such that each nanowire is disposed on a corresponding one of the first plurality of electrical leads, and a second plurality of electrical leads arranged substantially parallel to each other and substantially orthogonal to and in electrical contact with the plurality of nanowires.
  • Each of the plurality of nanowires has alternating metallic and semiconductor regions.
  • Figure 1 is a schematic illustration of some structural features of an electronic device according to an embodiment of the current invention
  • Figures 2(a) and 2(b) are a schematic illustrations of some structural features of an electronic device according to an embodiment of the current invention and steps in the manufacturing process;
  • Figure 3(a) is a schematic illustration of a nanowire according to an embodiment of the current invention;
  • Figure 3(b) is a schematic illustration of an electronic device according to an embodiment of the current invention.
  • Figure 4 is a schematic illustration of an electronic device according to an embodiment of the current invention
  • Figure 5 is a schematic illustration of an electronic device according to an embodiment of the current invention shown in cross sectional view
  • Figure 6 is a schematic illustration of an electronic device according to an embodiment of the current invention
  • Figures 7A-7F show TEM images of the formation of NiSi regions in a Si nanowire
  • FIGS 7G and 7H illustrate schematically the formation of the NiSi regions of Figures 7A-7F;
  • Figure 8 A shows the growth rate of NiSi
  • Figure 8B shows the Activation energy of growth of nano NiSi
  • Figures 9A-9F show lattice images of the migration of epitaxial NiSi/Si interfaces.
  • Figures 9 A to 9C is the first set, and Figures 9D to 9F is the second set; and
  • Figures lOA-lOG show the hetero-structure of NiSi/Si/NiSi.
  • Figures 1OD to 1OG are lattice images of the hetero-structure down to 2 nm.
  • An embodiment of the current invention includes a concept of large scale integration of MOSFET devices on a Si nanowire. It can provide a unique device property that is different from the VLSI integration on SOI or Si wafers. Furthermore, it can be extended to a parallel array of Si nanowires.
  • the term nanowire as used herein means a structure that has one dimension that is greater than 100 nm and the two remaining orthogonal dimensions are each less than 100 nm.
  • the term wire does not imply anything about its electrical conductivity. It could be an electrical conductor, an electrical insulator, a semiconductor or any combination thereof.
  • the dimension of the nanowires may be at least ten times greater than the larger of the remaining two dimensions of the nanowire.
  • the dimension of the nanowires may be at least a hundred times greater than the larger of the remaining two dimensions of the nanowire. In some embodiments, the dimension of the nanowires may be at least a thousand times greater than the larger of the remaining two dimensions of the nanowire. In some embodiments, the smaller two dimensions of the nanowires are both less than about 40 nm. In some embodiments, the smaller two dimensions of the nanowires are less than about 40 nm and greater than about one nanometer.
  • FIG. 1 is a schematic illustration of at least portions of an electronic device 100 according to an embodiment of the current invention.
  • the electronic device 100 has an oxidized p-type Si nanowire 102, or a p-type Si nanowire having a SiO 2 coating 104 of several nanometers (nm) in thickness, lying on an Al thin film line 106.
  • the oxide coating 104 can provide the gate oxide and the Al line 106 underneath the Si nanowire 102 can provide the "word” line or gate to control such a MOSFET device.
  • Two Ni thin film lines 108 can be deposited by photo-resist lithographic techniques to cross the Si nanowire for this example. Before the deposition of the photo-resist and the Ni thin films 108, one can deposit a thin oxide 110 to cover the Si nanowire 102, followed by chemical-mechanical polishing to flatten the oxide 110 surface for photo-resist. (See Figure 2(a).) The deposited oxide 110 can also serve as insulation of the "word" line. The contact openings on the oxide of the Si nanowire 102 were etched in this example so the Ni can make direct contact with exposed openings on the Si nanowire 102, as shown in Figure 2(a).
  • Figure 2(a) is a schematic cross-sectional view of structure of the electronic device 100.
  • An annealing at 550 0 C for a short time will induce the formation of NiSi 112 in the Si nanowire 102.
  • the device 100 To operate the device 100, one may apply a voltage along the Al "word" line 106 underneath the Si nanowire 102. A layer of electrons will be attracted to the p-type St channel 1 16 between the two NiSi 112 sections. This layer of electrons is traditionally called the inversion layer. Since the diameter of the nanowire is small, the inversion layer will occupy substantially the entire section 116 of the Si nanowire 102. Since NiSi is metallic, the channel is connected electrically by the inversion layer so the two NiSi columns 112 are electrically connected. Using the Al interconnect "bit" lines 114, one can measure the channel current as a function of the applied gate voltage. This is the basic behavior of a field effect transistor. (See H. S. Wong, "Beyond the conventional transistor," IBM J. Res. & Devel. 46, 133-167 (2002).)
  • Figure 4 depicts a schematic illustration of a superlattice 200 of Si and NiSi according to an embodiment of this invention that includes a repeated bamboo-type structure of Si/NiSi/Si/NiSi/Si/NiSi/Si 202 on the p-type Si nanowire 204.
  • a repeated bamboo-type structure of Si/NiSi/Si/NiSi/Si/NiSi/Si 202 on the p-type Si nanowire 204 (Yue Wu Jie Xiang, Chen Yang, Wei Lu, and Charles M. Lieber, "Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures," Nature, 430, 61-65 (2004).)
  • the shaded sections depict NiSi sections and the open sections depict p-Si sections in the Si nanowire 204.
  • all of the p-type bamboo-type Si nano regions will have an inversion layer and so the entire superlattice is electrically connected according to this embodiment of the current invention.
  • FIG. 5 is a schematic illustration of an electronic device 300 according to an embodiment of the current invention.
  • the electronic device 300 has an array of Si nanowires
  • the diameter of the Si nanowire can vary the diameter of the Si nanowire, the dopant concentration in the Si nanowire, the thickness of the SiO 2 coating on the Si nanowire, and the length of the nanocolumn of superlattice of Si and NiSi.
  • NiSi by CoSi 2 or other suicide which has very low resistivity and an excellent lattice match to Si. (See, e.g.i K.N.
  • NiSi sections may be replaced by a SiO 2 section to provide an electrical insulator along the nanowire.
  • the SiO 2 coating generates stress in the Si nanowire which can provide increased electron mobility.
  • one may provide a S1 3 N4 layer instead of the SiO 2 layer.
  • the Si 3 N 4 layer generates compression in the Si nanowire which can provide increased hole mobility.
  • the large scale integration of circuits as depicted in Figure 6 can in principle be fabricated by using SOI.
  • Figures 7A- 1OG show experimental results for a particular example according to an embodiment of the current invention.
  • Figures 7A-7F show TEM images of the formation of NiSi regions in a Si nanowire.
  • Figures 7G and 7H illustrate schematically the formation of the NiSi regions of Figures 7A-7F.
  • Figure 8A shows the growth rate of NiSi.
  • Figure 8B shows the Activation energy of growth of nano NiSi.
  • Figures 9A-9F show lattice images of the migration of epitaxial NiSi/Si interfaces.
  • Figures 9A to 9C is the first set, and Figures 9D to 9F is the second set.
  • Figures 1 OA-I OG show the hetero-structure of NiSi/Si/NiSi.
  • Figures I OD to 1OG are lattice images of the hetero- structure down to 2 nm.

Abstract

An electronic device has a first electrical lead, a nonowire disposed on the first electrical lead, the nanowire having at least one semiconductor section between first and second metallic sections, a second electrical lead constructed to be in electrical contact with the first metallic section of the nanowire, and a third electrical lead in electrical contact with the metallic section of the nanowire. The nanowire has at least a partial oxide outer layer.

Description

VERY LARGE SCALE INTEGRATION OF FIELD EFFECT TRANSISTORS ON Si NANOWIRES
CROSS-REFERENCE OF RELATED APPLICATION This application claims priority to U.S. Provisional Application No. 60/775,343 filed
February 22, 2006, the entire contents of which are hereby incorporated by reference.
BACKGROUND
1. Field of Invention The present invention relates to electronic devices and more particularly to electronic devices that have nanowire components.
2. Discussion of Related Art
Conventional large scale integration of transistors has been accomplished on Si wafers using MOSFET technology, the Metal-Oxide-Semiconductor Field-Effect-Transistor technology. Dynamic-random-access-memory chips (DRAM chips), have been built on the basis of MOSFET technology by adding capacitors as memory units to the circuit. The basic circuit consists of one FET transistor and one capacitor. It is the simplest circuit and enables very large scale integration of a very large number of such circuits on a Si wafer. In the last thirty to forty years, the progress or increase of density of circuits per unit area of chip of this technology has followed Moore's law. In the last several years, MOSFET technology has transferred from plain Si wafers to SOI wafers, Silicon-On-Insulator wafers. In SOI, the transistors are built on a thin film of Si in the SOI. We may say the technology of large scale integration has advanced from a Si wafer to a thin film of Si. We expect that in the next stage of advancement, step-by-step, we shall transfer the technology from a thin film to a wire. In other words, we shall build large scale integration of transistors in a Si nanowire. There is thus a need for the development of field effect transistors on Si nanowires. SUMMARY
Further objectives and advantages will become apparent from a consideration of the description, drawings, and examples.
An electronic device according to an embodiment of the current invention has a first electrical lead, a nonowire disposed on the first electrical lead, the nanowire comprising at least one semiconductor section between first and second metallic sections, a second electrical lead constructed to be in electrical contact with the first metallic section of the nanowire, and a third electrical lead in electrical contact with the metallic section of the nanowire. The nanowire comprises at least a partial oxide outer layer.
An electronic device according to an embodiment of the current invention has a first plurality of electrical leads arranged substantially parallel to each other, a plurality of nanowires arranged substantially parallel to each other such that each nanowire is disposed on a corresponding one of the first plurality of electrical leads, and a second plurality of electrical leads arranged substantially parallel to each other and substantially orthogonal to and in electrical contact with the plurality of nanowires. Each of the plurality of nanowires has alternating metallic and semiconductor regions.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is better understood by reading the following detailed description with reference to the accompanying figures in which: Figure 1 is a schematic illustration of some structural features of an electronic device according to an embodiment of the current invention;
Figures 2(a) and 2(b) are a schematic illustrations of some structural features of an electronic device according to an embodiment of the current invention and steps in the manufacturing process; Figure 3(a) is a schematic illustration of a nanowire according to an embodiment of the current invention;
Figure 3(b) is a schematic illustration of an electronic device according to an embodiment of the current invention;
Figure 4 is a schematic illustration of an electronic device according to an embodiment of the current invention; Figure 5 is a schematic illustration of an electronic device according to an embodiment of the current invention shown in cross sectional view;
Figure 6 is a schematic illustration of an electronic device according to an embodiment of the current invention; Figures 7A-7F show TEM images of the formation of NiSi regions in a Si nanowire;
Figures 7G and 7H illustrate schematically the formation of the NiSi regions of Figures 7A-7F;
Figure 8 A shows the growth rate of NiSi;
Figure 8B shows the Activation energy of growth of nano NiSi; Figures 9A-9F show lattice images of the migration of epitaxial NiSi/Si interfaces.
Figures 9 A to 9C is the first set, and Figures 9D to 9F is the second set; and
Figures lOA-lOG show the hetero-structure of NiSi/Si/NiSi. Figures 1OD to 1OG are lattice images of the hetero-structure down to 2 nm.
DETAILED DESCRIPTION
In describing embodiments of the present invention illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the invention is not intended to be limited to the specific terminology so selected. It is to be understood that each specific element includes all technical equivalents which operate in a similar manner to accomplish a similar purpose.
An embodiment of the current invention includes a concept of large scale integration of MOSFET devices on a Si nanowire. It can provide a unique device property that is different from the VLSI integration on SOI or Si wafers. Furthermore, it can be extended to a parallel array of Si nanowires. The term nanowire as used herein means a structure that has one dimension that is greater than 100 nm and the two remaining orthogonal dimensions are each less than 100 nm. The term wire does not imply anything about its electrical conductivity. It could be an electrical conductor, an electrical insulator, a semiconductor or any combination thereof. In some embodiments, the dimension of the nanowires may be at least ten times greater than the larger of the remaining two dimensions of the nanowire. In some embodiments, the dimension of the nanowires may be at least a hundred times greater than the larger of the remaining two dimensions of the nanowire. In some embodiments, the dimension of the nanowires may be at least a thousand times greater than the larger of the remaining two dimensions of the nanowire. In some embodiments, the smaller two dimensions of the nanowires are both less than about 40 nm. In some embodiments, the smaller two dimensions of the nanowires are less than about 40 nm and greater than about one nanometer.
Figure 1 is a schematic illustration of at least portions of an electronic device 100 according to an embodiment of the current invention. The electronic device 100 has an oxidized p-type Si nanowire 102, or a p-type Si nanowire having a SiO2 coating 104 of several nanometers (nm) in thickness, lying on an Al thin film line 106. In this example, the oxide coating 104 can provide the gate oxide and the Al line 106 underneath the Si nanowire 102 can provide the "word" line or gate to control such a MOSFET device. If needed, we can produce an Al/Ni silicide/heavily doped poly-Si as the "word" line underneath the oxidized p-type Si nanowire, similar to a conventional polycide "word" line.
Two Ni thin film lines 108 (one shown in Figure 2(a)) can be deposited by photo-resist lithographic techniques to cross the Si nanowire for this example. Before the deposition of the photo-resist and the Ni thin films 108, one can deposit a thin oxide 110 to cover the Si nanowire 102, followed by chemical-mechanical polishing to flatten the oxide 110 surface for photo-resist. (See Figure 2(a).) The deposited oxide 110 can also serve as insulation of the "word" line. The contact openings on the oxide of the Si nanowire 102 were etched in this example so the Ni can make direct contact with exposed openings on the Si nanowire 102, as shown in Figure 2(a).
Figure 2(a) is a schematic cross-sectional view of structure of the electronic device 100. An annealing at 5500C for a short time will induce the formation of NiSi 112 in the Si nanowire 102. (See Figure 2(b).) One can control the annealing so that a bamboo-type column of NiSi is formed in the Si nanowire. One can thus obtain a nanowire structure of Si/NiSi/Si/NiSi/Si according to an embodiment of the current invention. Sections of Si in the nanowire 102 are still coated with oxide 104 since they were protected by the photoresist during the etching of the contact openings for suicide formation. Then one can etch away the remaining Ni and deposit Al interconnects 1 14 (one shown in Figure 2(b)) in the same trenches in the photo-resist. The cross-sectional view of the structure of the nanowire 102 after suicide formation is depicted in Fig. 2(b). The Al interconnect 1 14 is a "bit" line for the electronic device 100. By etching the photo-resist away, one can obtain a single MOSFET device in a Si nanowire 102, as depicted in Figure 3(a). In Figure 3(b), we illustrate the microstructure within the Si nanowire according to an embodiment of the current invention. It has two sections of NiSi 1 12 and a section of Si 116 between them that can provide a field-effect-transistor.
To operate the device 100, one may apply a voltage along the Al "word" line 106 underneath the Si nanowire 102. A layer of electrons will be attracted to the p-type St channel 1 16 between the two NiSi 112 sections. This layer of electrons is traditionally called the inversion layer. Since the diameter of the nanowire is small, the inversion layer will occupy substantially the entire section 116 of the Si nanowire 102. Since NiSi is metallic, the channel is connected electrically by the inversion layer so the two NiSi columns 112 are electrically connected. Using the Al interconnect "bit" lines 114, one can measure the channel current as a function of the applied gate voltage. This is the basic behavior of a field effect transistor. (See H. S. Wong, "Beyond the conventional transistor," IBM J. Res. & Devel. 46, 133-167 (2002).)
Figure 4 depicts a schematic illustration of a superlattice 200 of Si and NiSi according to an embodiment of this invention that includes a repeated bamboo-type structure of Si/NiSi/Si/NiSi/Si/NiSi/Si 202 on the p-type Si nanowire 204. (Yue Wu Jie Xiang, Chen Yang, Wei Lu, and Charles M. Lieber, "Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures," Nature, 430, 61-65 (2004).) In Figure 4, the shaded sections depict NiSi sections and the open sections depict p-Si sections in the Si nanowire 204. Furthermore, one can deposit Al wires as electrodes over the NiSi to form a chain of circuits on the Si nanowire. One can label the Al electrodes from yl , y2, y3 .... yn, and label the Si nanowire as xl . When one applies a voltage along xl, all of the p-type bamboo-type Si nano regions will have an inversion layer and so the entire superlattice is electrically connected according to this embodiment of the current invention. Now upon connecting the circuit between yl and y2, one can sense a transistor between them. However, if one were to connect the circuit between yl and y3, one would measure two transistors between them. If one were to connect yl and y4, one would measure three transistors between them, and so on. This is a unique property of integration of transistors on a Si nanowire. One can measure the source-to-drain current of one or two or three or many transistors.
Figure 5 is a schematic illustration of an electronic device 300 according to an embodiment of the current invention. The electronic device 300 has an array of Si nanowires
(302, 304, 306, 308) in parallel, illustrated in cross-section, each on an Al thin film line (310, 312, 314, 316). In each of the Si nanowires (302, 304, 306, 308), a superlattice of Si/NiSi/Si/NSi type structure has been produced. For the purpose of illustration, we shall consider four parallel Si nanowires as depicted in Fig. 5. In actual applications, one could use less than four or more than four, depending on the particular application. One can sputter a thin layer of SiO2 over the array and follow by chemical-mechanical polishing to flatten the surface for lithographic purposes. Then one can deposit a photo-resist on the flattened surface and develop a parallel set of trenches across the array of Si nanowires (302, 304, 306, 308). By etching, one can remove the top half of SiO2 coating of Si nanowires in order to open contact windows on the Si nanowires (302, 304, 306, 308) for Ni deposition to form bamboo-type NiSi in the Si nanowires. One can then remove the remaining Ni and then deposit Al interconnects into the trenches before etching away the photo-resist. Again, for the purpose of illustration, we illustrate four Al interconnects deposited across the four Si nanowires (302, 304, 306, 308). The cross-section of such a structure is shown in Figure 5.
In Figure 6, we have labeled the Si nanowires (and the "word" lines underneath) as xl, x2, x3, x4, and the Al "bit" lines as yl , y2, y2, y4 for an electronic device 400 according to an embodiment of the current invention. We label the transistors as tyxy; for example, in which •t322 means the transistor on x2 between y3 and y2. In operation of the electronic device 400, if one were to pass a voltage across x2, all the transistors will a have an inversion layer of electrons to link the neighboring NiSi, so the entire x2 becomes conducting. If one then connects y3 to y2, this would provide a circuit connecting the line y3-the transistor t322- the line y2. In this manner, one can obtain random assess to every transistor in the 2-dimensional array. Hence, one can achieve a very large scale integration of transistors using Si nanowires according to embodiments of the current invention.
However, when we open all the gates on x2, and we connect y3 and yl, we have two transistors t322 and t221 connected. On the other hand, when we open all the gates on x2 and x3, and we connect y2 and y3, for example, we have two transistors t322 and t332 in parallel. The properties of transistors in series and in parallel are of interest and may have very unique device applications.
To obtain the above very large scale of integration of transistors on Si nanowires, many processing steps may be required. For example, one may use a processing step to place a Si nanowire on a "word" line of Al as shown in Figure 1. There are currently processing steps available to make such devices.
To control the properties of the MOSFET on Si nanowires, one can vary the diameter of the Si nanowire, the dopant concentration in the Si nanowire, the thickness of the SiO2 coating on the Si nanowire, and the length of the nanocolumn of superlattice of Si and NiSi. One could replace the Al interconnects by Cu interconnects, but since Cu may poison the Si nanowire easily if Cu can diffuse into or reacts with the Si nanowire, Al may have advantages in certain applications. We can replace the SiO2 oxide coating on the Si nanowire by a high dielectric constant material for better gate performance. Also we can replace NiSi by CoSi2 or other suicide which has very low resistivity and an excellent lattice match to Si. (See, e.g.i K.N. Tu and J. W. Mayer, "Suicide Formation," Chapter 10 in Thin Films - Inter-diffusion and Reactions, edited by J.M. Poate, K.N. Tu and J. W. Mayer, John Wiley (1978), which is incorporated herein by reference; and F. Nava, K.N. Tu, O. Thomas, J.P. Senateur, R. Madar, A. Borghesi, G. Guizzetti, O. Laborde and O. Bisi, "Electrical and Optical Properties of Single-Crystalline and Thin-Film Suicides," Materials Science Reports, 9, 141-200 (1993).) In addition, one or more of the NiSi sections may be replaced by a SiO2 section to provide an electrical insulator along the nanowire. The SiO2 coating generates stress in the Si nanowire which can provide increased electron mobility. Alternatively, one may provide a S13N4 layer instead of the SiO2 layer. The Si3N4 layer generates compression in the Si nanowire which can provide increased hole mobility. Combinations of nanowires having different coatings, and combinations of coatings may be used without departing from the scope of this invention.
The large scale integration of circuits as depicted in Figure 6 can in principle be fabricated by using SOI. One should produce narrow and isolated Si lines on SOI and along the Si line produce Si/NiSi/Si/NiSi superlattice, then the rest of the integration is similar to what has been disclosed in the above.
EXAMPLE
Figures 7A- 1OG show experimental results for a particular example according to an embodiment of the current invention. Figures 7A-7F show TEM images of the formation of NiSi regions in a Si nanowire.
Figures 7G and 7H illustrate schematically the formation of the NiSi regions of Figures 7A-7F. Figure 8A shows the growth rate of NiSi. Figure 8B shows the Activation energy of growth of nano NiSi. Figures 9A-9F show lattice images of the migration of epitaxial NiSi/Si interfaces. Figures 9A to 9C is the first set, and Figures 9D to 9F is the second set. Figures 1 OA-I OG show the hetero-structure of NiSi/Si/NiSi. Figures I OD to 1OG are lattice images of the hetero- structure down to 2 nm.
Examples described above involve Si nanowires. However, this invention is not limited to only the materials described above. For example, one may use nanowires of semiconductors other than Si without departing from the general concepts of the invention.

Claims

1 CLAIM:
1. An electronic device, comprising: a first electrical lead; a nonowire disposed on said first electrical lead, said nanowire comprising at least one semiconductor section between first and second metallic sections; a second electrical lead constructed to be in electrical contact with said first metallic section of said nanowire; and a third electrical lead in electrical contact with said metallic section of said nanowire, wherein said nanowire comprises at least a partial oxide outer layer.
2. An electronic device according to claim 1, wherein said semiconductor section of said nanowire comprises p-type Si and said first and second metallic sections comprise NiSi.
3. An electronic device according to claim 1, wherein said first, second and third electrical leads are metallic leads.
4. An electronic device according to claim 1, wherein said first, second and third electrical leads are aluminum leads.
5. An electronic device according to claim 1 , wherein said partial oxide outer layer is greater than about 1 nm thick and less than about 10 nm thick.
6. An electronic device according to claim 1 , further comprising an electrical insulator disposed between said first electrical lead and at least one of said second and third electrical leads.
7. An electronic device according to claim 1 , wherein when a voltage is applied across said first and second metallic sections of said nanowire, an inversion layer forms substantially entirely across said semiconductor layer to provide a substantially conductive path.
8. An electronic device according to claim 1, wherein said nanowire has a long dimension that is longer than two orthogonal cross dimensions of said nanowire, said long dimension of said nanowire being at least ten times greater than a larger of said two orthogonal cross dimensions of said nanowire.
9. An electronic device according to claim 1, wherein said nanowire has a long dimension that is longer than two orthogonal cross dimensions of said nanowire, said long dimension of said nanowire being at least a hundred times greater than a larger of said two orthogonal cross dimensions of said nanowire.
10. An electronic device according to claim 1, wherein said nanowire has a long dimension that is longer than two orthogonal cross dimensions of said nanowire, said long dimension of said nanowire being at least a thousand times greater than a larger of said two orthogonal cross dimensions of said nanowire.
1 1. An electronic device according to claim 1, wherein said nanowire has a long dimension that is longer than two orthogonal cross dimensions of said nanowire, said two orthogonal cross dimensions of said nanowire being less than about 100 nm.
12. An electronic device according to claim 1, wherein said nanowire has a long dimension that is longer than two orthogonal cross dimensions of said nanowire, said two orthogonal cross dimensions of said nanowire being less than about 100 nm and greater than about 1 nm.
13. An electronic device, comprising a first plurality of electrical leads arranged substantially parallel to each other; a plurality of nanowires arranged substantially parallel to each other such that each nanowire is disposed on a corresponding one of said first plurality of electrical leads; and a second plurality of electrical leads arranged substantially parallel to each other and substantially orthogonal to and in electrical contact with said plurality of nanowires, wherein each of said plurality of nanowires has alternating metallic and semiconductor regions.
14. An electronic device according to claim 13, wherein said semiconductor regions of said plurality of nanowires comprise p-type Si and said metallic sections of said plurality of nanowires comprise NiSi.
15. An electronic device according to claim 13, wherein said first and second pluralities of electrical leads are metallic leads.
16. An electronic device according to claim 13, wherein said first and second pluralities of electrical leads are aluminum leads.
17. An electronic device according to claim 13, wherein said plurality of nanowires each has at least a partial oxide outer layer.
18. An electronic device according to claim 17, wherein said partial oxide outer layers are each greater than about 1 nm thick and less than about 10 nm thick.
19. An electronic device according to claim 13, further comprising an electrical insulator disposed between said first and second pluralities of electrical leads.
20. An electronic device according to claim 13, wherein when a voltage is applied across at least two electrical leads of said second plurality of electrical leads an inversion layer forms substantially entirely across at least one semiconductor region of each of said plurality of nanowires.
21. An electronic device according to claim 13, wherein each nanowire of said plurality of nanowires has a long dimension that is longer than two orthogonal cross dimensions of said each nanowire, said long dimension of said each nanowire being at least ten times greater than a larger of said two orthogonal cross dimensions of said each nanowire.
22. An electronic device according to claim 13, wherein each nanowire of said plurality of nanowires has a long dimension that is longer than two orthogonal cross dimensions of said each nanowire, said long dimension of said each nanowire being at least a hundred times greater than a larger of said two orthogonal cross dimensions of said each nanowire.
23. An electronic device according to claim 13, wherein each nanowire of said plurality of nanowires has a long dimension that is longer than two orthogonal cross dimensions of said each nanowire, said long dimension of said each nanowire being at least a thousand times greater than a larger of said two orthogonal cross dimensions of said each nanowire.
24. An electronic device according to claim 13, wherein each nanowire of said plurality of nanowires has a long dimension that is longer than two orthogonal cross dimensions of said each nanowire, said two orthogonal cross dimensions of said each nanowire being less than about 100 nm.
25. An electronic device according to claim 13, wherein each nanowire of said plurality of nanowires has a long dimension that is longer than two orthogonal cross dimensions of said each nanowire, said two orthogonal cross dimensions of said each nanowire being less than about 100 nm and greater than about 1 nm.
26. A nanostructure having an axial dimension and two orthogonal transverse dimensions, wherein the axial dimension is at least twice as long as the longer of two transverse dimensions, wherein the two orthogonal dimensions are each at least 1 nm and less than about lOOnm, and wherein said nanostructure has alternating substantially semiconductor and metallic regions along a direction of the axial dimension.
PCT/US2007/004383 2006-02-22 2007-02-21 Very large scale integration of field effect transistors on si nanowires WO2007100551A2 (en)

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