WO2007089949A3 - Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes - Google Patents

Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes Download PDF

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Publication number
WO2007089949A3
WO2007089949A3 PCT/US2007/003248 US2007003248W WO2007089949A3 WO 2007089949 A3 WO2007089949 A3 WO 2007089949A3 US 2007003248 W US2007003248 W US 2007003248W WO 2007089949 A3 WO2007089949 A3 WO 2007089949A3
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WO
WIPO (PCT)
Prior art keywords
memory cells
charge storage
storage nodes
trench
split charge
Prior art date
Application number
PCT/US2007/003248
Other languages
French (fr)
Other versions
WO2007089949A2 (en
Inventor
Chungho Lee
Wei Zheng
Chi Chang
Unsoon Kim
Hiroyuki Kinoshita
Original Assignee
Spansion Llc
Chungho Lee
Wei Zheng
Chi Chang
Unsoon Kim
Hiroyuki Kinoshita
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc, Chungho Lee, Wei Zheng, Chi Chang, Unsoon Kim, Hiroyuki Kinoshita filed Critical Spansion Llc
Publication of WO2007089949A2 publication Critical patent/WO2007089949A2/en
Publication of WO2007089949A3 publication Critical patent/WO2007089949A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench (64) and an adjacent second trench (64) in a semiconductor substrate (52), the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region (58) in the substrate and a second source/drain-region (58) in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier (62) in the substrate between the first source/drain region and the second source drain region and forming a first storage element (84) on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line (60) is formed in contact with the first storage element and the second storage element.
PCT/US2007/003248 2006-02-04 2007-02-05 Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes WO2007089949A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US76484706P 2006-02-04 2006-02-04
US60/764,847 2006-02-04

Publications (2)

Publication Number Publication Date
WO2007089949A2 WO2007089949A2 (en) 2007-08-09
WO2007089949A3 true WO2007089949A3 (en) 2007-11-29

Family

ID=38235446

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/003248 WO2007089949A2 (en) 2006-02-04 2007-02-05 Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes

Country Status (1)

Country Link
WO (1) WO2007089949A2 (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5955767A (en) * 1996-01-24 1999-09-21 Advanced Micro Devices, Inc. Semiconductor device with self-aligned insulator
US6215702B1 (en) * 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
EP1205978A2 (en) * 2000-11-09 2002-05-15 Innotech Corporation Semiconductor memory device, method of manufacturing the same and method of driving the same
EP1300888A1 (en) * 2001-10-08 2003-04-09 STMicroelectronics S.r.l. Process for manufacturing a dual charge storage location memory cell
US6639271B1 (en) * 2001-12-20 2003-10-28 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US20040005761A1 (en) * 2002-02-15 2004-01-08 Takumi Shibata Method for manufacturing non-volatile memory device
US6770934B1 (en) * 2003-04-03 2004-08-03 Powerchip Semiconductor Corp. Flash memory device structure and manufacturing method thereof
US20040238852A1 (en) * 2003-05-30 2004-12-02 Dana Lee Array of integrated circuit units with strapping lines to prevent punch through
US6917068B1 (en) * 2002-06-21 2005-07-12 Advanced Micro Devices, Inc. Semiconductor device having conductive structures formed near a gate electrode

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5955767A (en) * 1996-01-24 1999-09-21 Advanced Micro Devices, Inc. Semiconductor device with self-aligned insulator
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
US6215702B1 (en) * 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
EP1205978A2 (en) * 2000-11-09 2002-05-15 Innotech Corporation Semiconductor memory device, method of manufacturing the same and method of driving the same
EP1300888A1 (en) * 2001-10-08 2003-04-09 STMicroelectronics S.r.l. Process for manufacturing a dual charge storage location memory cell
US6639271B1 (en) * 2001-12-20 2003-10-28 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US20040005761A1 (en) * 2002-02-15 2004-01-08 Takumi Shibata Method for manufacturing non-volatile memory device
US6917068B1 (en) * 2002-06-21 2005-07-12 Advanced Micro Devices, Inc. Semiconductor device having conductive structures formed near a gate electrode
US6770934B1 (en) * 2003-04-03 2004-08-03 Powerchip Semiconductor Corp. Flash memory device structure and manufacturing method thereof
US20040238852A1 (en) * 2003-05-30 2004-12-02 Dana Lee Array of integrated circuit units with strapping lines to prevent punch through

Also Published As

Publication number Publication date
WO2007089949A2 (en) 2007-08-09

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