WO2007089949A3 - Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes - Google Patents

Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes Download PDF

Info

Publication number
WO2007089949A3
WO2007089949A3 PCT/US2007/003248 US2007003248W WO2007089949A3 WO 2007089949 A3 WO2007089949 A3 WO 2007089949A3 US 2007003248 W US2007003248 W US 2007003248W WO 2007089949 A3 WO2007089949 A3 WO 2007089949A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cells
trench
charge storage
storage nodes
source
Prior art date
Application number
PCT/US2007/003248
Other languages
French (fr)
Other versions
WO2007089949A2 (en
Inventor
Chi Chang
Unsoon Kim
Hiroyuki Kinoshita
Chungho Lee
Wei Zheng
Original Assignee
Chi Chang
Unsoon Kim
Hiroyuki Kinoshita
Chungho Lee
Spansion Llc
Wei Zheng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US76484706P priority Critical
Priority to US60/764,847 priority
Application filed by Chi Chang, Unsoon Kim, Hiroyuki Kinoshita, Chungho Lee, Spansion Llc, Wei Zheng filed Critical Chi Chang
Publication of WO2007089949A2 publication Critical patent/WO2007089949A2/en
Publication of WO2007089949A3 publication Critical patent/WO2007089949A3/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923Programmable transistors with more than two possible different levels of programmation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28282Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268 comprising a charge trapping insulator
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • H01L29/7883Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench (64) and an adjacent second trench (64) in a semiconductor substrate (52), the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region (58) in the substrate and a second source/drain-region (58) in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier (62) in the substrate between the first source/drain region and the second source drain region and forming a first storage element (84) on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line (60) is formed in contact with the first storage element and the second storage element.
PCT/US2007/003248 2006-02-04 2007-02-05 Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes WO2007089949A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US76484706P true 2006-02-04 2006-02-04
US60/764,847 2006-02-04

Publications (2)

Publication Number Publication Date
WO2007089949A2 WO2007089949A2 (en) 2007-08-09
WO2007089949A3 true WO2007089949A3 (en) 2007-11-29

Family

ID=38235446

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/003248 WO2007089949A2 (en) 2006-02-04 2007-02-05 Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes

Country Status (1)

Country Link
WO (1) WO2007089949A2 (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5955767A (en) * 1996-01-24 1999-09-21 Advanced Micro Devices, Inc. Semiconductor device with self-aligned insulator
US6215702B1 (en) * 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
EP1205978A2 (en) * 2000-11-09 2002-05-15 Innotech Corporation Semiconductor memory device, method of manufacturing the same and method of driving the same
EP1300888A1 (en) * 2001-10-08 2003-04-09 SGS-THOMSON MICROELECTRONICS S.r.l. Process for manufacturing a dual charge storage location memory cell
US6639271B1 (en) * 2001-12-20 2003-10-28 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US20040005761A1 (en) * 2002-02-15 2004-01-08 Takumi Shibata Method for manufacturing non-volatile memory device
US6770934B1 (en) * 2003-04-03 2004-08-03 Powerchip Semiconductor Corp. Flash memory device structure and manufacturing method thereof
US20040238852A1 (en) * 2003-05-30 2004-12-02 Dana Lee Array of integrated circuit units with strapping lines to prevent punch through
US6917068B1 (en) * 2002-06-21 2005-07-12 Advanced Micro Devices, Inc. Semiconductor device having conductive structures formed near a gate electrode

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5955767A (en) * 1996-01-24 1999-09-21 Advanced Micro Devices, Inc. Semiconductor device with self-aligned insulator
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
US6215702B1 (en) * 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
EP1205978A2 (en) * 2000-11-09 2002-05-15 Innotech Corporation Semiconductor memory device, method of manufacturing the same and method of driving the same
EP1300888A1 (en) * 2001-10-08 2003-04-09 SGS-THOMSON MICROELECTRONICS S.r.l. Process for manufacturing a dual charge storage location memory cell
US6639271B1 (en) * 2001-12-20 2003-10-28 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US20040005761A1 (en) * 2002-02-15 2004-01-08 Takumi Shibata Method for manufacturing non-volatile memory device
US6917068B1 (en) * 2002-06-21 2005-07-12 Advanced Micro Devices, Inc. Semiconductor device having conductive structures formed near a gate electrode
US6770934B1 (en) * 2003-04-03 2004-08-03 Powerchip Semiconductor Corp. Flash memory device structure and manufacturing method thereof
US20040238852A1 (en) * 2003-05-30 2004-12-02 Dana Lee Array of integrated circuit units with strapping lines to prevent punch through

Also Published As

Publication number Publication date
WO2007089949A2 (en) 2007-08-09

Similar Documents

Publication Publication Date Title
TW578299B (en) A semiconductor memory device using vertical-channel transistors
TW448543B (en) High performance DRAM and method of manufacture
US20120231593A1 (en) Method for fabricating 3d-nonvolatile memory device
TWI280669B (en) Self aligned non-volatile memory cells and processes for fabrication
TWI285954B (en) Semiconductor device and method for manufacturing the same
TW569435B (en) A stacked gate flash memory and the method of fabricating the same
TW541643B (en) Method of fabricating magnetic random access memory operating based on tunnel magnetroresistance effect
TW200521597A (en) Method of fabricating thin film transistor array substrate
TW200828517A (en) Method for making a keyhole opening during the manufacture of a memory cell
TWI238520B (en) Semiconductor device and its manufacturing method
TW200845312A (en) Nonvolatile semiconductor memory and manufacturing method thereof
TW200536044A (en) Semiconductor device and method of making the same
TWI256735B (en) Transistor of semiconductor device and method of manufacturing the same
SG161735A1 (en) Folded bit line dram with vertical ultra thin body transistors
TW200820435A (en) Semiconductor devices with dual-metal gate structures and fabrication methods thereof
TW200515603A (en) Nonvolatile semiconductor memory device with tapered sidewall gate and method of fabricating the same
TW200643960A (en) Methods of operating p-channel non-volatile devices
WO2007103147A3 (en) U-shaped transistor and corresponding manufacturing method
TW508765B (en) Method of forming a system on chip
TW200733306A (en) Method for manufacturing semiconductor device
TW200822345A (en) NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same
TW540141B (en) Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array
TW200816495A (en) Printed non-volatile memory
TW200731415A (en) Methods for forming a semiconductor device
TW560064B (en) Twin MONOS cell fabrication method and array organization

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase in:

Ref country code: DE

122 Ep: pct app. not ent. europ. phase

Ref document number: 07763026

Country of ref document: EP

Kind code of ref document: A2