WO2007089545A3 - Handling processor computational errors - Google Patents
Handling processor computational errors Download PDFInfo
- Publication number
- WO2007089545A3 WO2007089545A3 PCT/US2007/002089 US2007002089W WO2007089545A3 WO 2007089545 A3 WO2007089545 A3 WO 2007089545A3 US 2007002089 W US2007002089 W US 2007002089W WO 2007089545 A3 WO2007089545 A3 WO 2007089545A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- error
- instruction
- computer processor
- handling processor
- computational errors
- Prior art date
Links
- 238000000034 method Methods 0.000 abstract 1
- 238000012544 monitoring process Methods 0.000 abstract 1
- 238000011084 recovery Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
- G06F11/1407—Checkpointing the instruction stream
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Hardware Redundancy (AREA)
- Retry When Errors Occur (AREA)
- Testing And Monitoring For Control Systems (AREA)
- Debugging And Monitoring (AREA)
Abstract
Embodiments include a computer processor-error controller, a computerized device, a device, an apparatus, and a method. A computer processor-error controller includes a monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction. The computer processor-error controller includes an error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/343,927 US8214191B2 (en) | 2005-08-29 | 2006-01-31 | Cross-architecture execution optimization |
US11/343,745 US8209524B2 (en) | 2005-08-29 | 2006-01-31 | Cross-architecture optimization |
US11/343,927 | 2006-01-31 | ||
US11/343,745 | 2006-01-31 | ||
US11/364,130 US7493516B2 (en) | 2005-08-29 | 2006-02-28 | Hardware-error tolerant computing |
US11/364,131 US8375247B2 (en) | 2005-08-29 | 2006-02-28 | Handling processor computational errors |
US11/364,573 US7607042B2 (en) | 2005-08-29 | 2006-02-28 | Adjusting a processor operating parameter based on a performance criterion |
US11/364,130 | 2006-02-28 | ||
US11/364,131 | 2006-02-28 | ||
US11/364,573 | 2006-02-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007089545A2 WO2007089545A2 (en) | 2007-08-09 |
WO2007089545A3 true WO2007089545A3 (en) | 2008-09-25 |
Family
ID=38327877
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/002090 WO2007089546A2 (en) | 2006-01-31 | 2007-01-23 | Adjusting a processor operating parameter based on a performance criterion |
PCT/US2007/002089 WO2007089545A2 (en) | 2006-01-31 | 2007-01-23 | Handling processor computational errors |
PCT/US2007/001904 WO2007089498A2 (en) | 2006-01-31 | 2007-01-24 | Hardware-error tolerant computing |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/002090 WO2007089546A2 (en) | 2006-01-31 | 2007-01-23 | Adjusting a processor operating parameter based on a performance criterion |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/001904 WO2007089498A2 (en) | 2006-01-31 | 2007-01-24 | Hardware-error tolerant computing |
Country Status (1)
Country | Link |
---|---|
WO (3) | WO2007089546A2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030005265A1 (en) * | 2001-06-27 | 2003-01-02 | International Business Machines Corporation | Checkpointing a superscalar, out-of-order processor for error recovery |
US20040174944A1 (en) * | 1999-09-27 | 2004-09-09 | The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantatins | System and method of digital system performance enhancement |
US20050138478A1 (en) * | 2003-11-14 | 2005-06-23 | Safford Kevin D. | Error detection method and system for processors that employ alternating threads |
US20060101303A1 (en) * | 2004-10-22 | 2006-05-11 | International Business Machines Corporation | Self-repairing of microprocessor array structures |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7260742B2 (en) * | 2003-01-28 | 2007-08-21 | Czajkowski David R | SEU and SEFI fault tolerant computer |
US7770034B2 (en) * | 2003-12-16 | 2010-08-03 | Intel Corporation | Performance monitoring based dynamic voltage and frequency scaling |
US7376849B2 (en) * | 2004-06-30 | 2008-05-20 | Intel Corporation | Method, apparatus and system of adjusting one or more performance-related parameters of a processor |
-
2007
- 2007-01-23 WO PCT/US2007/002090 patent/WO2007089546A2/en active Application Filing
- 2007-01-23 WO PCT/US2007/002089 patent/WO2007089545A2/en active Application Filing
- 2007-01-24 WO PCT/US2007/001904 patent/WO2007089498A2/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040174944A1 (en) * | 1999-09-27 | 2004-09-09 | The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantatins | System and method of digital system performance enhancement |
US20030005265A1 (en) * | 2001-06-27 | 2003-01-02 | International Business Machines Corporation | Checkpointing a superscalar, out-of-order processor for error recovery |
US20050138478A1 (en) * | 2003-11-14 | 2005-06-23 | Safford Kevin D. | Error detection method and system for processors that employ alternating threads |
US20060101303A1 (en) * | 2004-10-22 | 2006-05-11 | International Business Machines Corporation | Self-repairing of microprocessor array structures |
Also Published As
Publication number | Publication date |
---|---|
WO2007089546A2 (en) | 2007-08-09 |
WO2007089546A3 (en) | 2008-10-16 |
WO2007089498A3 (en) | 2008-05-08 |
WO2007089498A2 (en) | 2007-08-09 |
WO2007089545A2 (en) | 2007-08-09 |
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