WO2007085834A3 - Etch stop structure - Google Patents

Etch stop structure Download PDF

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Publication number
WO2007085834A3
WO2007085834A3 PCT/GB2007/000253 GB2007000253W WO2007085834A3 WO 2007085834 A3 WO2007085834 A3 WO 2007085834A3 GB 2007000253 W GB2007000253 W GB 2007000253W WO 2007085834 A3 WO2007085834 A3 WO 2007085834A3
Authority
WO
WIPO (PCT)
Prior art keywords
etch stop
layer
stop layer
etching
area
Prior art date
Application number
PCT/GB2007/000253
Other languages
French (fr)
Other versions
WO2007085834A2 (en
Inventor
Anthony J Walton
Wayne Holland
Alan M Gundlach
William Parkes
Original Assignee
Stfc Science & Technology
Anthony J Walton
Wayne Holland
Alan M Gundlach
William Parkes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stfc Science & Technology, Anthony J Walton, Wayne Holland, Alan M Gundlach, William Parkes filed Critical Stfc Science & Technology
Publication of WO2007085834A2 publication Critical patent/WO2007085834A2/en
Publication of WO2007085834A3 publication Critical patent/WO2007085834A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00595—Control etch selectivity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0135—Controlling etch progression
    • B81C2201/014—Controlling etch progression by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A buried etch stop layer (208) for fabricating stepped etched structures has a patterned recess (211). The etch stop layer is buried between etchable first (201) and second (202) layers. The recessed patterned buried etch stop layer can be made by forming a portion of the etch stop layer (204) on one of the etchable layers, etching the recess into it, then wafer bonding the etch stop layer (208) between the first (201) and second (202) layers. Once the buried etch stop layer has been formed, the process for fabricating stepped structures starts with patterning the first layer (201) and etching it to reveal a portion of the recessed area of the etch stop (211). Selective removal by etching of the revealed area is done to remove its entire thickness in the recessed area (211) but only to remove a partial thickness of the remaining revealed area (212). This is followed by selective etching of the revealed area of the second layer, masked by the remaining revealed area (212), so as to transfer a portion of the recess pattern into the second layer, optionally down to a membrane layer (214). This provides improved etch uniformity for stepped etched structures, including those with membranes.
PCT/GB2007/000253 2006-01-25 2007-01-25 Etch stop structure WO2007085834A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0601415.3 2006-01-25
GB0601415A GB0601415D0 (en) 2006-01-25 2006-01-25 Etch stop structure

Publications (2)

Publication Number Publication Date
WO2007085834A2 WO2007085834A2 (en) 2007-08-02
WO2007085834A3 true WO2007085834A3 (en) 2007-10-25

Family

ID=36060768

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2007/000253 WO2007085834A2 (en) 2006-01-25 2007-01-25 Etch stop structure

Country Status (2)

Country Link
GB (1) GB0601415D0 (en)
WO (1) WO2007085834A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5985753A (en) * 1998-08-19 1999-11-16 Advanced Micro Devices, Inc. Method to manufacture dual damascene using a phantom implant mask
US6350700B1 (en) * 2000-06-28 2002-02-26 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6767827B1 (en) * 2003-06-11 2004-07-27 Advanced Micro Devices, Inc. Method for forming dual inlaid structures for IC interconnections

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5985753A (en) * 1998-08-19 1999-11-16 Advanced Micro Devices, Inc. Method to manufacture dual damascene using a phantom implant mask
US6350700B1 (en) * 2000-06-28 2002-02-26 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6767827B1 (en) * 2003-06-11 2004-07-27 Advanced Micro Devices, Inc. Method for forming dual inlaid structures for IC interconnections

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BRAD SMITH: "Partial Via-First Dual Inlaid Integration With Buried Etchstop", IP.COM JOURNAL, IP.COM INC., WEST HENRIETTA, NY, US, 11 January 2002 (2002-01-11), XP013001606, ISSN: 1533-0001 *

Also Published As

Publication number Publication date
WO2007085834A2 (en) 2007-08-02
GB0601415D0 (en) 2006-03-08

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