WO2007084202A3 - Processor core and method for managing branch misprediction in an out-of-order processor pipeline - Google Patents

Processor core and method for managing branch misprediction in an out-of-order processor pipeline Download PDF

Info

Publication number
WO2007084202A3
WO2007084202A3 PCT/US2006/041614 US2006041614W WO2007084202A3 WO 2007084202 A3 WO2007084202 A3 WO 2007084202A3 US 2006041614 W US2006041614 W US 2006041614W WO 2007084202 A3 WO2007084202 A3 WO 2007084202A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
instruction
pipeline
portion
processor
misprediction
Prior art date
Application number
PCT/US2006/041614
Other languages
French (fr)
Other versions
WO2007084202A2 (en )
Inventor
Karagada Ramarao Kishore
Kjeld Svendsen
Vidya Rajagopalan
Maria Ukanwa
Original Assignee
Mips Tech Inc
Karagada Ramarao Kishore
Kjeld Svendsen
Vidya Rajagopalan
Maria Ukanwa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384Register renaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3857Result writeback, i.e. updating the architectural state
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3857Result writeback, i.e. updating the architectural state
    • G06F9/3859Result writeback, i.e. updating the architectural state with result invalidation, e.g. nullification
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Abstract

A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.
PCT/US2006/041614 2005-10-31 2006-10-26 Processor core and method for managing branch misprediction in an out-of-order processor pipeline WO2007084202A3 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11261654 US7711934B2 (en) 2005-10-31 2005-10-31 Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US11261655 US7734901B2 (en) 2005-10-31 2005-10-31 Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US11/261,655 2005-10-31
US11/261,654 2005-10-31

Publications (2)

Publication Number Publication Date
WO2007084202A2 true WO2007084202A2 (en) 2007-07-26
WO2007084202A3 true true WO2007084202A3 (en) 2007-10-04

Family

ID=38267515

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/041614 WO2007084202A3 (en) 2005-10-31 2006-10-26 Processor core and method for managing branch misprediction in an out-of-order processor pipeline

Country Status (1)

Country Link
WO (1) WO2007084202A3 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8635437B2 (en) * 2009-02-12 2014-01-21 Via Technologies, Inc. Pipelined microprocessor with fast conditional branch instructions based on static exception state
WO2013100999A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Enabling and disabling a second jump execution unit for branch misprediction

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US6079014A (en) * 1993-12-02 2000-06-20 Intel Corporation Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
US6249862B1 (en) * 1996-05-17 2001-06-19 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US6760835B1 (en) * 2000-11-22 2004-07-06 Lsi Logic Corporation Instruction branch mispredict streaming

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6079014A (en) * 1993-12-02 2000-06-20 Intel Corporation Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US6249862B1 (en) * 1996-05-17 2001-06-19 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US6760835B1 (en) * 2000-11-22 2004-07-06 Lsi Logic Corporation Instruction branch mispredict streaming

Also Published As

Publication number Publication date Type
WO2007084202A2 (en) 2007-07-26 application

Similar Documents

Publication Publication Date Title
US5463745A (en) Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system
US6496925B1 (en) Method and apparatus for processing an event occurrence within a multithreaded processor
US5898853A (en) Apparatus for enforcing true dependencies in an out-of-order processor
US6883107B2 (en) Method and apparatus for disabling a clock signal within a multithreaded processor
US6889319B1 (en) Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US6279105B1 (en) Pipelined two-cycle branch target address cache
US7003629B1 (en) System and method of identifying liveness groups within traces stored in a trace cache
US5649138A (en) Time dependent rerouting of instructions in plurality of reservation stations of a superscalar microprocessor
US20050125632A1 (en) Transitioning from instruction cache to trace cache on label boundaries
US20020073301A1 (en) Hardware for use with compiler generated branch information
US6934865B2 (en) Controlling a processor resource based on a compile-time prediction of number of instructions-per-cycle that will be executed across plural cycles by the processor
US6543002B1 (en) Recovery from hang condition in a microprocessor
US20070204135A1 (en) Distributive scoreboard scheduling in an out-of order processor
US20030005266A1 (en) Multithreaded processor capable of implicit multithreaded execution of a single-thread program
US6662294B1 (en) Converting short branches to predicated instructions
US5892934A (en) Microprocessor configured to detect a branch to a DSP routine and to direct a DSP to execute said routine
US20050172277A1 (en) Energy-focused compiler-assisted branch prediction
US7133969B2 (en) System and method for handling exceptional instructions in a trace cache based processor
US6209086B1 (en) Method and apparatus for fast response time interrupt control in a pipelined data processor
US7711929B2 (en) Method and system for tracking instruction dependency in an out-of-order processor
US7197630B1 (en) Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation
US20050216714A1 (en) Method and apparatus for predicting confidence and value
US5799180A (en) Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken
US20090113182A1 (en) System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing Unit
US20070288725A1 (en) A Fast and Inexpensive Store-Load Conflict Scheduling and Forwarding Mechanism

Legal Events

Date Code Title Description
NENP Non-entry into the national phase in:

Ref country code: DE

122 Ep: pct app. not ent. europ. phase

Ref document number: 06849307

Country of ref document: EP

Kind code of ref document: A2