WO2007080529A1

WO2007080529A1 - Shielded cross-tie coplanar waveguide structure

Info

Publication number: WO2007080529A1
Application number: PCT/IB2007/050038
Authority: WO
Inventors: Lukas F. Tiemeijer
Original assignee: Nxp B.V.
Priority date: 2006-01-09
Filing date: 2007-01-05
Publication date: 2007-07-19
Also published as: TW200737587A

Abstract

The present invention relates to a coplanar waveguide structure of a cross-tie type integrated on a substrate, wherein connection means are provided for electrically connecting at least one conductor of the coplanar waveguide pattern to said cross-tie periodic conductor pattern, so as to set the cross-tie periodic conductor pattern to a predetermined reference potential. Thereby, a grounding or a full shielding can be obtained to reduce signal loss and dispersion in high data rate on-chip signal transport, as well as reduce size and increase performance.

Description

Shielded cross-tie coplanar waveguide structure

The present invention relates to a coplanar waveguide structure of a cross-tie type integrated on a substrate.

Reduction of circuit dimensions in both hybrid and monolithic microwave integrated circuits (MMICs) is important from cost and reliability point of view. Passive devices, especially those designed with distributed transmission lines occupy large amounts of space. Slow- wave propagation by separating electric and magnetic energies has been developed to reduce transmission-line length for a given insertion phase. Several periodic structures such as the so-called cross-tie coplanar waveguide (CT-CPW) as described for example in S. Seki et al., "Cross-Tie Slow- Wave Coplanar Waveguide on Semi-Insulating GaAs Substrates", Electronics Letters, Vol. 17, pp. 940-941, 1981 have been proposed to improve the performance of slow- wave transmission lines.

Fig. 2 shows schematic cross sections of a conventional CT-CPW structure as disclosed for example in the above prior art. According to Fig. 2, the slow-wave transmission line of this conventional CT-CPW is made of small alternating sections as shown in the two cross sections. The alternating sections A and B extend by a small amount of several micrometers (e.g. 10 μm) in the propagation direction of the propagating wave, i.e., perpendicular to the cross sectional plane of Fig. 2. Both alternating sections comprise a substrate 40, e.g. a semi-isolating GaAs substrate, on which an isolation layer 30, e.g. a dielectric layer or sheet, is provided. On top of this isolation layer 30, a coplanar waveguide pattern comprising a central conductor 10 arranged in a substantially central portion between two outer conductors 12 is provided. Additionally, section A comprises a bottom conductor or so-called cross-tie bar 50 of a cross-tie periodic conductor pattern which is formed under the coplanar waveguide pattern and separated by the isolation layer 30. Due to this cross-tie pattern, section A forms a low-impedance section, while section B forms a high-impedance section.

Slow- wave propagation is possible by spatially separated storage of electric energy and magnetic energy. The structure of Fig. 2 forms a periodic connection of two kinds of planar transmission lines, sections A and B, with different characteristic impedances. If the spatial period of such a connection is small compared with the resultant wavelength, and if the characteristic impedance of section A is much smaller than the characteristic impedance of section B, electric energy is mainly stored in section A, while magnetic energy is mainly stored in section B, which results in spatially separated energy storage.

The above on-chip slow- wave transmission line structure of Fig. 2 is also attractive to realize filter or impedance matching circuits at microwave frequencies. Key performance parameters are the slow- wave factor (SWF) which should be as large as possible to facilitate miniaturization, the line impedance which should be around 50 Ω, and the loss which should be as low as possible (typically expressed in decibel (dB) per guided wavelength). This conventional CT-CPW shows a loss of 5 to 7 dB per guided wavelength on a semi-isolating GaAs substrate.

The cross-tie conductor pattern may be formed by photo-etching of a vacuum- deposited Al film on a Cr-doped GaAs substrate, and then RF-sputtered alumina can be used as the dielectric sheet forming the insulating layer 30. The conventional CPW pattern can then be formed by vacuum deposition of Au.

However, the conventional CT-CPW pattern shown in Fig. 2 is not suitable for use in standard Silicon IC processes, due to the fact that the propagating wave will then see lossy silicon, which leads to undesirable high losses.

It is therefore an object of the present invention to provide an improved CT- CPW structure which is compatible with standard IC process technology.

This object is achieved by a coplanar waveguide structure as claimed in claim 1.

Accordingly, connection means are provided for electrically connecting at least one conductor of the coplanar waveguide pattern to the cross-tie periodic conductor pattern. This provides the advantage that the cross-tie periodic conductor pattern can be set to a predetermined reference potential, e.g. ground potential or any other reference potential, so as to achieve a shielding function of the cross-tie pattern. Thereby, the bottom conductor of the cross-tie pattern of Fig. 2 is no longer floating, so that capacitive coupling to the substrate can be prevented and losses caused on the conductive substrate, such as silicon, can be reduced significantly. The connection means may comprise stack means arranged for spanning intermediate metal layers, so as to achieve the desired electrical connection.

Furthermore, the coplanar waveguide pattern may comprise at least one central conductor arranged between two outer conductors, and said connecting means may be arranged to connect cross-tie bars of said cross-tie periodic conductor pattern to said outer conductors. Such a structure enables straight forward and simple manufacturing as the outer conductors merely have to be connected by vertical metallic elements or stacks to the lower cross-tie pattern. Optionally, the coplanar waveguide pattern may be a differential pattern with two adjacent central conductors. According to a first aspect, the cross-tie periodic conductor pattern may be an intermittent pattern in a direction of wave propagation with cross-tie bars separated by a predetermined distance corresponding to the length of the other section.

According to a second aspect, the cross-tie periodic conductor pattern may be a continuous pattern in a direction of wave propagation, wherein cross-tie bars are periodically arranged at first and second distances from said coplanar waveguide pattern to provide full shielding.

Both above aspects provide the advantage that, due to the obtained pattern ground shield, no return current is flowing underneath the central conductor.

At least one of the cross-tie periodic conductor patterns may be made of polysilicon material. Furthermore, the coplanar waveguide structure can be integrated in a CMOS-type integrated circuit structure. Additionally, the coplanar waveguide structure may be integrated in a PCB-(Printed Circuit Board)-type structure.

The present invention will now be described based on preferred embodiments with reference to the accompanying drawings in which:

Fig. 1 shows schematic cross sections of two periodic sections of a coplanar waveguide structure according to the first preferred embodiment;

Fig. 2 shows schematic cross sections of two periodic sections of a conventional coplanar waveguide structure according to the prior art;

Fig. 3 shows schematic cross sections of periodic sections of a coplanar waveguide structure according to the second preferred embodiment;

Fig. 4 shows a schematic cross section of one of the periodic sections of a differential coplanar waveguide structure according to a third preferred embodiment; Fig. 5 shows a diagram indicating characteristic impedances versus frequency of a conventional microstrip waveguide and the coplanar waveguide structure according to the first preferred embodiment;

Fig. 6 shows a diagram indicating slow- wave factors versus frequency of a conventional microstrip waveguide in comparison to the coplanar waveguide structure according to the first preferred embodiment;

Fig. 7 shows a diagram indicating transmission line attenuation versus frequency of a conventional microstrip waveguide and the coplanar waveguide structure according to the first preferred embodiment; and Fig. 8 shows a diagram indicating transmission line loss versus frequency of conventional microstrip and coplanar waveguide structures in comparison to the coplanar waveguide structure according to the first preferred embodiment.

In the following, the preferred embodiments will be described in case of their realization in a radio frequency (RF) (Bi-)CMOS IC process.

Fig. 1 shows cross sections of respective periodic sections A and B of a grounded cross-tie CPW (GCT-CPW) according to the first preferred embodiment. In the exemplary RF (Bi-)-CMOS IC process, the CPW would typically be realized in the top metal level or layer, whereas the cross-tie periodic conduction pattern can be realized in an insulating layer 30 made of polysilicon or the like, or in a first metal layer Ml. The cross-tie periodic conductor pattern is only provided in section A, so that an intermittent pattern with cross-tie bars 50 separated in the direction of propagation of the waveguide is obtained. The distance between the cross-tie bars corresponds to the length of section B. In the conventional CT-CWP of Fig. 2 the bottom conductor 50 in section A is floating. It can easily be seen that there is a significant capacitive coupling to the substrate 40, which is known to cause losses on conductive substrates like silicon.

In contrast thereto, section A of the first preferred embodiment shown in Fig. 1 comprises outer conductors 22 which are electrically connected to the bottom conductor of the cross-tie periodic conductor pattern 50. In a specific example, the electrical connection between the outer conductors 22 and the cross-tie bars of the cross-tie periodic conductor pattern 50 may be achieved by providing via stacks spanning all intermediate metal layers of the integrated structure. When the length of sections A and B are reduced to less than a micron and brought close to the minimum line width allowed in IC processes, the capacitive field lines originating from the central conductor 10 in section B will no longer be able to pass the slits between the cross-tie bars, and capacitive coupling to the substrate 40 will be significantly reduced.

As an alternative option, Fig. 3 shows cross sections of two periodic alternating sections A and B in a fully shielded cross-tie CPW (FSCT-CPW) according to the second preferred embodiment. In the example of an RF (Bi-)CMOS IC process, the CPW again can be realized in the top metal level or layer, whereas the cross-tie periodic conductor pattern 50 is now realized in the metal layer Ml in section A, and in the insulating layer 30 (poly layer) in section B. Thereby, the required different characteristic impedances of the waveguide can be achieved.

It is to be noted that since in the GCT-CPW structure of the first preferred embodiment and the FSCT-CPW structure of the second preferred embodiment the length of sections A and B can be reduced to less than one micron, their behavior can no longer be described with the conventional theory provided in the initially mentioned prior art document. Instead, the patterned ground shield obtained by the cross-tie periodic conductor pattern should be regarded as a high K dielectric, since there is no return current anymore flowing underneath the central conductor 10. Nevertheless, the behavior can be modeled accurately using this assumption.

Accordingly, in the second preferred embodiment of Fig. 3, the cross-tie periodic conductor pattern comprises two different cross-tie bars 50, 52, wherein the cross-tie bar 50 of section A is arranged in the first metal layer Ml and has a larger distance from the central conductor 10 as compared to the cross-tie bar 52 of section B, which is located at a smaller distance from the central conductor 10 and provided in the insulation layer 30. Hence, in section B, the connection element or portion of the outer conductors 24 is shorter than the connection element or portion of the outer conductors 22 of section A.

Fig. 4 shows a cross section of an example of a differential GCT-CPW structure (section A) which has been made in a CMOS 090 process and which performance will be compared later against a conventional differential CPW in a microstrip configuration. In Fig. 4, different metal layers Ml to M6 provided in this IC process technology are shown and an upper aluminum cap 70 is provided on each of the outer connectors 22 which form an integrated electrically connecting structure comprising via stacks 80 spanning all the intermediate metal layers M2 to M5. Thereby, connection elements are formed for connecting the outer conductors 22 with the cross-tie bar 50 formed in the first metal layer Ml. In the example of Fig. 4, the width W of two central conductors 10-1 and 10-2 which form the differential waveguide structure may be selected to W = 3.5 μm, while the two central conductors 10-1 and 10-2 may be arranged at a distance of S = 5 μm. The total width of the coplanar waveguide structure then amounts to W_tot = 70 μm. In the preferred embodiment, the differential GCT-CPW is realized by replacing the conventional Ml shielding plate by polysilicon bars 50 with a width of 1 μm in the direction of propagation (i.e. perpendicular to the plane of Fig. 4) and at a spacing of 1 μm. However, it is clear that different metallization layers and track widths and spacings can be chosen depending on the required line characteristic impedance ZO, slow- wave factor SWF and loss. Moreover, the differential transmission line structure with two central conductors 10-1 and 10-2 is an optional example, the same principles apply for single transmission lines as well as for data busses employing many parallel lines.

In the following, the performance of the differential GCT-CPW of the third preferred embodiment is compared to a conventional differential CPW using the diagrams of Figs. 5 to 8. The measured data of both CPWs are shown by empty and filled squares, while results obtained from two-dimensional electromagnetic simulations with commercial software are shown with continuous lines. For the differential GCT-CPW structure of the third preferred embodiment, the polysilicon cross-tie bars 50 were modeled by a 20 μm-thick dielectric element with a relative permeability ε_r of 100. Fig. 5 shows a diagram of measuring and simulation results of the characteristic impedance ZO versus frequency for a common mode propagation, i.e. both central conductors 10-1 and 10-2 are excited in phase. As can be gathered from Fig. 5, in the frequency range from 1 to 10 GHz the characteristic impedance ZO is less frequency dependent in the proposed differential GCT-CPW structure as indicated by the filled squares. For circuit design, this means that signal distortion due to dispersion can be significantly reduced and broadband impedance matching can be achieved more easily.

Fig. 6 shows a diagram indicating measuring and simulation results of the slow- wave factor SWF versus frequency. As can be seen, the slow- wave factor SWF has increased in the proposed differential GCT-CPW structure from a value of approximately 2 to a value of approximately 3. Moreover, similar to the characteristic impedance ZO, the slow- wave factor SWF has become much less frequency-dependent.

In the following, transmission line attenuation and loss versus frequency are compared based on Figs. 7 and 8, respectively Fig. 7 shows a diagram of measuring and simulation results of the transmission line attenuation A in dB per mm (dB/mm) versus frequency for a common mode propagation. Furthermore, Fig. 8 shows a diagram of measuring and simulation results of the transmission line loss in dB per guided wavelength (dB/Lg) versus frequency for a common mode propagation, wherein additional measurement points (black dots) obtained from the conventional CT-CPW structure of Fig. 2 have been added to indicate improvements achieved by the proposed grounded structure. As can be gathered from Figs. 7 and 8, transmission line loss and attenuation can be reduced substantially in the proposed GCT- CPW structures according to the preferred embodiments, to provide a significantly better performance. The proposed GCT-CPW structures might thus be preferable for certain applications due to its lower loss instead of its larger SWF.

Figs. 5 to 8 also show that the measurement results basically reflect the results of simulation. Similar results can be obtained for the differential mode of propagation where out-of-phase signals are applied to the central conductors 10-1 and 10-2. Of course, similar results can also be obtained for non-differential coplanar waveguide structures according to the first and second preferred embodiments.

As shown above, the proposed GCT-CPW and FSCT-CPW transmission line structures are attractive to reduce signal loss and dispersion in high data-rate on-chip signal transport, as well as to reduce size and increase performance of on-chip impedance matching stubs and transmission line based filters. Furthermore, since for these new transmission line layouts the capacitance and loss per unit length are predominantly set by the width of the central conductor 10 while the inductance per unit length is set by the width to spacing ratio between this central conductor 10 and the outer conductors 22, 24, the characteristic impedance ZO and the attenuation loss can be set independently by changing these widths and spacings. Therefore, compared to conventional microstrip lines where inductance and capacitance per unit length are strongly coupled, and where the thickness of the dielectric sets the track widths for a given impedance, a significant larger design space is available for a given IC process back-end stack.

In summary, a coplanar waveguide structure of a cross-tie type integrated on a substrate has been described, wherein connection means are provided for electrically connecting at least one conductor of the coplanar waveguide pattern to said cross-tie periodic conductor pattern, so as to set the cross-tie periodic conductor pattern to a predetermined reference potential. Thereby, a grounding or full shielding can be obtained to a reduced signal loss and dispersion in high data rate on-chip signal transport, as well as reduced size and increased performance.

It is noted that the present invention is not restricted to the above preferred embodiments. Rather, any type of electrical connection, connector or conductor can be used to provide the grounded cross-tie bar or fully shielded cross-tie periodic conductor pattern. The preferred embodiments may thus vary within the scope of the attached claims. Finally but yet importantly, it is noted that the term "comprises" or

"comprising" when used in the specification including the claims is intended to specify the presence of stated features, means, steps or components, but does not exclude the presence or addition of one or more other features, means, steps, components or group thereof. Further, the word "a" or "an" preceding an element in a claim does not exclude the presence of a plurality of such elements. Moreover, any reference sign does not limit the scope of the claims.

Claims

CLAIMS:

1. A coplanar waveguide structure of a cross-tie type integrated on a substrate (40), said waveguide structure comprising: a coplanar waveguide pattern (10, 22, 24; 10-1, 10-2, 22); a cross-tie periodic conductor pattern (50; 50, 52) arranged below said coplanar waveguide pattern; a dielectric separation layer (30) arranged between said coplanar waveguide pattern and said cross-tie periodic conductor pattern; and connection means (22; 24; 80) for electrically connecting at least one conductor (22; 24) of said coplanar waveguide pattern to said cross-tie periodic conductor pattern, so as to set said cross-tie periodic conductor pattern to a predetermined reference potential.

2. A waveguide structure according to claim 1, further comprising stack means (80) arranged for spanning intermediate metal layers (M2 - M5).

3. A waveguide structure according to claim 1 or 2, wherein said coplanar waveguide pattern comprises at least one central conductor (10; 10-1, 10-2) arranged between two outer conductors (22; 24), and wherein said connections means (80) are arranged to connect cross-tie bars (50) of said cross-tie periodic conductor pattern to said outer conductors.

4. A waveguide structure according to claim 3, wherein said coplanar waveguide pattern is a differential pattern with two adjacent central conductors (10-1, 10-2).

5. A waveguide structure according to any one of the preceding claims, wherein said cross-tie periodic conductor pattern is an intermittent pattern in a direction of waveguide propagation with cross-tie bars (50) separated by a predetermined distance.

6. A waveguide structure according to any one of claims 1 or 4, wherein said cross-tie periodic conductor pattern is a non-separated continuous pattern in a direction of waveguide propagation, wherein cross-tie bars (50, 52) are periodically arranged at first and second distances from said coplanar waveguide pattern to provide full shielding.

7. A waveguide pattern according to any one of the preceding claims, wherein at least one of said cross-tie periodic conductor patterns is made of polysilicon material.

A waveguide structure according to any one of the preceding claims, wherein said coplanar waveguide structure is integrated in a CMOS-type or Bi-CMOS-type integrated circuit structure.

8. A waveguide structure according to any one of claims 1 to 6, wherein said coplanar waveguide structure is integrated in a PCB-type structure.