WO2007072538A1

WO2007072538A1 - Queue scheduling device, queue scheduling method and information relay device

Info

Publication number: WO2007072538A1
Application number: PCT/JP2005/023262
Authority: WO
Inventors: Daisuke Namihira
Original assignee: Fujitsu Limited
Priority date: 2005-12-19
Filing date: 2005-12-19
Publication date: 2007-06-28

Abstract

A dequeue execution section basically shifts to readout a next queue after dequeuing one frame. When a deficit value controlled in a deficit processing section becomes 0 in queue, the queue is excluded from a scheduling (dequeue) subject but a deficit value that is not less than 0 in queue, i.e., a queue that still includes a frame, is only subjected to the execution of a dequeue in turn. When all the queues are excluded from scheduling subjects, the deficit processing section resets the deficit value by a quantum value and returns to an initial state. A burst size at the dequeue can be suppressed to be one frame.

Description

Specification

Queue scheduling apparatus, queue scheduling method, information relay apparatus

TECHNICAL FIELD [0001] The present invention relates to a queue scheduling device, a queue scheduling method, and an information relay device, for example, a technique effective when applied to control of communication quality (QoS: Quality of Service) on an information network.

Background art

[0002] For example, as a scheduling technique for QoS control implemented in information relay devices such as routers, the output bandwidth ratio between queues is defined and scheduling is performed at that ratio in order to achieve minimum bandwidth guarantee. There is a scheduling technique called Deficit Round Robbin (DRR).

[0003] The outline of the DRR method is as follows.

The DRR read control unit 1002 performs the following [Step S1] to [Step S5] for a plurality of queues 1001 of l to n as in the reference technique of FIG.

[0004] [Step S 1] Each queue is assigned a deficit value and a quantum value. The Quantum value is a value determined by the bandwidth ratio of each queue, and the Deficit value is the initial value of the Quantum value, and the frame length is subtracted every time scheduling is used.

[0005] [Step S2] Start from queue 1 and dequeue if there is a frame in cue 1 with a force greater than the deficit value power SO of cue 1 (read the cue force frame), and the deficit value in the dequeued frame Subtract long.

[0006] [Step S3] The above [Step S2] is repeated until the Deficit value is 0 or less or there are no more frames.

[Step S4] When the Deficit value is 0 or less or there are no more frames, the process moves to the next queue and executes the above-mentioned [Step S2] to [Step S3].

[0007] [Step S5] When the last queue n is completed, the Quantum value of each queue is added to the Deficit value of queues l to n, respectively. At this time, the deficit value becomes Qua If it becomes larger than the ntum value, the deficit value is set to the same value as the Quantum value. Then, return to queue 1 and execute from [Step S2].

[0008] In this DRR method, of the queues, the larger the set Quantum value, the more frames are dequeued successively. Therefore, by setting the Quantum value appropriately between each queue, the bandwidth ratio between queues can be set, and the minimum bandwidth guarantee is realized.

[0009] However, the Quantum value is the maximum frame length MTU (Maximum

A value greater than (Transfer Unit) must be set. If it is Ethernet (registered trademark), but if jumbo frames are allowed, the MTU will increase accordingly.

[0010] Here, in the DRR method, dequeue is continued until the deficit value reaches 0 in a specific queue. Therefore, the burst size (Burst size: —continuously in one dequeue from one queue) The length of the data to be read). However, since the Quantum value must be greater than or equal to the MTU value, the minimum setting value for guaranteed minimum bandwidth must be the same as the MTU value. Therefore, the maximum setting value for guaranteed minimum bandwidth is the minimum setting value X bandwidth ratio.

[0011] Here, assuming that the minimum setting value of minimum bandwidth guarantee is 100 kilobits Z seconds (Kbps) and the maximum setting value is 1 gigabit Z seconds (Gbps), Quantum The value must be 10,000 times the MTU value! /. If MTU is 1.5 kilobytes (Kbyte) of Ethernet (registered trademark), the Quantum value is 15 megabytes (Mbyte), that is, a burst amount (size) of 15 Mbytes. This is a very large burst amount and causes the following problems.

[0012] As a reference technique, as shown in FIG. 2, it is assumed that there is a relay apparatus having a configuration in which a relay processing chip 1000 (chip 1) and a relay processing chip 2000 (chip 2) are mounted. In this case, the relay processing chip 1000 and the relay processing chip 2000 may be different devices! /. In Figure 2, 10G indicates the line speed of 10Gbps, and 1G indicates the line speed of IGbps. The relay processing chip 1000 is mounted with the queue 1001 and the DRR read control unit 1002 described above, and a frame arrives at each of the queues 1001 at a line speed of 10 G. The processing chip 2000 outputs a frame at 10G.

[0014] It is assumed that the destination of the frame is determined in the previous stage of entering the relay processing chip 1000. The method is determined by each of the relay processing chip 1000 or the relay processing chip 2000, but it is not related to the present invention!

[0015] The relay processing chip 1000 performs DRR or other QoS processing, passes it to the relay processing chip 2000 through the 10G line, and stores it in the transmission buffer 2001 (for example, queue) of the destination circuit in the relay processing chip 2000. The frames shall be transmitted sequentially to the line.

[0016] Now, consider a mode in which a 1G X 10 flow comes to the relay processing chip 1000 and the 1G flow is distributed in 10 directions from the end of the relay processing chip 2000.

If DRR is executed on the flow from relay processing chip 1000 to relay processing chip 2000, and the above Quantum value is set, relay processing chip 2000 has a flow of lOGbps on each lGbps line. In this case, only 15Mbyte is transferred.

[0017] In this case, since there are ten flows, the result is a transfer amount of lGbps. However, since the burst amount is too large, the dequeue interval of multiple packets (frames) held in individual queues will vary greatly depending on the burst size of other queues, and it will continue in one queue. Variations in the dequeue interval (ie, transmission interval) between multiple packets, the so-called jitter, is becoming very large.

That is, 15 Mbytes are transmitted to the transmission buffer 2001 prepared for each lGbps line of the relay processing chip 2000 at the lOGbps speed. Since it goes out at lGbps speed, 13.5Mbyte transmission buffer 2001 is required for each lGbps line as a result.

[0019] If the transmission buffer 2001 having such a capacity is provided in each line unit, the chip size of the relay processing chip 2 000 is increased, and the amount of memory to be mounted in the periphery increases. There are technical problems that the product is very large and the cost is very high.

[0020] Also, if the capacity of the transmission buffer 2001 is not increased, the transmission buffer 2001 overflows and frames are discarded, and the line speed of lGbps is fully used for each line.

[0021] In addition, since scheduling by DRR guarantees the minimum bandwidth and limits the maximum bandwidth, that is, not shaving, the shaving function is implemented separately from DRR. By combining this shaving process, the burst size can be reduced, but the minimum bandwidth guarantee cannot be maintained. An example is shown below.

[0022] First, an example in which shaving is not performed for comparison is shown below.

As shown in FIG. 3, there are three queues 1001 of queue 1 to queue 3, and the output line bandwidth from the DRR read control unit 1002 is lGbps. For simplicity, assume that the MTU of the line is 1 and all incoming packets are 1 in length. At this time, the minimum bandwidth guarantee for queues 1 to 3, queue 1: 500 megabits Z seconds (Mbps)

Queue 2: 350Mbps

Queue 3: 150Mbps

If the minimum guaranteed bandwidth is 50 Mbps, the Quantum values for each queue are 10, 7, and 3, respectively.

At this time, if the shaving is not performed in each queue 1001, the scheduling result in the DRR read control unit 1002 is as shown in FIG.

In Fig. 4, “o” in the queue output means that the packet was output to the subsequent stage of the queue power. The deficit value indicates what the deficit value is after the packet is sent out. In addition, Fig. 4 is shown assuming that the time taken to flow a packet of length 1 downstream is 1, and that scheduling is started from time t = 0.

In FIG. 4, the DRR read control unit 1002 first starts scheduling from queue 1. Since the initial value of the deficit value is 10, scheduling is performed from queue 1 from time t = 0 to 9, and the deficit value becomes 0 from the scheduling result at time t = 9, so the process moves to the next queue.

[0025] From time t = 10, scheduling is performed from the next queue 2 until time t = 16. Go to queue 3 in the same way. Similarly for queue 3, scheduling is performed from time t = 17 to 19, and all queues have been completed, so the deficit value is cleared (quantum value Vq is added), and scheduling is performed again from time t = 20.

[0026] In this example, DRR has a round from time t = 0 to 19, and the bandwidth can be calculated by the ratio of the total amount of packets output. Since the line speed on the output side of the DRR read control unit 1002 is IGbps, when it is divided by 20, one “◯” in Fig. 4 corresponds to 50Mbps.

[0027] Therefore, queue 1 has 10 "O" and 500 Mbps, queue 2 has 7 "O" and 350 Mbps, and queue 3 has 3 "O" and 150 Mbps. I understand that. It can also be seen that queue 1 with a large deficit value affects the burst size accordingly.

[0028] Next, with reference to FIG. 5, a case will be described in which a situation is assumed in which each of the three queues 1 to 3 is performing shaving.

By performing shaving, the DRR read control unit 1002 cannot see the packet (the packet is not in the queue) even though the packet is in the queue 1001. Shaving is realized by adjusting the timing when packets actually existing in this queue are visible from the DRR read control unit 1002 side.

[0029] When shave is performed strictly, there is no burst size (the output time is completely adjusted in units of packets), but in reality, a burst size is generated to some extent. In addition, in the leaky packet method and token packet method, which are basically used in the shaping method, an allowable burst size can be specified.

[0030] That is, the maximum bandwidth is output up to the burst size, and then transmission is performed according to the set bandwidth. If this burst size is reduced, the burst amount can be suppressed. The tolerance to congestion with other queues is weakened, and even when the line is free, the maximum bandwidth is not fully used. Conversely, increasing the burst size increases resistance to congestion with other queues, but increases the burst size.

In the example of FIG. 5, the burst size by queue shaving is set to 3. In addition, the shaving band of each queue

Queue 1: 500Mbps Queue 2: 500Mbps

Queue 3: 300Mbps

And The value of the bandwidth is not particularly meaningful, and is simply set to a value that is more than the minimum bandwidth guaranteed value.

[0032] The scheduling result in this example is as follows.

As in the previous example in Fig. 4, scheduling is first performed from queue 1. Scheduling is also performed at time t = 0, 1, and 2 for queue 1 and scheduling is possible because the deficit value is 7, but shaving is performed in the previous stage and the burst size is 3, so DRR read controller 1002 Appears to have no packets in queue 0.

[0033] Therefore, the scheduling of queue 0 ends here, and the process moves to the next queue. Similarly for queue 2, the deficit value is still 0 at time t = 5! / ヽ, but scheduling ends here due to the shaving burst size. In queue 3, the deficit value reaches 0 at time t = 8, so scheduling ends. Since all the queues have been completed, the deficit value is cleared (quantum value calculation), and scheduling is performed again from time t = 9.

[0034] In the example of Fig. 5, DRR is a cycle from time t = 0 to 8, and the bandwidth can be calculated in the same way by the ratio of the total amount of packets output, and queue 1, queue 2, The bandwidth power S of queue 3 is all 333 Mbps. Queue 3 sends 333 Mbps to the minimum bandwidth of 150 Mbps, so there is no problem, but queue 1 outputs only 333 Mbps even though queue 2 has the minimum bandwidth of 500 Mbps and queue 2 has the minimum bandwidth of 350 Mbps. In other words, the minimum bandwidth guarantee is not observed.

[0035] This is because the burst size setting for shaving is a problem. In this example, the burst size should be set to at least 10 !,! /, Ken! / ヽ (not limited to this example, Quantum A burst size greater than or equal to the value must be set).

[0036] Therefore, if shaving is implemented and the burst size of DRR is reduced, the minimum bandwidth guarantee cannot be realized. Eventually, there is no choice but to increase the shaving burst size. In such a case, shaving is performed, and even the accuracy of the shaving is not good enough.

[0037] It should be noted that Patent Document 1 describes a packet from each buffer (queue) in DRR control. A contention control technique is disclosed in which a granularity value, which is a control parameter for determining whether or not data can be read, is set based on statistical observation information regarding the packet length.

[0038] However, although the technique of Patent Document 1 guarantees the fairness of the throughput between the buffers, it is expected that it will be difficult to guarantee the minimum bandwidth of each buffer and to suppress the burst amount. Is done.

Patent Document 1: Japanese Patent Laid-Open No. 2001-223740

Disclosure of the invention

[0039] An object of the present invention is to provide a queue scheduling technique that can reduce the burst amount while maintaining the set bandwidth of each queue.

Another object of the present invention is to provide a queue scheduling technique that does not deteriorate the shaving accuracy even when used together with the implementation of shaving.

[0040] Another object of the present invention is to provide a queue scheduling technique capable of more evenly scheduling flows for each queue.

Another object of the present invention is to provide a queue scheduling technique capable of constructing an information relay apparatus at a lower cost.

Another object of the present invention is to provide an information relay apparatus capable of realizing stable bandwidth control and shaping according to the attributes of communication data at a low cost.

The first aspect of the present invention provides a plurality of queues that hold communication data in the order of arrival and an initial value that is provided corresponding to each of the queues and that corresponds to the attribute of the communication data held in the queue. Storage means set as a value;

An operation of sequentially reading out the communication data from the queue whose management value is 0 or more and subtracting the length of the communication data read out from the queue power from the management value corresponding to the queue;

An operation of setting the initial value as the management value for all the storage means when there is no corresponding queue whose management value is 0 or more;

Queue control means for executing

A queue scheduling apparatus is provided.

[0042] A second aspect of the present invention is the queue scheduling apparatus according to the first aspect. The initial value provides a queue scheduling apparatus that is set according to a minimum guaranteed bandwidth allocated to each of the queues.

[0043] A third aspect of the present invention provides the queue scheduling apparatus according to the first aspect, further comprising a shaving control means for shaving the communication data held in the queue.

[0044] According to a fourth aspect of the present invention, in the queue scheduling apparatus according to the first aspect, the queue control means includes:

Management value calculation means provided in each of the queues;

Dequeue execution means for sequentially trying to read the communication data for a plurality of the queues,

The dequeue execution means is

A function of executing the reading of the communication data by setting the read request signal output to the management value calculation means to be true when the first readable signal output to each of the management value calculation means is true; ,

When all of the second readable signals output from the individual management value calculation means and indicating the remaining presence or absence of the communication data in the queue are false, all the management value calculation means A function that outputs an initialization signal that instructs setting of the initial value to be true, and

The management value calculation means includes

A function of making the first readable signal true when the communication data exists in the queue;

A function of making the second readable signal true if the management value power is greater than the resultant power SO after the execution of the reading of the communication data of the cue force;

When the initialization signal from the dequeue execution means is true, the storage means And a function of setting the initial value as the management value.

[0045] According to a fifth aspect of the present invention, for each of a plurality of queues that hold communication data in the order of arrival, an initial value corresponding to an attribute of the communication data held in the queue is used as a management value. Step to set and

Reading the communication data sequentially from the queue having the management value of 0 or more, and subtracting the length of the communication data read from the queue power from the management value corresponding to the queue;

Setting the initial value as the management value corresponding to all the queues when there is no queue corresponding to the management value of 0 or more;

A queue scheduling method is provided.

[0046] A sixth aspect of the present invention provides a queue scheduling method in which the initial value is set according to a minimum guaranteed bandwidth allocated to each of the queues in the queue scheduling method according to the fifth aspect.

A seventh aspect of the present invention provides a queue scheduling method according to the fifth aspect, further comprising a step of shaving the communication data held in the queue.

[0048] An eighth aspect of the present invention is a port control unit that manages a plurality of ports through which communication data is input and output, and a path control unit that switches a transfer path of the communication data between the plurality of ports. And an information relay device including:

The port control means includes

Multiple queues holding communication data in the order of arrival;

Storage means provided corresponding to each of the queues, and an initial value corresponding to an attribute of the communication data held in the queue is set as a management value;

The communication data is sequentially read out from the queue having the management value of 0 or more, and the queue power is read out The length of the communication data corresponding to the queue is Subtracting from the control value;

Queue control means for executing

An information relay device including a queue scheduling device including

[0049] A ninth aspect of the present invention is the information relay device according to the eighth aspect,

The initial value provides an information relay device that is set according to the minimum guaranteed bandwidth allocated to each of the queues.

[0050] A tenth aspect of the present invention is the information relay device according to the eighth aspect,

Furthermore, an information relay device including a shaving control means for shaving the communication data held in the queue is provided.

[0051] An eleventh aspect of the present invention is the information relay device according to the eighth aspect,

The queue control means includes

Management value calculation means provided in each of the queues;

The dequeue execution means is

A function of executing the reading of the communication data by setting the read request signal output to the management value calculation means to be true when the first readable signal outputted by each of the management value calculation means is true; ,

When all of the second readable signals output from the individual management value calculation means and indicating the remaining presence or absence of the communication data in the queue are false, all the management value calculation means are stored in the storage means. A function that outputs an initialization signal that instructs setting of the initial value to be true, and

The management value calculation means includes

After execution of reading of the communication data of the queue power, the management value power of the communication data The result of subtracting the data size is a function that makes the second readable signal true if it is greater than the force SO,

And a function of setting the initial value as the management value for the storage means when the initialization signal from the dequeue execution means is true.

[0052] The conventional technical problem described above is derived from the operation of the conventional DRR. In other words, the conventional DRR operation that keeps dequeuing from the same queue until the deficit value becomes 0 is the cause of the burst size increase.

Therefore, in the above-described present invention, the following queue read control is performed as an example.

In other words, basically, when there is one frame, if one packet is dequeued, it moves to reading the next queue.

[0054] When the deficit value becomes 0, the target queue is also excluded from the target of scheduling (dequeue), and only for queues with a deficit value of 0 or more (that is, queues that still have frames) Perform dequeue with.

[0055] Thus, when all the queues are excluded from the scheduling target, the deficit value is reset and the process returns to the beginning.

With this control mode, the burst size can be limited to one frame, and the above-mentioned technical problem can be solved.

[0056] According to the present invention described above, DRR control capable of suppressing the burst amount to a certain amount or less can be realized.

In addition, since the burst amount can be suppressed, shaving accuracy will not be deteriorated even when used together with shaving.

[0057] Further, since jitter is suppressed by reducing the burst amount, the flow for each queue is scheduled more fairly.

Brief Description of Drawings

FIG. 1 is a conceptual diagram showing a configuration of a DRR system that is a reference technique of the present invention.

FIG. 2 is a conceptual diagram showing the configuration of a relay device that implements the DRR system, which is the reference technology of the present invention. FIG. 3 is a block diagram for explaining the operation when shaving is not executed according to the DRR method which is the reference technique of the present invention.

FIG. 4 is a conceptual diagram for explaining the operation when shaving is not executed according to the DRR system which is the reference technique of the present invention.

FIG. 5 is a conceptual diagram for explaining the operation when shaving is used in combination in the DRR system which is the reference technique of the present invention.

FIG. 6 is a conceptual diagram showing an example of the configuration of an information relay apparatus that implements a queue scheduling method according to an embodiment of the present invention.

FIG. 7 is a conceptual diagram showing an example of a configuration of a queue scheduling apparatus according to an embodiment of the present invention.

FIG. 8 is a conceptual diagram showing an example of a configuration of a deficit processing unit constituting the queue scheduling apparatus according to an embodiment of the present invention.

FIG. 9 is a conceptual diagram showing an example of a configuration of a dequeue execution unit that constitutes a queue scheduling apparatus according to an embodiment of the present invention.

FIG. 10 is a flowchart showing an example of the operation of the deficit processing unit in the queue scheduling apparatus according to one embodiment of the present invention.

FIG. 11 is a flowchart showing an example of the operation of the deficit processing unit in the queue scheduling apparatus according to one embodiment of the present invention.

FIG. 12 is a flowchart showing an example of the operation of the deficit processing unit in the queue scheduling apparatus according to one embodiment of the present invention.

FIG. 13 is a flowchart showing an example of the operation of the dequeue execution unit in the queue scheduling apparatus according to one embodiment of the present invention.

FIG. 14 is a conceptual diagram showing an example of the operation of a queue scheduling apparatus according to an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 6 is a conceptual diagram showing an example of the configuration of an information relay apparatus that implements the queue scheduling method according to an embodiment of the present invention. The information relay device 100 according to the present embodiment includes a plurality of input / output ports 110 and a port control unit 12.

0, includes internal switch 130.

Each input / output port 110 is connected to an external communication line (not shown), and frame 300 (communication data) as communication data is input / output.

The internal switch 130 switches the transfer path of the frame 300 between the plurality of input / output ports 110.

Each input / output port 110 is provided with a port control unit 120 that controls input / output of the frame 300 with respect to the input / output port 110.

[0062] On the input side of the frame 300 in the port control unit 120, a packet analysis unit 121, a destination search processing unit 122, and a queue scheduling device 200 are provided. In addition, a queue scheduling device 200 is provided on the output side of the port control unit 120.

The packet analysis unit 121 determines the attribute of the frame 300 based on the control information included in the frame 300 that arrives at the input / output port 110.

The destination search processing unit 122 determines information such as a destination address included in the frame 300.

Instruct the internal switch 130 of the transfer destination I / O port 110.

[0064] The queue scheduling apparatus 200 on the input side performs the shaving (smoothing of traffic change with time) and the quality of communication service (QoS) such as minimum bandwidth guarantee for the incoming frame 300. Perform management.

[0065] The queue scheduling apparatus 200 on the output side manages the quality of the communication service of the frame 300 sent to the outside.

FIG. 7 is a conceptual diagram showing an example of the configuration of the queue scheduling apparatus 200 of the present embodiment.

The queue scheduling apparatus 200 according to the present embodiment includes a plurality of queues 210 (queue 1 to queue n), a queue control unit 220, and a shaving control unit 250.

The queue control unit 220 includes a plurality of deficit processing units 230 (management value calculation means) and a dequeue execution unit 240 (dequeue execution means).

The deficit processing unit 230 is provided in each queue 210. The dequeue execution unit 240 passes the queue 210 from each of the plurality of queues 210 as described below. Execute read (dequeue) of program 300.

The shaving control unit 250 notifies the deficit processing unit 230 of information such as the presence / absence of the frame 300 and the frame length L in the individual queues 210 via the shaving signal 251.

[0069] At this time, the shaving control unit 250 appropriately controls the shaving signal 251 so that the frame 300 does not exist until a predetermined timing even when the frame 300 actually exists in the queue 210. By making it appear to the processing unit 230, control is performed so that the traffic becomes substantially constant at the upper limit value set in the queue 210.

[0070] Two logic signals, dequeue enable signal 2 63 (first readable signal) and more—dequeue signal 264 (second readable signal), which will be described later, are sent from the deficit processing unit 230 to the dequeue execution unit 240. Is output.

The dequeue execution unit 240 outputs two logical signals, a dequeue request signal 261 and an add-quantum signal 262, which will be described later, to the deficit processing unit 230.

FIG. 8 is a conceptual diagram showing an example of the configuration of the deficit processing unit 230 of the present embodiment.

The deficit processing unit 230 of this embodiment includes a calculation Z control logic 231, a quantum value register 232 (storage means), and a deficit value register 233 (storage means).

In the Quantum value register 232, the Quantum value Vq (initial value) corresponding to the minimum guaranteed bandwidth assigned to the queue 210 corresponding to the Deficit processing unit 230 is set.

In the deficit value register 233, a deficit value Vd (management value) initialized by the quantum value Vq is set.

The calculation Z control logic 231 obtains information on the presence / absence of the frame 300 in the corresponding queue 210 and information on the frame length L based on the shaving signal 251 input from the shaving control unit 250.

In addition, the calculation Z control logic 231 performs reception processing (according to determination of the logical state) of the dequeue request signal 261 and the add-quantum signal 262 from the dequeue execution unit 240.

In addition, the calculation Z control logic 231 performs transmission of the frame 300 to the dequeue execution unit 240, and outputs the dequeue enable signal 263 and the more-dequeue signal 264 (logic state setting processing). FIG. 9 is a conceptual diagram showing an example of the configuration of the dequeue execution unit 240 of the present embodiment. The dequeue execution unit 240 of this embodiment includes a dequeue control logic 241, a round robin power counter 242, and an internal state register 243.

The round robin counter 242 is a counter that stores a counter value for sequentially accessing each of the plurality of queues 210. In the case of the present embodiment, the counter value returns to 1 when counting up to n corresponding to queue 1 to queue n.

However, in the present embodiment, as described later, only the queue 210 to which the dequeue enable signal 263 from the deficit processing unit 230 is asserted is subject to dequeue by round robin (in order). Other than that, it is skipped only when the counter value changes.

[0080] The internal status register 243 is dequeued in all of the plurality of queues 210, even though it can be dequeued based on the value of the deficit value Vd. An internal state flag 243a for determining whether or not the force is applied is stored.

[0081] The dequeue control logic 241 includes a dequeue enable signal 26 output from the deficit processing unit 230.

3, more—Operates internal state flag 243a according to the logical state of dequeue signal 264.

[0082] Further, according to the state of internal state flag 243a, whether to continue the sequential dequeue processing for queue 210 and the logical state of add-Quantum signal 262 output to deficit processing unit 230 are determined. .

In this embodiment, as an example, a configuration example in which the queue control unit 220 is divided into a deficit processing unit 230 and a dequeue execution unit 240 is shown, but both may be configured integrally! /.

Hereinafter, an example of the operation of the present embodiment will be described.

In the information relay device 100, the frame 300 arriving at an arbitrary input / output port 110 is identified by the packet analysis unit 121 of the port control unit 120 for attributes such as urgency, minimum bandwidth to be allocated, and traffic. Further, the destination search processing unit 122 determines the destination.

In queue scheduling apparatus 200, according to the attribute discrimination result of frame 300 in packet analysis section 121, frame 300 is distributed to queue 210 having a corresponding attribute set. [0086] Then, in queue scheduling apparatus 200, the QoS necessary for frame 300 is realized by controlling the reading order of frames 300 in each of a plurality of queues 210 as described below as an example. To do.

[0087] The internal switch 130 transfers the frame 300 arriving from the queue scheduling apparatus 200 on the input side to the output side of the input / output port 110 corresponding to the destination determined by the destination search processing unit 122, and this output The frame 300 transferred to the side is output to the outside through the queue scheduling device 200 similar to that on the input side.

Hereinafter, the operation of each unit of queue scheduling apparatus 200 will be described in detail with reference to flowcharts.

In the queue scheduling apparatus 200 of the present embodiment, for example, the following queue read control is performed.

That is, basically when one frame 300 is dequeued from one queue 210, the process proceeds to reading the next queue.

Then, when the deficit value Vd becomes 0, the queue 210 is excluded from scheduling (dequeueing), and only the queue 210 having a deficit value Vd of 0 or more (that is, the queue with the frame 300 still) is the same. Execute dequeue in order (Round Robbin).

Thus, when all the queues 210 are excluded from the scheduling target, the deficit value Vd is reset (initialized) with the quantum value Vq, and the process returns to the beginning.

According to such dequeue control, the burst size is limited to the frame length L of one frame, and the above-mentioned technical problem can be solved.

FIG. 10, FIG. 11, and FIG. 12 are diagrams in the queue scheduling apparatus 200 of the present embodiment.

5 is a flowchart showing an example of the operation of a deficit processing unit 230.

The deficit processing unit 230 always executes the following [Operation SI 1] to [Operation S 14].

[Operation S11] If there is a frame 300 in the corresponding queue 210 and the Deficit value Vd force is greater than ^, the dequeue enable signal 263 is asserted. Otherwise, dequeue enable signal 263 is negated.

[0093] [Operation S12] The frame length L of the first frame 300 of the corresponding queue 210 is examined, and the current If the value obtained by subtracting the frame length L from the existing deficit value Vd is still larger than 0, the more-dequeue signal 264 is also asserted. Otherwise, the more—dequeue signal 264 is negated.

[Operation S13] When the dequeue request signal 261 is asserted from the dequeue execution unit 240, the first frame 300 is extracted from the queue 210 and passed to the dequeue execution unit 240. After that, the frame length L is subtracted from the deficit value Vd.

[Operation S14] When the add-quantum signal 262 is asserted from the dequeue execution unit 240, the quantum value Vq is calculated to the deficit value Vd. At this time, if the Deficit value Vd becomes larger than the Quantum value Vq by addition, the Deficit value Vd is set to the same value as the Quantum value Vq.

That is, as illustrated in the flowchart of FIG. 10, the deficit processing unit 230 (calculation Z control logic 231) initializes the deficit value Vd with the quantum value Vq (step 401).

Then, it is checked based on the shaving signal 251 whether or not there is a frame 300 in the corresponding queue 210 (step 402).

If frame 300 is in queue 210! /, Dequeue enable signal 263 is negated (step 403), and if frame 300 is in queue 210, dequeue enable signal 263 is asserted (step 406). .

When the dequeue enable signal 263 is asserted, the dequeue request signal 261 may be asserted at any time by the dequeue execution unit 240 force.

When the dequeue request signal 261 is asserted, as shown in the flowchart of FIG. 11, the deficit processing unit 230 detects the dequeue request signal 261 being asserted (step 411) and removes it from the corresponding queue 210. One frame 300 is dequeued (removed) and transferred to the dequeue execution unit 240 (step 412), and the frame length L of the frame 300 is subtracted from the deficit value Vd (step 413).

[0099] Returning to FIG. 10, the deficit processing unit 230 uses the deficit value Vd to the frame length L (however, if step 403 is executed in the previous stage, that is, the processing of FIG. 11 is executed! If ヽ, the frame length L = 0) is subtracted from the value SO (step 404). If greater, the more—dequeue signal 264 is asserted (step 407), otherwise In this case, the more—dequeue signal 264 is negated (step 405).

[0100] Then, the process returns to step 402 and the same processing is repeated.

In the process of iterating in FIG. 10, if the add-quantum signal 262 is asserted from the dequeue execution unit 240 at any time, the processing in the flowchart in FIG. 12 is executed.

That is, when the deficit processing unit 230 detects the add-quantum signal 262 (step 421), the deficit processing unit 230 calculates the quantum value Vq to the deficit value Vd (step 422). However, in this addition, if the addition result becomes larger than the Quantum value Vq, the Deficit value Vd is set to the same value as the Quantum value Vq.

On the other hand, the operation of the dequeue execution unit 240 is as follows, for example.

[Operation S21] Set the internal status flag 243a (rr_continue) to 0.

[Operation S22] Refer to the dequeue enable signal 263 and the more—dequeue signal 264 of the plurality of queues 210 in order (in order from 1 to n of the value of the round robin counter 242). If the dequeue enable signal 263 is asserted, the queuer also performs dequeue only once (outputs the dequeue request signal 261 to the deficit calculation unit). Also, when dequeue is performed and the more-dequeue signal 264 is asserted, set rr—continue to 1.

[Operation S23] Move to the next queue 210 in order, and execute [Operation S22] in all the queues. If rr—continue is 0 after going through all the queues 210, the add-quantum signal 262 is asserted to all the deficit processing units 230.

[0105] [Operation S24] Return the queue 210 to be referenced to the beginning (the value of the round robin counter 242 is

Return to 1) and repeat the dequeue process again from [Operation S21] above.

The processing of the dequeue execution unit 240 will be further described with reference to the flowchart of FIG.

[0106] The dequeue execution unit 240 sets the round robin counter 242 to 1, sets the queue 1 as a dequeue target, and initializes the internal state flag 243a (rr_continue) to 0 (step 501).

Thereafter, it is determined whether or not the dequeue enable signal 263 of the corresponding queue is asserted (step 502).

If the dequeue enable signal 263 is not asserted, the dequeue request signal After negating No. 261 (step 503), it is determined whether or not the power has completely gone through all the queues 210 (whether the corresponding queue is queue n or not) (step 504).

If the circuit has not made a round, the corresponding queue is set to the next queue 210 (incrementing the round mouth bin counter 242) (step 505), and then the processing returns to step 502 described above.

[0109] If it is determined in step 502 above that the dequeue enable signal 263 of the corresponding queue is asserted, the dequeue request signal 2 to the deficit processing unit 230 of the corresponding queue

61 is asserted (step 506), the dequeued frame 300 is received from the deficit processing unit 230, output to the internal switch 130 at the subsequent stage, and the dequeue request signal 261 is negated (step 507).

[0110] After that, it is determined whether the more—dequeue signal 264 of the corresponding queue is asserted (step 508). If it is asserted, rr_continue is set to 1 (step 509) and step 504 is executed. Execute.

[0111] If it is determined in step 504 that all queues 210 have been dequeued (that is, the value of round-robin counter 242 is the maximum value n), whether rr—continue is 0 or not is determined. Determine (step 510).

[0112] Then, when rr—continue = 0, the decuring of the frames 300 of all the queues 210 is completed, so the add-quantum signal 2 is sent to all the deficit processing units 230.

After 62 is asserted to initialize the deficit value Vd (step 511), the process returns to the first step 501.

[0113] If it is determined in step 510 that rr—continue is not 0, the first step 5

Returning to 01, the dequeue is executed in order only for the queue 210 that has not used up the deficit value Vd in the previous round.

[0114] The operation of the deficit processing unit 230 and the dequeue execution unit 240 of the queue control unit 220 as described above sequentially looks at all the queues 210 in a laudrobin fashion, so the burst size of a single queue is always 1 Reduced to packet length.

[0115] Further, the deficit processing unit 230 corresponding to each queue 210 indicates whether or not the bandwidth allocated to the queue 210 (that is, the value of the deficit value Vd) is used up. Use signal 264 and the allocated bandwidth, turn it off! /, Na! /, Cue 210 By providing the internal state flag 243a (rr—continue) for controlling so that the deficit value Vd is not initialized while it exists, the bandwidth ratio allocated in all the queues 210 can be accurately protected.

[0116] The result of the conventional example shown in FIGS. 4 and 5 described above by the queue scheduling control in the queue scheduling apparatus 200 of the present embodiment as described above will be described below.

[0117] The number of queues is 3, the minimum bandwidth is 500Mbps (queue 1), 350Mbps (queue 2), 150 Mbps (queue 3), and shaving is 500Mbps (queue 1), 500Mbps (queue 2), 300Mbps (queue) 3). Similarly, the shaving burst size is set to 3.

In this case, the scheduling result by the queue scheduling apparatus 200 of the present embodiment is as shown in FIG.

In the case of this embodiment, unlike the case of the conventional DRR in which dequeue is continuously dequeued from the single queue by the value of the deficit value Vd, the control mode is changed so that the queuing is performed one frame at a time from all the queues. Therefore, at time t = 0 to 8, all three queues 1 to 3 operate in a round robin fashion.

[0119] After that, since the deficit value Vd of queue 3 became 0, it was excluded, and next dequeue was performed alternately on queue 1 and queue 2, and finally only queue 1 was greater than the deficit value ^ Dequeue 1

[0120] The force that the burst size of the queue shaper (shaving controller 250) is 3. Since one frame is taken out from each queue, the problem that scheduling cannot be performed due to insufficient burst size even though it is larger than the deficit value Vd force O. It does not occur in the case of the embodiment.

[0121] In this example, frames are output from queue 1 with a maximum of 3 bursts, so that the capacity of the transmission buffer on the output side is limited to the length of 3 to 4 frames. Since the conventional example shown in FIGS. 4 and 5 requires a buffer of 10 frames, it can be seen that in the case of the present embodiment, the required buffer size can be significantly reduced.

[0122] Also, if the difference in Deficit value is large (the difference in minimum bandwidth guarantee is large for each queue), it will always be output continuously, but in most cases the difference in Deficit value Vd is small. This makes it possible to reduce the buffer size, and can produce a sufficient effect in normal use.

[0123] Note that in the assertion process of the more-dequeue signal 264 of the deficit processing unit 230, whether or not there is a second packet in the corresponding queue 210 is not dequeued until it returns once. This is because it is assumed that a dequeue request from the unit 240 comes (dequeue request signal 261 is asserted).

[0124] In conventional DRR, one or more frames corresponding to the length corresponding to the deficit value Vd

If you don't dequeue 300 consecutively (unless Burst), you can't guarantee minimum bandwidth! For this reason, the shaving controller 250 of the queue 210 has to perform burst transfer that is equal to or greater than the value of the deficit value Vd.

In the case of this embodiment, in order to reduce the burst size, the set value of the burst size by the shaving control unit 250 must also be lowered. For this reason, there is a situation in which there is a frame 300 in the cue 210 but the power of shaving should not be dequeued.

[0126] In this state, the deficit value 230 of the deficit processing unit 230 may be reset (initialization by the quantum value Vq), and there may be a moment when scheduling according to the set bandwidth cannot be performed as it is. In this embodiment, the more-dequeue signal 264 is provided, and in the assertion process of the more-dequeue signal 264, it is determined whether or not there is a second packet in the corresponding queue 210.

[0127] Of course, even if there is no more-dequeue signal 264, it will be the same as the set bandwidth if a little time elapses. However, the provision of the more-dequeue signal 264 as in this embodiment is an instantaneous bandwidth. This is effective when strict scheduling is performed without allowing any deviation.

[0128] The following effects can be obtained by mounting the above-described queue scheduling apparatus 200 in the information relay apparatus 100 or the like.

When multiple flows of frames 300 having different attributes are flowing through the information relay apparatus 100, the burst size on the output side of the queue control unit 220 of the queue scheduling apparatus 200 is always suppressed to the frame length L of one frame. Even if only a single flow of the frame 300 flows in the information relay apparatus 100, the burst size can be suppressed to the burst size set by the shaving control unit 250.

In conventional DRR implementation, the shaving control unit 250 must be allowed to set a burst size greater than the Quantum value Vq. Otherwise, the bandwidth ratio could not be maintained.

On the other hand, in the case of the present embodiment, the burst size of the shaving control unit 250 may be set to a minimum, so that the burst size can be considerably suppressed even in a single flow.

[0131] Since the burst size can be suppressed, for example, the capacity of the data buffer provided in the internal switch 130 or the like located at the subsequent stage of the queue control unit 220 corresponding to the burst size can be reduced.

As a result, it is possible to reduce the cost and mounting area required for the storage elements that constitute the data buffer.

Industrial applicability

According to the present invention, it is possible to reduce the burst amount while maintaining the set bandwidth of each queue.

In addition, according to the present invention, it is possible to provide a queue scheduling technique that does not deteriorate the shaving accuracy even when used together with the implementation of shaving.

[0134] Further, according to the present invention, it is possible to schedule flows for each queue more fairly.

Further, according to the present invention, it is possible to construct an information relay device at a lower cost.

[0135] Further, according to the present invention, it is possible to provide an information relay apparatus capable of realizing stable bandwidth control and shelving according to attributes of communication data at a low cost. The present invention is not limited to the configuration exemplified in the above-described embodiment, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0136] For example, the configurations of the information relay device 100 and the queue scheduling device 200 that implement the queue scheduling technique of the present invention are examples, and are widely used in general information devices. It is possible to apply.

Claims

The scope of the claims

[1] Multiple queues holding communication data in the order of arrival;

Read the communication data sequentially from the queue whose management value is 0 or more

The queue power, an operation of subtracting the length of the read communication data from the management value corresponding to the queue;

Queue control means for executing

A queue scheduling apparatus comprising:

[2] In the queue scheduling device according to claim 1,

The queue scheduling apparatus, wherein the initial value is set according to a minimum guaranteed bandwidth allocated to each of the queues.

[3] In the queue scheduling device according to claim 1,

The queue scheduling apparatus further comprises shaving control means for shaving the communication data held in the queue.

[4] In the queue scheduling device according to claim 1,

The queue control means includes

Management value calculation means provided in each of the queues;

The dequeue execution means is

When all of the second readable signals that are output from the individual management value calculation means and indicate the remaining presence or absence of the communication data in the queue are all false, And a function for outputting an initialization signal that instructs setting of the initial value for the storage means to be true.

The management value calculation means includes

[5] Corresponding to each of a plurality of queues that hold communication data in the order of arrival, setting an initial value according to the attribute of the communication data held in the queue as a management value; Reading the communication data from the queue of 0 or more in order, and subtracting the length of the read communication data from the management value corresponding to the queue;

A queue scheduling method comprising:

[6] In the queue scheduling method according to claim 5,

The queue scheduling method, wherein the initial value is set according to a minimum guaranteed bandwidth allocated to each of the queues.

[7] In the queue scheduling method according to claim 5,

The queue scheduling method further includes a step of shaving the communication data held in the queue.

[8] An information relay device comprising: port control means for managing a plurality of ports through which communication data is input / output; and path control means for switching the transfer path of the communication data between the plurality of ports. And The port control means includes

Multiple queues holding communication data in the order of arrival;

Queue control means for executing

An information relay device comprising a queue scheduling device including

[9] In the information relay device according to claim 8,

The information relay device, wherein the initial value is set according to a minimum guaranteed bandwidth allocated to each of the queues.

[10] In the information relay device according to claim 8,

The information relay device further includes a shaving control means for shaving the communication data held in the queue.

[11] In the information relay device according to claim 8,

The queue control means includes

Management value calculation means provided in each of the queues;

The dequeue execution means is

The management value calculation means includes

And a function for setting the initial value as the management value for the storage means when the initialization signal from the dequeue execution means is true.