WO2007049087A1

WO2007049087A1 - Semiconductor chip with amorphous crack-stop layer

Info

Publication number: WO2007049087A1
Application number: PCT/IB2005/003159
Authority: WO
Inventors: Kai Chong Chan; Mary Teo; Choew Kheng Soh
Original assignee: Infineon Technologies Ag
Priority date: 2005-10-24
Filing date: 2005-10-24
Publication date: 2007-05-03

Abstract

A semiconductor chip (19; 20; 21; 22) comprises a crystalline layer (31; 32; 32'; 32'') of semiconductor material having an active surface (27; 28; 28'; 28'') and a passive surface (29; 30; 30'; 30''). The active surface (27; 28; 28'; 28'') com-prises embedded electrical circuits and contact regions (23; 24; 24'; 24'') for contacting the electrical circuits. One or more amorphous layers (25; 26; 26'; 26'') of semiconductor material or of semiconductor oxide material are provided on the passive surface (29; 30; 30'; 30'').

Description

SEMICONDUCTOR CHIP WITH AMORPHOUS CRACK-STOP LAYER

This invention relates to a semiconductor chip and, in particular to a thin semiconductor chip, by which the yield of correctly functioning chips in production can be improved.

It is known that integrated electrical circuits sometimes fail after mounting one or more semiconductor chips onto a substrate although the semiconductor chips were previously found to be good.

US 5 882 956 suggests to improve the dicing of the wafer in which the semiconductor chips are fabricated. US 4 610 079,

US 5 096 855 and US 6 838 299^' address the same or similar solutions .

Other approaches such as in US 5 024 970, US 5 818 111, US 5 834 829, US 6 022 791, US 6 084 287, US 6 365 958 and US 6

383 893 try to limit or to stop cracks which may occur before they reach the electrical structures in the substrate or in the semiconductor chip.

The aforementioned methods do not yet provide a sufficient yield rate, especially when stacked semiconductor chips are to be provided in one semiconductor package.

The object of the invention is to provide a method to fabri- cate a semiconductor package and an improved semiconductor package that has a high yield rate in production. The invention provides a semiconductor chip with a crystalline layer of semiconductor material, the crystalline layer having an active surface and a passive surface. The active surface comprises embedded electrical circuits and contact regions. Contact regions such as contact pads are electrically connected to the embedded electrical circuits. A passivation layer is provided on top of the active surface leaving the contact regions uncovered.

One or more amorphous layers of semiconductor material or of semiconductor oxide material are provided on the passive surface. These materials can include silicon or germanium, both being widely used to fabricate semiconductor components.

The invention seeks to improve the production yield of good chips by preventing cracks from being induced during semiconductor chip manufacturing. When subjected to stress, the cracks can propagate leading to semiconductor chip failure and even chip breakage.

Some of such cracks originate from the impact of a probe pin that can result in a "probe mark" on the rear surface of the semiconductor chip. The probe pin is used to release the ^■ semiconductor chip from a wafer bonding sheet. For that pur- pose, the probe pin hits the rear surface of the semiconductor chip after the wafer singulation process.

During semiconductor chip manufacturing, electrical circuits are formed on a semiconductor wafer. The semiconductor wafer is then singulated into semiconductor chips. The semiconductor chip has an active surface and rear surface that is passive. The wafer singulation process then involves placing the semiconductor wafer with the rear surface facing downwards onto a wafer bonding sheet. The wafer bonding sheet has a layer of adhesive. The wafer is diced around singulation lines .

For flip chip mounting, the semiconductor chip undergoes a subsequent operation to rotate the active surface of the semiconductor chip to face downward. A handler with a suction cup is placed above the semiconductor chip. The semiconductor chip, when released from the wafer bonding sheet, has the ac- tive surface facing upwards. The handler receives the released semiconductor chip and rotates the active surface to face downwards. The semiconductor chip is then transferred to a collet. The collet has flanges around the semiconductor chip and a vacuum system. The collet accurately positions the semiconductor chip with its active surface facing downward onto a substrate. The collet can leave a crack called collet mark on the rear surface of the semiconductor chip.

The invention improves the resistance of the semiconductor chip to damage and to the formation of cracks caused by the mechanical handling processes by providing an amorphous layer of material on the rear surface of the semiconductor chip.

A polycrystalline material has a plurality of domains. A do- main has orderly and repeated layout of atoms. Atoms are connected to each other by chemical bonds. A domain boundary defines the boundary between domains. An amorphous material has a random layout of atoms . Some atoms are connected by chemical bonds. A semiconductor chip primarily consists of crys- talline material. A crack on a semiconductor chip surface, tends to propagate along domain boundary when subjected to thermal or mechanical stress. A semiconductor chip according to the invention has an amorphous surface. It is believed that the random layout of atoms in the amorphous layer slows down crack propagation thereby improving breakage strength.

Other methods to improve the semiconductor fracture strength involve removing or reducing surface cracks. The process to remove or reduce surface cracks is termed "stress relief". These methods include chemical mechanical polishing, wet etching, dry etching and dry polishing. The table below compares the ^"various methods to increase silicon fracture strength.

μm = micrometer

The invention allows for - different from the aforementioned methods - a variation of the breakage strength of a semiconductor chip. An further advantage of the invention is that the amorphous layer acts as a compliant layer to reduce the impact of any- fracturing force. During semiconductor chip manufacturing, the semiconductor chip experiences fracturing force from the eject probe during wafer singulation process and the collet impact for flip chip type mounting on the substrate.

A possible further advantage of the invention is a reduction in radio frequency losses for high frequency devices.

The invention provides a silicon semiconductor chip with an amorphous silicon layer at the rear surface of the semiconductor. This provides one means of implementing the invention.

Another means of implementing the invention is to provide a semiconductor chip with a layer of amorphous silicon oxide at the rear surface of the semiconductor chip.

The invention also provides a method that is effective for semiconductor chips with thicknesses less than 100 μm. Current stress relief methods have limited effects for thin wafers. The provision of a thin semiconductor chip is often a requirement for thin or stacked-chip packages. The trend to- wards miniaturisation and system-in-packages drives the demand for thin semiconductor chips. The invention provides such semiconductor chips with a high yield rate.

A semiconductor chip according to the invention has an ainor- phous layer of thickness from about 10 nm (nanometer) to the same thickness as the crystalline semiconductor layer. This provides the ability to adjust the amount of breaking strength improvement. The thickness of the amorphous layer influences the semiconductor chip breaking strength. Changing the thickness of the amorphous layer changes the semiconductor chip breaking strength.

The invention provides a method to fabricate a semiconductor wafer with a plurality of semiconductor chips according to the invention.

An electronic component comprises a substrate, one or more semiconductor chips according to the invention, a plurality of electrical contact means and an encapsulation medium. The substrate includes a plurality of contact areas such as contact pads on its upper surface and a plurality of contact points on its lower surface. The electrical contact means comprise bond wires or solder balls. The electrical contact means provide electrical contact between the contact regions of the semiconductor chip with the contact areas of the substrate. The encapsulation medium covers the top surface of the substrate, the semiconductor chips and the contact means into a single body.

The semiconductor chip according to the invention is able to reduce the stress which occurs within the electronic component. The difference between modulus of the semiconductor chip and modulus of the components surrounding the semiconductor chip generates stress. This is particularly so at temperature extremes. The electronic component experiences temperature extremes during electronic component assembly process, electronic component testing and end-user application. The modulus of the semiconductor chip can be adjusted to match the modulus of the surrounding components. The amorphous layer of the semiconductor material has a different modulus as compared to crystalline semiconductor material. Changing the thickness of the amorphous layer alters the resultant modulus of the semiconductor chip.

For providing an amorphous layer on the rear surface of a semiconductor chip one thins the wafer by treating the passive side of the wafer that is opposite to the active side. Then the passive side of the wafer is provided with an amorphous layer of semiconductor material and the wafer is singu- lated thereafter into semiconductor chips.

The reduction of wafer thickness is in preparation for electronic component assembly process. The physical size and shape of the electronic component usually requires a reduction in wafer thickness. Reduction of wafer thickness also reduces wafer breaking strength and makes it prone to breakage. The provision of the amorphous layer after wafer thinning improves the wafer breakage strength for easier handling.

There are several methods for forming the amorphous layer of silicon or silicon oxide on a silicon chip. One method is using ion implantation. The passive surface of the silicon material is subjected to 1 x 10¹⁵ Xenon ions cm^"2 in the 1 to 4 Mev (mega-electron volt)^' energy range to form the amorphous layer. This is followed by annealing to remove defective areas such as point defects.

Another method to provide an amorphous layer is plasma etching. This method involves using a plasma to etch the passive surface of the semiconductor chip. The plasma contains highly excited ions, which easily react chemically. There is also a physical bombardment mechanism in that the ions are accelerated towards the wafer with an electric field. The acceler- ated ions break down the crystalline structure at the passive surface and turn it into an amorphous structure.

Fine grid grinding is another method to provide an amorphous layer. This involves the use of a fine grid mesh to grind the passive surface of the semiconductor chip. This causes a thin surface layer of crystalline structure to break down and turn amorphous .

Several methods exist for depositing an amorphous layer of silicon or silicon oxide onto a silicon chip. One method called chemical vapour deposition (CVD) uses glow discharge to produce a non-equilibrium and reactive plasma by decomposing a raw material gas such as silane gas.

Another deposition method is physical vapour deposition (PVD) . PVD involves a deposition of a thin film by physical means. One form of PVD is sputtering. Sputtering is a process whereby atoms of a coating material are ejected into the gas phase by the bombardment of energetic ions. The sputtered atoms deposit onto a target material placed below thereby building up the desired coating film.

Figure 1 shows an electronic component 1 according to the in- vention.

Figure 2 shows an enlarged region A of figure 1.

Figure 3 shows an enlarged region B of figure 1.

Figure 4 shows the breaking strength of first wafers,

Figure 5 shows the breaking strength of further wafers and Figure 6 shows the breaking strength of further wafers.

Figure 7 shows the cross section of a semiconductor chip 34 according to the invention.

Figure 1 shows an electronic component 1, which includes a substrate 2 at its lowest part. On top of substrate 2 is placed a first semiconductor chip 19 of a flip chip type. A first spacer 16 rests on top of the first semiconductor chip 19. A second semiconductor chip 20 sits on top of the first spacer 16. The second semiconductor chip 20 has a second spacer 17 on its top surface. A third semiconductor chip 21 is located on top of second spacer 17 and directly beneath the bottom surface of a third spacer 18. A fourth semiconductor chip 22 is provided on the top surface of the third spacer 18. The spacers 16, 17, 18 are made of insulating material such as polyimide. Encapsulation medium 15 covers semiconductor chips 19, 20, 21, 22 and spacers 16, 17, 18 on the substrate 2 forming thereby a single body.

The substrate 2 includes a plurality of outer contact pads 8 at the peripheral area of. its upper surface, a plurality of inner contact pads 10 at the central area of its upper sur- face and a plurality of external contact^' pads 9 on its lower surface. The substrate 2 is made of a three layer laminate 5, 6, 7. The laminate 5, 6, 7 has a low dielectric constant and good insulation property. Each laminate 5, 6, 7 has a plurality of metal traces which is not shown in figure 1. The metal traces of each laminate 5, 6, 7 are connected to metal traces of the other laminates 5, 6, 7 by conductive vias 3. Conductive vias 3 and metal traces connect the outer contact pads 8 and the inner contact pads 10 with the external contact pads 9. A solder ball 4 is attached to each of the external contact pads 9 to form the electrical connection between the electronic component 1 and the external substrate such as a printed circuit board that is not shown on the diagram.

The first semiconductor chip 19 has a first crystalline layer 31 and an first amorphous layer 25. The first amorphous layer 25 is placed above the first crystalline line layer 31. The first crystalline layer 31 has a first active surface 27 fac- ing downwards. The first rear surface 29 of the first amorphous layer is passive and faces upwards. The first active surface 27 has electrical circuits located at the central portion of the surface and a plurality of first chip contact pads 23 at the peripheral of the surface. The electrical cir- cuits are connected with the first chip contact pads 23 by metal lines embedded within the first active surface 27. Figure 1 does not display the electrical circuits and metal lines. A solder ball 11 is provided at, each of the first chip contact pads 23. The first semiconductor chip 19 is electri- cally connected by the solder balls 11 to the inner contact pads 10 located on the upper surface of the substrate 2. The first semiconductor chip 19 has a collet mark 13 on its first rear surface 29. The collet mark is a fracture of the rear surface by the collet during substrate mounting. The first amorphous layer 25 acts as compliant layer to soften the collet impact.

The second semiconductor chip 20 has a second crystalline layer 32 on top of a second amorphous layer 26. The second active surface 28 of the second crystalline layer 32 is facing upwards. On the second active surface 28 are electrical circuits at its central portion and a plurality of second chip contact pads 24 located at its periphery. The electrical circuits are connected to second chip contact pads 24 by metal lines embedded within the second active surface 28. The electrical circuits and metal lines are not disclosed in figure 1. The second chip contact pad 24 has a bond wire 12 con- necting it to the outer contact pad 8 located on the upper surface of substrate 2. The second rear surface 30 of the second semiconductor chip 20 is passive and is facing downwards. The second semiconductor chip 20 is laterally wider than the first semiconductor chip 19 so that it protrudes over the first semiconductor chip 19. The length of protrusion is about 250 micrometer (μm) . The second chip contact pads 24 are located on the area of the second chip semiconductor chip 20 protruding over the first semiconductor 19. During wire bond operation, a bond force and ultrasonic en- ergy are applied for a few milliseconds on the second chip contact pad 24. The second semiconductor chip 20 experiences shear force during wire bond operation due to the protruding area. The second semiconductor chip 20 benefits from increased breaking strength arising from the second amorphous layer 26.

The third semiconductor chip 21 has features similar to the second semiconductor chip 20 with the exception that it is laterally smaller than the second semiconductor chip 20. Similar components have the same reference numbers with a prime symbol.

The features of the fourth semiconductor chip 22 are similar to that of the third semiconductor chip 21 with the exception that it is laterally smaller than the third semiconductor chip 21. Similar components are numbered with the same reference numbers with a double prime symbol. The fourth semiconductor chip 22 has a probe mark 14 on its fourth rear surface 30' ' . The probe mark 14 is a fracture of the fourth rear surface 30'' by an eject probe hitting the fourth rear surface 30'' during wafer singulation process. Fourth amorphous layer 26' ' acts as compliant layer to cushion the impact of the eject probe.

The layer of an amorphous layer 25, 26, 26' , 26'' on the rear surface 29, 30, 30', 30'' of the semiconductor chip 19, 20, 21, 22 occurs during the semiconductor chip manufacturing process. The semiconductor chip manufacturing process comprises the fabrication of electrical circuits onto the semiconductor wafer, wafer thinning, singulating wafer into semiconductor chips and packaging of the semiconductor chip 19, 20, 21, 22. The forming of the amorphous layer 25, 26, 26', 26" on the rear surface 29, 30, 30', 30'' occurs directly after wafer thinning. The thickness of the amorphous layer 25, 26, 26' , 26'' alters the modulus value of the semiconductor chip 19, 20, 21, 22. The thickness of the amorphous is selected to maximise matching of the semiconductor chip' s 19, 20, 21, 22 modulus with the modulus of the components surrounding the semiconductor chip 19, 20, 21, 22. The estimated thickness of the crystalline layer is 60 micrometer (μm) ^'. The thickness of the amorphous layer is roughly 10 μm.

Figure 2 displays an enlarged detail A of figure 1. The fourth amorphous layer 26' ' has suffered a probe dent 35 on its fourth rear surface 30' ' . The fourth crystalline rear surface 34'' has a probe mark 14. The probe mark 14 is located directly above the probe dent 35.

Figure 3 shows an enlarged detail B of figure 1. The first amorphous layer 25 has a collet dent 36 on first rear surface 29. Just below the collet dent 36 is located the collet mark 13. The collet mark 13 is found on the first crystalline rear surface 33.

Figure 4 shows wafer breaking strength for different stress release option. These data are collected from wafers of 185 micrometer (μm) thickness. The semiconductor wafer has a plurality of semiconductor chips . The breaking strength of the semiconductor wafer reflects the breaking strength of the semiconductor chip that it contains.

Wafers PE185_W1 and PE185_W2 are treated with 3 μm plasma etch. Wafers PE185_W1 have a minimum, maximum and average breaking strength of about 22, 108 and 68 N respectively. Wafers PE185_W2 exhibit a minimum, maximum and average break- ing strength of about 34, 104 and 65 N respectively.

Wafers DP185_W1 and DP185_W2 are subjected with 3 μm dry polish. Wafers DP185_W1 show a minimum, maximum and average breaking strength of about 28, 92 and 65 N respectively. Wafers DP185_W2 display a minimum, maximum and average breaking strength of about 18, 88 and 60 N respectively.

Wafers WE185_W1 and WE185_W2 are exposed with 25 μm wet etch. Wafers WE185_W1 have a minimum, maximum and average breaking strength of about 52, 102 and 78 N respectively. Wafers

WE185_W2 demonstrate a minimum, maximum and average breaking strength of about 28, 108 and 78 N respectively.

Figure 5 displays wafer breaking strength for different stress release options. These data are obtained from wafers of 65 μm thickness. Wafers PE65_W1 and PE65_W2 are subjected with 3 μm plasma etch. Wafers PE65_W1 display a minimum, maximum and average breaking strength of about 11, 24 and 17 N respectively. Wafers PE65_W2 show a minimum, maximum and average breaking strength of about 9, 21 and 16 N respectively.

Wafers DP65_W1 and DP65_W2 are exposed with 3 μm dry polish. Wafers DP65_W1 exhibit a minimum, maximum and average breaking strength of about 4, 23 and 16 N respectively. Wafers DP65_W2 have a minimum, maximum and average breaking strength of about 4, 24 and 16 N respectively.

Wafers WE65_W1 and WE185_W2 are treated with 25 μm wet etch. Wafers WE65_W1 display a minimum, maximum and average break- ing strength of about 7, 22 and 16 N respectively. Wafers WE65_W2 disclose a minimum, maximum and average breaking strength of about 9, 23 and 16 N respectively.

Figure 4 and 5 show a significant reduction of breaking strength when wafer thickness is reduced from 185 to 65 μm.

Figure 6 discloses wafer breaking strength for different stress release options. These data are gathered from wafers of 50 μm thickness. Wafers with no plasma etch stress relief have minimum, maximum and average breaking strength of about 0.2, 3.5 and 1.0 N respectively. Wafers with plasma etch stress relief show a minimum, maximum and average breaking strength of about 11, 19 and 14 N respectively. Wafers with plasma etch stress relief and an amorphous layer have a mini- mum, maximum and average breaking strength of about 12 N, 23 N and 16 N respectively. This displays an average increase of about 15 % breaking strength when the silicon wafer is pro- vided with amorphous silicon layer according to the invention.

Figure 7 shows the cross section of a semiconductor chip 40 with the invention. The passive surface of the semiconductor chip 40 is facing upwards. The semiconductor chip 40 has a layer of amorphous silicon 37 over the passive surface of crystalline silicon 39. Interface 38 is the boundary between the amorphous silicon 37 and the crystalline silicon 39.

Reference numbers

1 electronic component

2 substrate 3 via

4 solder ball

5 first laminate layer

6 second laminate layer

7 third laminate layer 8 outer contact pad

9 external contact pad

10 inner contact pad

11 solder ball

12 bond wire 13 collet mark

14 probe mark

15 encapsulation medium

16 first spacer

17 second spacer 18 third spacer

19 first semiconductor chip

20 second semiconductor chip

21 third semiconductor chip

22 fourth semiconductor chip 23 first chip contact pad

24 second chip contact pad

24' third chip contact pad

24' ' fourth chip contact pad

25 first amorphous layer 26 second amorphous layer

26' third amorphous layer

26' ' fourth amorphous layer

27 first active surface 28 second active surface 28' third active surface 28' ' fourth active surface

29 first rear surface 30 second rear surface

30' third rear surface

30' ' fourth rear surface

31 first crystalline layer

32 second crystalline layer 32' third crystalline layer

32' ' fourth crystalline layer

33 first crystalline rear surface

34 second crystalline rear surface 34' third crystalline rear surface 34' ' fourth crystalline rear surface

35 probe dent

36 collet dent

37 amorphous silicon

38 interface 39 crystalline silicon

40 semiconductor chip

Claims

Patent claims

1. A semiconductor chip (19; 20; 21; 22) comprising: a crystalline layer (31; 32; 32' ; 32'' ) of semicon- ductor material having an active surface (27; 28;

28' ; 28'' ) and a passive surface (29; 30; 30' ; 30" ) wherein the active surface (27; 28; 28'; 28' ' ) comprises embedded electrical circuits and contact regions (23; 24; 24' ; 24''), - one or more amorphous layers (25; 26; 26' ; 26'' ) of semiconductor material or of semiconductor oxide material on the passive surface (29; 30; 30' ; 30" ).

2. A semiconductor chip (19; 20; 21; 22) according to claim

1, characterised in that the semiconductor chip (19; 20; 21; 22) and the amorphous layer (25; 26; 26' ; 26" ) at the rear surface (29; 30; 30'; 30' ') of the semiconductor chip (19; 20; 21; 22) comprises silicon material.

3. A semiconductor chip (19; 20; 21; 22) according to claim

1 or claim 2, characterised in that the amorphous layer (25; 26; 26'; 26'') at the rear surface (29; 30; 30'; 30'') of semiconductor chip (19; 20; 21; 22) comprises silicon oxide material.

4. A semiconductor chip (19; 20; 21; 22) according to one of the previous claims, characterised in that the semiconductor chip (19; 20; 21; 22) has a thickness of less than 100 μm.

5. A semiconductor chip (19; 20; 21; 22) according to pre- vious claims, characterised in that the thickness of the amorphous layer (25; 26; 26'; 26'') ranges from 10 nm to the same thickness as the crystalline semiconductor layer (31; 32; 32' ; 32'' ) .

β. A semiconductor wafer comprising areas of a plurality of semiconductor chips (19; 20; 21; 22) according to one of the previous claims.

7. An electronic component comprising: a substrate (2) which includes a plurality of contact areas (8, 10) on its upper surface and a plurality of contact points (9) on its lower surface, one or more semiconductor chips (19; 20; 21; 22) according to one of the claims 1 to 5, a plurality of electrical contact means (11, 12) provided between the contact regions (23; 24; 24' ; 24'' ) and the contact areas (8, 10) (for electrically connecting the contact regions (23; 24; 24' ; 24") of the semiconductor chip (19; 20; 21; 22) with the contact areas (8, 10) of the substrate

(2), an encapsulation medium (15) covering at least the top surface of substrate (2) , the semiconductor chip(s) (19; 20; 21; 22) and the contact means (11, 12) .

8. A method for fabricating a semiconductor chip (19; 20; 21; 22), the method comprising of the following steps: providing electrical circuits in an active side of the wafer, thinning of the wafer by treating the passive side of the wafer that is opposite to the active side, - providing the passive side of the wafer with an amorphous layer of semiconductor material, singulating the wafer into semiconductor chips.

9. A method for fabricating a semiconductor chip (19; 20; 21; 22) according to claim 8, characterised in that the step of providing an amorphous layer (25; 26; 26' ; 26'' ) of material on the passive side (29; 30; 30' ; 30' ' ) of the wafer comprises one or more of the follow- ing steps: ion implantation, plasma etching, fine grid grinding, annealing.

10. A method for fabricating a semiconductor chip (19; 20;

21; 22) according to claim 8, characterised in that the step of providing an amorphous layer (25; 26; 26' ; 26" ) of material on the passive side (29; 30; 30' ;

30' ' ) of the wafer comprises the step of depositing the layer of amorphous material with one or more of the following steps: - chemical vapour deposition, - physical vapour deposition.