WO2007045772A1 - Device for passivating a transversal semiconductor component - Google Patents

Device for passivating a transversal semiconductor component Download PDF

Info

Publication number
WO2007045772A1
WO2007045772A1 PCT/FR2006/002383 FR2006002383W WO2007045772A1 WO 2007045772 A1 WO2007045772 A1 WO 2007045772A1 FR 2006002383 W FR2006002383 W FR 2006002383W WO 2007045772 A1 WO2007045772 A1 WO 2007045772A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electronic component
component according
nitride
transistor
Prior art date
Application number
PCT/FR2006/002383
Other languages
French (fr)
Inventor
Christian Brylinski
Sylvain Delage
Original Assignee
Thales
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales filed Critical Thales
Publication of WO2007045772A1 publication Critical patent/WO2007045772A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]

Definitions

  • the field of the invention is that of lateral electronic components operating at high voltage and more particularly that of microwave power components. These components are, for example, transistors.
  • a side component is a component in which the flow of the main stream is parallel to the surface of the substrate over at least part of its path in the component.
  • the MESFET transistors (lateral), almost all GaAs MESFET transistors, the HEMT transistors (acronym for the English expression "High Electron Mobility Transistor”) LD-MOS 1
  • MOS transistors (acronym for the English expression "High Electron Mobility Transistor")
  • D-MOS transistors are partially lateral.
  • the category of purely vertical, that is, non-lateral, transistors comprises the majority of bipolar transistors, electrostatic induction transistors (Static Induction Transistors or SIT, Schottky gate or P / N), some U-MOS and some V-MOS.
  • the term “lateral component” means a component that is totally or partially lateral.
  • the operation of a lateral transistor 1 in relation with FIG. 1 is briefly described.
  • the transistor 1 shown in section comprises a semiconductor substrate 10 which comprises at least one layer C1 on which metallizations of the source 20 are deposited.
  • These passivation devices have the particular function of protecting the semiconductor surface from a disturbance on the surface or in the vicinity of this surface.
  • the current flows mainly in the part of the layer 1 located between the source and the drain, designated channel.
  • a problem encountered with these lateral transistors is that of the accumulation of electrons in the passivation device during the operation of the transistor, in particular in the device 50 'located between the metallizations of the gate and the drain. These electrons thus trapped are responsible for many problems:
  • This type of effect also causes a slow and gradual degradation of the component that directly impacts its operational reliability.
  • the parasitic effects of this type are called lagging effects ("lag" in English). They are already present in the GaAs and InP side components operating at peak voltages of less than 30 V. They are very much reinforced in the components under development based on large bandgap semiconductors (compounds H1- N and SiC), intended to operate at much higher peak voltages, between 60 and 300 V depending on the case.
  • the high voltage moves the electronic energy distribution towards high energies.
  • Increasing the semiconductor band gap reduces the potential steps between semiconductor and insulator. Both of these effects favor the injection of electrons into the insulation.
  • the injected electrons are located in deep levels of the insulation, where they can remain very long if no external excitation (light, thermal agitation, strong electric field) comes dislodge them.
  • a solution to limit the effects due to the accumulation of electrons consists in exploiting only a small part of the potentialities offered by the electrical properties of the semiconductor material.
  • the prototypes of current HEMT GaN transistors are operated between 25 and 30 V instead of the 70 to 100 V allowed by the breakdown field of the material.
  • the object of the invention is to reduce the accumulation of electrons in the passivation device during the operation of the transistor regardless of the use of side field plates.
  • the invention may optionally be used in addition to side field plates.
  • the invention proposes a lateral semiconductor electronic component, the semiconductor comprising at least one layer C1 on which at least one passivation device is disposed, the layer C1 having a minimum of conduction band MBC1 .
  • the passivation device comprises at least one elementary cell itself comprising at least one barrier layer C2 disposed on the layer C1 and a collection layer C3 disposed on the layer C2, of minimum conduction band respective MBC2 and MBC3, with MBC2 greater than MBC1 and MBC3 and that the C2 layer has a thickness of less than 20 nm, this cell aiming at to avoid an accumulation of electrons in the passivation device during the operation of the component.
  • the role of the barrier layer C2 is to oppose the passage of electrons from the layer C1.
  • the role of the C3 collection layer is to collect the electrons which have crossed the C2 layer or which have momentarily stopped there, stored temporarily in deep levels.
  • the layer C2 is such that it induces a steep potential barrier for the electrons that would like to pass from the layer C1 to the layer C2.
  • the layer C2 must be sufficiently fine to allow the passage of the layer C2 towards the layer C1 or the layer C3 of the electrons which could be stored in deep levels of the layer C2.
  • It preferably comprises a stack of several elementary cells, for example from 10 to 20 cells, so as to form a protection of sufficient thickness for the layer C1.
  • the role of the C3 layer is also to evacuate to the drain the electrons collected.
  • the drain metallization is configured so as to allow the passage without electrically of the electrons of the layer C3 to this electrode: according to a characteristic of the invention, the passivation device being located next to a drain which comprises a metallization, each layer C3 of the elementary cell or cells is in contact with the metallization of the drain.
  • the layer C3 has a resistivity of less than 10 12 Ohm.cm.
  • the layer C3 advantageously has a thickness less than
  • the stack has a thickness of less than 1.5 ⁇ m.
  • the layer C2 is a silicon oxide layer and the layer C3 is a layer of silicon nitride or amorphous silicon.
  • the layer C2 is an aluminum nitride layer and the layer C3 is a layer of gallium nitride or aluminum-gallium nitride or gallium-indium nitride or a nitride nitride compound. aluminum-gallium-indium or silicon carbide.
  • the layer C2 is a layer of carbon or carbon-nitrogen compounds and the layer C3 is a layer of silicon carbide or silicon.
  • the carbon is for example SP3 or diamond.
  • the component is a transistor, for example a MESFET or HEMT or MOS type transistor.
  • the component is a microwave power transistor.
  • the invention also relates to the use of the component at peak voltages of between 50 and 350 V.
  • FIG. 1 already described schematically represents a transistor of the state of the art seen in section
  • FIG. 2 schematically represents an exemplary embodiment of a passivation device according to the invention, comprising an elementary cell
  • FIG. 3 schematically represents the conduction band minima for the layers C1, C2 and C3 as a function of the direction. perpendicular to the surface of the layer C1
  • Figure 4 shows schematically an example of a passivation device comprising a stack of elementary cells
  • Figure 5 schematically shows a metallization of the drain between two passivation devices.
  • the invention will be described by taking a transistor as an example of a component.
  • the transistor may be a MESFET or HEMT or MOS type transistor.
  • the traditional passivation insulator is replaced by a passivation device which comprises an elementary cell 52; this cell 52 comprises a layer C2 called barrier layer disposed on the layer C1 and, on the layer C2, a layer C3 called collection layer.
  • the role of the barrier layer C2 is to oppose the passage of electrons from the layer C1.
  • the role of the collection layer is to oppose the passage of electrons from the layer C1.
  • C3 is to collect and evacuate towards the drain the electrons which have crossed the layer C2 or which have momentarily stopped there, stored temporarily in deep levels.
  • the layers C1, C2 and C3 have a conduction band whose minima are respectively designated MBC1, MBC2 and MBC3, as shown in FIG. 3.
  • MBC2 is greater than MBC1 and greater than
  • MBC3 There is no imposed positioning for MBC3 with respect to MBC1, as shown in the figure.
  • the layer C2 induces a steep potential barrier for the electrons that would like to pass from the layer C1 to the layer C2.
  • the thickness of the layer C2 must be sufficiently thick to prevent the passage of the vast majority (> 99%) of the electrons flowing in the layer C1 when the transistor is in operation. On the other hand, it must be sufficiently fine so that electrons that could have been stored in deep layers of the layer C2 are allowed to pass through the tunneling effect of the layer C2 towards the layer C1 or the layer C3.
  • the layer C2 consists of a usual insulator such as SiO 2, Si 3 N 4, AlN, BN, C, CN, etc.
  • the optimum thickness is between 3 and 15 nm.
  • the layer C3 is not necessarily very insulating, but it must have a breakdown electric field as strong as possible. Indeed, it is necessary to avoid as much as possible breakdown phenomena since we are always looking for a good voltage resistance of the transistor.
  • a minimum of low MBC3 conduction band generally leads to a weak breakdown field.
  • the latter can nevertheless be increased by adjusting the thickness of the layer C3: indeed, the effective breakdown field of the layer C3 is even larger than the layer is thin. This is a consequence of the nature of the main breakdown mechanism: impact ionization.
  • This layer C3 plays the role of an electron quantum well. If the layer is too thin, the energy of the first bound level where the electrons are stopped in the quantum well will go up, which risk of diminishing collection efficiency.
  • the optimum thickness is between 1 and 20 nm.
  • the role of the C3 layer is also to evacuate to the drain the electrons collected.
  • the drain metallization 40 is configured to allow the passage without electric obstacle electrons of the C3 layer to this electrode.
  • This electrode therefore has at least one contact zone with the layer C3, as illustrated in FIG.
  • the passivation device 50 comprises a stack of elementary cells 52 so as to form, for the layer C1, a protection of sufficient thickness, typically between 0.1 and 1 ⁇ m.
  • This stack can be supplemented by a thick insulation type C2 layer.
  • Examples of stacking of elementary cells were carried out. Each layer measuring approximately 6 nm thick, a bilayer elementary cell measures approximately 12 nm and the superlattice constituted by the stack reaches approximately 240 nm.
  • the layers C2 and C3 are for example deposited on the entire surface of the substrate, that is to say on the layer C1.
  • a trench is dug in the stack up to the layer C1 and the metal of the drain is deposited on the sides of the trench so that at least the edges of the layer C3 are in contact with the metal.
  • the metal can fill the whole trench.
  • the layers C2 are silicon oxide layers and the layers C3 are silicon nitride or amorphous silicon layers. They are for example conventionally deposited by plasma-enhanced chemical vapor deposition or "PECVD", acronym for the Anglo-Saxon expression “Plasma Enhanced Chemical Vapor Deposition”.
  • the layers C2 are aluminum nitride layers and the layers C3 of the gallium nitride or aluminum gallium nitride or gallium indium nitride layers or a compound of aluminum nitride-gallium-indium or silicon carbide.
  • PVD sputtering
  • CVD chemical vapor deposition
  • the layers C2 are layers of carbon or carbon-nitrogen compounds and the layers C3 of the layers of silicon carbide or silicon.
  • the carbon is for example SP3 or diamond. They are for example conventionally deposited by "PECVD", or by "CVD”.
  • This third superlattice has several advantages: a high thermal conductivity of the layers C2, etching of the layers, by plasma etching, based on oxygenated or fluorinated precursors, selective with respect to a C1 layer in GaN or AlGaN, a high thermal conductivity C3 layers, for the silicon carbide version.
  • the C2 layers are doped to introduce fixed charges as desired, and / or the C3 layers are doped to optimize the overall field profile and / or the electrical conduction in the C3 collector layers.

Abstract

The invention relates to an electronic component provided with a transversal semiconductor which comprises at least one layer (C1) on which at least one passivation device is arranged and which comprises a minimum of a conduction band (MBC1). The passivation device comprises at least one elementary cell (52) which is provided with at least one barrier layer (C1) and a collection layer (C2) placed on the layer (C1) and a collection layer (C3) placed on the layer (C2), minimum of respective conduction band MBC2 and MBC3, wherein the MBC2 is greater that MBC1 et MBC3 and the layer (C2) thickness is less than 20 nm, the cell (52) is used for avoiding an accumulation of electrons in the passivation device (50) during the component operation.

Description

DISPOSITIF DE PASSIVATION D'UN COMPOSANT A SEMICONDUCTEUR LATERAL DEVICE FOR PASSIVATING A SIDE SEMICONDUCTOR COMPONENT
Le domaine de l'invention est celui des composants électroniques latéraux fonctionnant à haute tension et plus particulièrement celui des composants hyperfréquences de puissance. Ces composants sont par exemple des transistors. Un composant latéral est un composant dans lequel la circulation du courant principal s'effectue parallèlement à la surface du substrat sur au moins une partie de son trajet dans le composant.The field of the invention is that of lateral electronic components operating at high voltage and more particularly that of microwave power components. These components are, for example, transistors. A side component is a component in which the flow of the main stream is parallel to the surface of the substrate over at least part of its path in the component.
Les transistors MESFET (acronyme de l'expression anglo- saxonne « Métal Semi-conductor Field Effect Transistor ») latéraux, presque tous les transistors MESFET GaAs, les transistors HEMTs, (acronyme de l'expression anglosaxonne « High Electron Mobility Transistor ») les LD- MOS1 l'immense majorité des transistors MOS des circuits numériques en silicium sont des composants totalement latéraux ou presque totalement latéraux. Parmi les transistors MOS (acronyme de l'expression anglo- saxonne « Métal Oxyde Semi-conductor »), les transistors D-MOS sont partiellement latéraux. La catégorie des transistors purement verticaux, c'est- à-dire non-latéraux, comprend la majorité des transistors bipolaires, les transistors à induction électrostatique (Static Induction Transistors ou SIT, à grille Schottky ou P/N), certains U-MOS et certains V-MOS. Dans la suite on entend par composant latéral un composant totalement ou partiellement latéral.The MESFET transistors (lateral), almost all GaAs MESFET transistors, the HEMT transistors (acronym for the English expression "High Electron Mobility Transistor") LD-MOS 1 The vast majority of MOS transistors in silicon digital circuits are totally lateral or almost completely lateral components. Among the MOS transistors (acronym for the term "Metal Oxide Semi-conductor"), the D-MOS transistors are partially lateral. The category of purely vertical, that is, non-lateral, transistors comprises the majority of bipolar transistors, electrostatic induction transistors (Static Induction Transistors or SIT, Schottky gate or P / N), some U-MOS and some V-MOS. In the following, the term "lateral component" means a component that is totally or partially lateral.
On rappelle brièvement le fonctionnement d'un transistor latéral 1 en relation avec la figure 1. Le transistor 1 représenté en coupe comprend un substrat 10 en semi-conducteur qui comprend au moins une couche C1 sur laquelle sont déposées des métallisations de la source 20, de la grille 30 et du drain 40 entre lesquelles sont déposés des dispositifs de passivation 50' en matériau isolant. Ces dispositifs de passivation ont notamment pour fonction de protéger la surface du semi-conducteur d'une perturbation en surface ou au voisinage de cette surface. Le courant circule principalement dans la partie de la couche 1 située entre la source et le drain, désignée canal. Un problème rencontré avec ces transistors latéraux est celui de l'accumulation d'électrons dans le dispositif de passivation au cours du fonctionnement du transistor, notamment dans le dispositif 50' situé entre les métallisations de la grille et du drain. Ces électrons ainsi piégés sont responsables de nombreux problèmes :The operation of a lateral transistor 1 in relation with FIG. 1 is briefly described. The transistor 1 shown in section comprises a semiconductor substrate 10 which comprises at least one layer C1 on which metallizations of the source 20 are deposited. the gate 30 and the drain 40 between which are deposited passivation devices 50 'of insulating material. These passivation devices have the particular function of protecting the semiconductor surface from a disturbance on the surface or in the vicinity of this surface. The current flows mainly in the part of the layer 1 located between the source and the drain, designated channel. A problem encountered with these lateral transistors is that of the accumulation of electrons in the passivation device during the operation of the transistor, in particular in the device 50 'located between the metallizations of the gate and the drain. These electrons thus trapped are responsible for many problems:
- ils provoquent un pincement électro-statique parasite du canal dans la zone grille-drain,they cause a parasitic electro-static nip of the channel in the grid-drain zone,
- ils augmentent la résistance du dispositif à l'état passant,they increase the resistance of the device in the on state,
- ils font chuter l'excursion (ou plage de variation) en courant, la densité de puissance disponible, le rendement de conversion énergétique du système qui comporte le composant, ce système étant par exemple un amplificateur ou un oscillateur,they reduce the excursion (or range of variation) in current, the available power density, the energy conversion efficiency of the system which comprises the component, this system being for example an amplifier or an oscillator,
- ils provoquent de graves instabilités lentes, plus ou moins réversibles, des caractéristiques du composant, instabilités qui dégradent les performances des systèmes qui comportent le composant,- they cause severe slow instabilities, more or less reversible, characteristics of the component, instabilities that degrade the performance of systems that include the component,
- ils rendent impossible l'obtention de modèles électriques fiables, modèles absolument nécessaires pour l'ingénierie des systèmes qui comportent le composant.they make it impossible to obtain reliable electrical models, absolutely necessary models for the engineering of the systems that comprise the component.
Ce type d'effets provoque aussi une dégradation lente et progressive du composant qui impacte directement sur sa fiabilité opérationnelle.This type of effect also causes a slow and gradual degradation of the component that directly impacts its operational reliability.
Les effets parasites de ce type sont appelés effets de traînage (« lag » en anglosaxon). Ils sont déjà présents dans les composants latéraux à base de GaAs et InP fonctionnant à des tensions de crête inférieures à 30 V. Ils sont très renforcés dans les composants en cours de développement à base de semi-conducteurs à grande bande interdite (composés Hl-N et SiC), destinés à fonctionner à des tensions crête bien supérieures, entre 60 et 300 V selon les cas.The parasitic effects of this type are called lagging effects ("lag" in English). They are already present in the GaAs and InP side components operating at peak voltages of less than 30 V. They are very much reinforced in the components under development based on large bandgap semiconductors (compounds H1- N and SiC), intended to operate at much higher peak voltages, between 60 and 300 V depending on the case.
La forte tension déplace la distribution énergétique électronique vers les hautes énergies. L'augmentation de la bande interdite du semiconducteur réduit les marches de potentiel entre semi-conducteur et isolant. Ces deux effets favorisent l'injection d'électrons dans l'isolant. Les électrons injectés se localisent dans des niveaux profonds de l'isolant, où ils peuvent rester très longtemps si aucune excitation externe ( lumière, agitation thermique, fort champ électrique ) ne vient les en déloger. Une solution pour limiter les effets dus à l'accumulation des électrons, consiste à n'exploiter qu'une petite partie des potentialités offertes par les propriétés électriques du matériau semi-conducteur. Pour donner un ordre de grandeur, on fait fonctionner les prototypes de transistors HEMT GaN actuels entre 25 et 30 V au lieu des 70 à 100 V qu'autoriserait le champ de claquage du matériau. On en tire des densités de puissance de 3 à 6 W/mm sur des petits transistors alors que l'on pourrait en espérer plus de 10 W/mm, le record mondial se situant actuellement vers 36 W/mm sur un petit transistor. Une autre solution porte sur l'adjonction de plaques de champ de part et d'autre de la grille du transistor. L'utilisation de ces plaques de champ latérales peut permettre de limiter l'amplitude des effets, en réduisant l'amplitude du champ électrique en bord de grille, mais il s'agit d'une réduction quantitative et non d'une suppression qualitative. Le flux de porteurs à forte énergie est plus faible, mais il reste encore une proportion des, porteurs du canal du transistor qui peuvent être injectés dans l'isolant et y être stockés. Les effets délétères sont minimisés et ralentis, mais ils sont encore présents.The high voltage moves the electronic energy distribution towards high energies. Increasing the semiconductor band gap reduces the potential steps between semiconductor and insulator. Both of these effects favor the injection of electrons into the insulation. The injected electrons are located in deep levels of the insulation, where they can remain very long if no external excitation (light, thermal agitation, strong electric field) comes dislodge them. A solution to limit the effects due to the accumulation of electrons, consists in exploiting only a small part of the potentialities offered by the electrical properties of the semiconductor material. To give an order of magnitude, the prototypes of current HEMT GaN transistors are operated between 25 and 30 V instead of the 70 to 100 V allowed by the breakdown field of the material. We draw power densities of 3 to 6 W / mm on small transistors while we could expect more than 10 W / mm, the world record is currently around 36 W / mm on a small transistor. Another solution relates to the addition of field plates on either side of the gate of the transistor. The use of these lateral field plates can make it possible to limit the amplitude of the effects by reducing the amplitude of the electric field at the edge of the grid, but it is a quantitative reduction and not a qualitative suppression. The carrier flow at high energy is lower, but there is still a proportion of transistor channel carriers that can be injected into the insulation and stored there. The deleterious effects are minimized and slowed down, but they are still present.
Le but de l'invention est de réduire l'accumulation d'électrons dans le dispositif de passivation au cours du fonctionnement du transistor indépendamment de l'utilisation de plaques de champ latérales.The object of the invention is to reduce the accumulation of electrons in the passivation device during the operation of the transistor regardless of the use of side field plates.
L'invention peut être éventuellement utilisée en complément de plaques de champ latérales.The invention may optionally be used in addition to side field plates.
Pour atteindre ce but, l'invention propose un composant électronique à semi-conducteur latéral, le semi-conducteur comprenant au moins une couche C1 sur laquelle est disposé au moins un dispositif de passivation, la couche C1 présentant un minimum de bande de conduction MBC1. Il est principalement caractérisé en ce que le dispositif de passivation comporte au moins une cellule élémentaire comprenant elle-même au moins une couche barrière C2 disposée sur la couche C1 et une couche de collection C3 disposée sur la couche C2, de minimum de bande de conduction respectif MBC2 et MBC3, avec MBC2 supérieure à MBC1 et MBC3 et en ce que la couche C2 présente une épaisseur inférieure à 20 nm, cette cellule visant à éviter une accumulation d'électrons dans le dispositif de passivation au cours du fonctionnement du composant.To achieve this object, the invention proposes a lateral semiconductor electronic component, the semiconductor comprising at least one layer C1 on which at least one passivation device is disposed, the layer C1 having a minimum of conduction band MBC1 . It is mainly characterized in that the passivation device comprises at least one elementary cell itself comprising at least one barrier layer C2 disposed on the layer C1 and a collection layer C3 disposed on the layer C2, of minimum conduction band respective MBC2 and MBC3, with MBC2 greater than MBC1 and MBC3 and that the C2 layer has a thickness of less than 20 nm, this cell aiming at to avoid an accumulation of electrons in the passivation device during the operation of the component.
Le rôle de la couche barrière C2 est de s'opposer au passage des électrons en provenance de la couche C1. Le rôle de la couche de collection C3 est de collecter les électrons qui ont franchi la couche C2 ou qui s'y sont momentanément arrêtés, stockés temporairement dans des niveaux profonds.The role of the barrier layer C2 is to oppose the passage of electrons from the layer C1. The role of the C3 collection layer is to collect the electrons which have crossed the C2 layer or which have momentarily stopped there, stored temporarily in deep levels.
La couche C2 est telle qu'elle induit une barrière de potentiel abrupte pour les électrons qui voudraient passer de la couche C1 vers la couche C2. La couche C2 doit être suffisamment fine pour autoriser le passage de la couche C2 vers la couche C1 ou la couche C3 des électrons qui ont pu être stockés dans des niveaux profonds de la couche C2.The layer C2 is such that it induces a steep potential barrier for the electrons that would like to pass from the layer C1 to the layer C2. The layer C2 must be sufficiently fine to allow the passage of the layer C2 towards the layer C1 or the layer C3 of the electrons which could be stored in deep levels of the layer C2.
Il comprend de préférence un empilement de plusieurs cellules élémentaires par exemple de 10 à 20 cellules de manière à former pour la couche C1 une protection d'épaisseur suffisante.It preferably comprises a stack of several elementary cells, for example from 10 to 20 cells, so as to form a protection of sufficient thickness for the layer C1.
Le rôle de la couche C3 est aussi d'évacuer vers le drain les électrons collectés. Pour ce faire la métallisation de drain est configurée de manière à autoriser le passage sans obstacle électrique des électrons de la couche C3 vers cette électrode : selon une caractéristique de l'invention, le dispositif de passivation étant situé à côté d'un drain qui comporte une métallisation, chaque couche C3 de la ou des cellules élémentaires est en contact avec la métallisation du drain.The role of the C3 layer is also to evacuate to the drain the electrons collected. To do this, the drain metallization is configured so as to allow the passage without electrically of the electrons of the layer C3 to this electrode: according to a characteristic of the invention, the passivation device being located next to a drain which comprises a metallization, each layer C3 of the elementary cell or cells is in contact with the metallization of the drain.
Selon une autre caractéristique de l'invention, la couche C3 présente une résistivité inférieure à 1012 Ohm.cm. La couche C3 présente avantageusement une épaisseur inférieure àAccording to another characteristic of the invention, the layer C3 has a resistivity of less than 10 12 Ohm.cm. The layer C3 advantageously has a thickness less than
20 nm.20 nm.
De préférence, l'empilement présente une épaisseur inférieure à 1.5 μm.Preferably, the stack has a thickness of less than 1.5 μm.
Selon un premier mode de réalisation, la couche C2 est une couche d'oxyde de silicium et la couche C3 est une couche de nitrure de silicium ou de silicium amorphe.According to a first embodiment, the layer C2 is a silicon oxide layer and the layer C3 is a layer of silicon nitride or amorphous silicon.
Selon un deuxième mode de réalisation, la couche C2 est une couche de nitrure d'aluminium et la couche C3 est une couche de nitrure de gallium ou de nitrure d'aluminium-gallium ou de nitrure de gallium-indium ou un composé de nitrure d'aluminium-gallium-indium ou de carbure de silicium. Selon un troisième mode de réalisation, la couche C2 est une couche de carbone ou de composés carbone-azote et la couche C3 est une couche de carbure de silicium ou de silicium. Le carbone est par exemple du SP3 ou du diamant. Selon une caractéristique de l'invention, le composant est un transistor, par exemple un transistor de type MESFET ou HEMT ou MOS.According to a second embodiment, the layer C2 is an aluminum nitride layer and the layer C3 is a layer of gallium nitride or aluminum-gallium nitride or gallium-indium nitride or a nitride nitride compound. aluminum-gallium-indium or silicon carbide. According to a third embodiment, the layer C2 is a layer of carbon or carbon-nitrogen compounds and the layer C3 is a layer of silicon carbide or silicon. The carbon is for example SP3 or diamond. According to one characteristic of the invention, the component is a transistor, for example a MESFET or HEMT or MOS type transistor.
Selon une autre caractéristique de l'invention, le composant est un transistor hyperfréquence de puissance.According to another characteristic of the invention, the component is a microwave power transistor.
L'invention concerne également l'utilisation du composant à des tensions crêtes comprises entre 50 et 350 V.The invention also relates to the use of the component at peak voltages of between 50 and 350 V.
D'autres caractéristiques et avantages de l'invention apparaîtront à la lecture de la description détaillée qui suit, faite à titre d'exemple non limitatif et en référence aux dessins annexés dans lesquels : la figure 1 déjà décrite représente schématiquement un transistor de l'état de la technique vu en coupe,Other features and advantages of the invention will appear on reading the detailed description which follows, given by way of nonlimiting example and with reference to the appended drawings in which: FIG. 1 already described schematically represents a transistor of the state of the art seen in section,
Ia figure 2 représente schématiquement un exemple de réalisation d'un dispositif de passivation conforme à l'invention, comportant une cellule élémentaire, la figure 3 représente schématiquement les minima de bande de conduction pour les couches C1 , C2 et C3 en fonction de la direction perpendiculaire à la surface de la couche C1 , la figure 4 représente schématiquement un exemple de dispositif de passivation comprenant un empilement de cellules élémentaires, la figure 5 représente schématiquement une métallisation du drain comprise entre deux dispositifs de passivation.FIG. 2 schematically represents an exemplary embodiment of a passivation device according to the invention, comprising an elementary cell, FIG. 3 schematically represents the conduction band minima for the layers C1, C2 and C3 as a function of the direction. perpendicular to the surface of the layer C1, Figure 4 shows schematically an example of a passivation device comprising a stack of elementary cells, Figure 5 schematically shows a metallization of the drain between two passivation devices.
On va décrire l'invention en prenant un transistor comme exemple de composant. Le transistor peut être un transistor de type MESFET ou HEMT ou MOS.The invention will be described by taking a transistor as an example of a component. The transistor may be a MESFET or HEMT or MOS type transistor.
Selon un premier mode de réalisation de l'invention décrit en relation avec la figure 2, l'isolant de passivation traditionnel est remplacé par un dispositif de passivation qui comporte une cellule élémentaire 52 ; cette cellule 52 comprend une couche C2 dite couche barrière disposée sur la couche C1 et, sur la couche C2, une couche C3 dite couche de collection. Le rôle de la couche barrière C2 est de s'opposer au passage des électrons en provenance de la couche C1. Le rôle de la couche de collectionAccording to a first embodiment of the invention described with reference to FIG. 2, the traditional passivation insulator is replaced by a passivation device which comprises an elementary cell 52; this cell 52 comprises a layer C2 called barrier layer disposed on the layer C1 and, on the layer C2, a layer C3 called collection layer. The role of the barrier layer C2 is to oppose the passage of electrons from the layer C1. The role of the collection layer
C3 est de collecter et évacuer vers le drain les électrons qui ont franchi la couche C2 ou qui s'y sont momentanément arrêtés, stockés temporairement dans des niveaux profonds.C3 is to collect and evacuate towards the drain the electrons which have crossed the layer C2 or which have momentarily stopped there, stored temporarily in deep levels.
Les couches C1 , C2 et C3 ont une bande de conduction dont les minima sont respectivement désignés MBC1 , MBC2 et MBC3, comme illustré figure 3. Selon l'invention, MBC2 est supérieur à MBC1 et supérieur àThe layers C1, C2 and C3 have a conduction band whose minima are respectively designated MBC1, MBC2 and MBC3, as shown in FIG. 3. According to the invention, MBC2 is greater than MBC1 and greater than
MBC3. Il n'y a pas de positionnement imposé pour MBC3 par rapport à MBC1 , comme illustré sur la figure.MBC3. There is no imposed positioning for MBC3 with respect to MBC1, as shown in the figure.
De la sorte, la couche C2 induit une barrière de potentiel abrupte pour les électrons qui voudraient passer de la couche C1 vers la couche C2.In this way, the layer C2 induces a steep potential barrier for the electrons that would like to pass from the layer C1 to the layer C2.
En outre, l'épaisseur de la couche C2 doit être suffisamment épaisse pour empêcher le passage de la très grande majorité ( > 99% ) des électrons qui circulent dans la couche C1 lorsque le transistor est en opération. Elle doit être par contre suffisamment fine pour, que des électrons qui ont pu être stockés dans des niveaux profonds de la couche C2, soient autorisés à passer par effet tunnel de la couche C2 vers la couche C1 ou la couche C3. En pratique, lorsque la couche C2 est constituée d'un isolant usuel tel que SiO2, Si3N4, AIN, BN, C, CN, etc, l'épaisseur optimale se situe entre 3 et 15 nm.In addition, the thickness of the layer C2 must be sufficiently thick to prevent the passage of the vast majority (> 99%) of the electrons flowing in the layer C1 when the transistor is in operation. On the other hand, it must be sufficiently fine so that electrons that could have been stored in deep layers of the layer C2 are allowed to pass through the tunneling effect of the layer C2 towards the layer C1 or the layer C3. In practice, when the layer C2 consists of a usual insulator such as SiO 2, Si 3 N 4, AlN, BN, C, CN, etc., the optimum thickness is between 3 and 15 nm.
La couche C3 n'est pas forcément très isolante, mais elle doit présenter un champ électrique de claquage aussi fort que possible. En effet, il faut éviter autant que possible les phénomènes de claquage puisque l'on recherche toujours une bonne tenue en tension du transistor.The layer C3 is not necessarily very insulating, but it must have a breakdown electric field as strong as possible. Indeed, it is necessary to avoid as much as possible breakdown phenomena since we are always looking for a good voltage resistance of the transistor.
Un minimum de bande de conduction MBC3 faible conduit généralement à un champ de claquage faible. Ce dernier peut néanmoins être augmenté en ajustant l'épaisseur de la couche C3 : en effet, le champ effectif de claquage de la couche C3 est d'autant plus grand que la couche est fine. C'est une conséquence de la nature du principal mécanisme de claquage : l'ionisation par impact. Cette couche C3 joue le rôle d'un puits quantique à électrons. Si la couche est trop fine, l'énergie du premier niveau lié où les électrons sont arrêtés dans le puits quantique va monter, ce qui risque de diminuer l'efficacité de collection. L'épaisseur optimale se situe entre 1 et 20 nm.A minimum of low MBC3 conduction band generally leads to a weak breakdown field. The latter can nevertheless be increased by adjusting the thickness of the layer C3: indeed, the effective breakdown field of the layer C3 is even larger than the layer is thin. This is a consequence of the nature of the main breakdown mechanism: impact ionization. This layer C3 plays the role of an electron quantum well. If the layer is too thin, the energy of the first bound level where the electrons are stopped in the quantum well will go up, which risk of diminishing collection efficiency. The optimum thickness is between 1 and 20 nm.
Le rôle de la couche C3 est aussi d'évacuer vers le drain les électrons collectés. Pour ce faire la métallisation de drain 40 est configurée de manière à autoriser le passage sans obstacle électrique des électrons de la couche C3 vers cette électrode. Cette électrode présente donc au moins une zone de contact avec la couche C3, comme illustré figure 5.The role of the C3 layer is also to evacuate to the drain the electrons collected. To do this the drain metallization 40 is configured to allow the passage without electric obstacle electrons of the C3 layer to this electrode. This electrode therefore has at least one contact zone with the layer C3, as illustrated in FIG.
Selon un autre mode de réalisation décrit en relation avec la figure 4, le dispositif de passivation 50 comprend un empilement de cellules élémentaires 52 de manière à former pour la couche C1 une protection d'épaisseur suffisante, typiquement comprise entre 0.1 et 1 μm. Cet empilement peut être complété par un isolant épais de type couche C2.According to another embodiment described with reference to FIG. 4, the passivation device 50 comprises a stack of elementary cells 52 so as to form, for the layer C1, a protection of sufficient thickness, typically between 0.1 and 1 μm. This stack can be supplemented by a thick insulation type C2 layer.
Des exemples d'empilement de 20 cellules élémentaires ont été réalisés. Chaque couche mesurant environ 6 nm d'épaisseur, une cellule élémentaire bicouche mesure environ 12 nm et le super-réseau constitué par l'empilement atteint environ 240 nm.Examples of stacking of elementary cells were carried out. Each layer measuring approximately 6 nm thick, a bilayer elementary cell measures approximately 12 nm and the superlattice constituted by the stack reaches approximately 240 nm.
Les couches C2 et C3 sont par exemple déposées sur toute la surface du substrat, c'est-à-dire sur la couche C1. Pour former la métallisation du drain, on creuse une tranchée dans l'empilement jusqu'à la couche C1 et on dépose le métal du drain sur les flancs de la tranchée pour qu'au moins les bords de la couche C3 soient en contact avec le métal. Le métal peut combler toute la tranchée.The layers C2 and C3 are for example deposited on the entire surface of the substrate, that is to say on the layer C1. To form the metallization of the drain, a trench is dug in the stack up to the layer C1 and the metal of the drain is deposited on the sides of the trench so that at least the edges of the layer C3 are in contact with the metal. The metal can fill the whole trench.
Selon un premier mode de réalisation du super-réseau, les couches C2 sont des couches d'oxyde de silicium et les couches C3 des couches de nitrure de silicium ou de silicium amorphe. Elles sont par exemple déposées de manière classique par dépôt chimique en phase vapeur activé par plasma ou « PECVD », acronyme de l'expression anglo- saxonne « Plasma Enhanced Chemical Vapor Déposition ». Selon un deuxième mode de réalisation du super-réseau, les couches C2 sont des couches de nitrure d'aluminium et les couches C3 des couches de nitrure de gallium ou de nitrure d'aluminium-gallium ou de nitrure de gallium-indium ou d'un composé de nitrure d'aluminium-gallium-indium ou de carbure de silicium. Elles sont par exemple déposées de manière classique par pulvérisation cathodique ou « PVD », acronyme de l'expression anglo-saxonne « Physical Vapor Déposition », ou encore par dépôt chimique en phase vapeur ou « CVD », acronyme de l'expression anglo-saxonne « Chemical Vapor Déposition ».According to a first embodiment of the superlattice, the layers C2 are silicon oxide layers and the layers C3 are silicon nitride or amorphous silicon layers. They are for example conventionally deposited by plasma-enhanced chemical vapor deposition or "PECVD", acronym for the Anglo-Saxon expression "Plasma Enhanced Chemical Vapor Deposition". According to a second embodiment of the superlattice, the layers C2 are aluminum nitride layers and the layers C3 of the gallium nitride or aluminum gallium nitride or gallium indium nitride layers or a compound of aluminum nitride-gallium-indium or silicon carbide. They are for example conventionally deposited by sputtering or "PVD", acronym for the expression Anglo-Saxon "Physical Vapor Deposition", or by chemical vapor deposition or "CVD", acronym for the English expression "Chemical Vapor Deposition".
Selon un troisième mode de réalisation du super-réseau, les couches C2 sont des couches de carbone ou de composés carbone-azote et les couches C3 des couches de carbure de silicium ou de silicium. Le carbone est par exemple du SP3 ou du diamant. Elles sont par exemple déposées de manière classique par « PECVD », ou encore par « CVD ». Ce troisième super-réseau présente plusieurs avantages : une forte conductivité thermique des couches C2, une attaque des couches, par gravure plasma, à base de précurseurs oxygénés ou fluorés, sélective par rapport à une couche C1 en GaN ou AIGaN, une forte conductivité thermique des couches C3, pour la version carbure de silicium.According to a third embodiment of the superlattice, the layers C2 are layers of carbon or carbon-nitrogen compounds and the layers C3 of the layers of silicon carbide or silicon. The carbon is for example SP3 or diamond. They are for example conventionally deposited by "PECVD", or by "CVD". This third superlattice has several advantages: a high thermal conductivity of the layers C2, etching of the layers, by plasma etching, based on oxygenated or fluorinated precursors, selective with respect to a C1 layer in GaN or AlGaN, a high thermal conductivity C3 layers, for the silicon carbide version.
Selon une variante, on dope les couches C2 pour introduire des charges fixes selon ce que l'on désire, et/ou on dope les couches C3 pour optimiser le profil global de champ et/ou la conduction électrique dans les couches collectrices C3. According to one variant, the C2 layers are doped to introduce fixed charges as desired, and / or the C3 layers are doped to optimize the overall field profile and / or the electrical conduction in the C3 collector layers.

Claims

REVENDICATIONS
1. Composant électronique à semi-conducteur latéral, le semiconducteur comprenant au moins une couche C1 sur laquelle est disposé au moins un dispositif de passivation (50), la couche C1 présentant un minimum de bande de conduction MBC1 , caractérisé en ce que le dispositif de passivation (50) comporte au moins une cellule élémentaire (52) comprenant elle-même au moins une couche barrière C2 disposée sur la couche C1 et une couche de collection C3 disposée sur la couche C2, de minimum de bande de conduction respectif MBC2 et MBC3, avec MBC2 supérieure à MBC1 et MBC3 et en ce que la couche C2 présente une épaisseur inférieure à 20 nm.1. Lateral semiconductor electronic component, the semiconductor comprising at least one layer C1 on which at least one passivation device (50) is arranged, the layer C1 having a minimum conduction band MBC1, characterized in that the device passivation device (50) comprises at least one elementary cell (52) which itself comprises at least one barrier layer C2 disposed on the layer C1 and a collection layer C3 disposed on the layer C2, of the respective conduction band minimum MBC2 and MBC3, with MBC2 greater than MBC1 and MBC3 and in that the C2 layer has a thickness less than 20 nm.
2. Composant électronique selon la revendication précédente, caractérisé en ce qu'il comprend un empilement de plusieurs cellules élémentaires (52).2. Electronic component according to the preceding claim, characterized in that it comprises a stack of several elementary cells (52).
3. Composant électronique selon la revendication précédente, caractérisé en ce que l'empilement comprend entre 10 à 20 cellules.3. Electronic component according to the preceding claim, characterized in that the stack comprises between 10 to 20 cells.
4. Composant électronique selon l'une quelconque des revendications précédentes, caractérisé en ce que le dispositif de passivation (50) étant situé à côté d'un drain qui comporte une métallisation (40), chaque couche C3 de la ou des cellules élémentaires (52) est en contact avec la métallisation du drain (40).4. Electronic component according to any one of the preceding claims, characterized in that the passivation device (50) is located next to a drain which comprises a metallization (40), each layer C3 of the elementary cell or cells ( 52) is in contact with the metallization of the drain (40).
5. Composant électronique selon l'une quelconque des revendications précédentes, caractérisé en ce que la couche C3 présente une résistivité inférieure à 1012 Ohm.cm.5. Electronic component according to any one of the preceding claims, characterized in that the C3 layer has a resistivity of less than 10 12 Ohm.cm.
6. Composant électronique selon l'une quelconque des revendications précédentes, caractérisé en ce que la couche C3 présente une épaisseur inférieure à 20 nm. 6. Electronic component according to any one of the preceding claims, characterized in that the C3 layer has a thickness of less than 20 nm.
7. Composant électronique selon l'une quelconque des revendications 2 à 6, caractérisé en ce que l'empilement présente une épaisseur inférieure à 1.5 μm.7. Electronic component according to any one of claims 2 to 6, characterized in that the stack has a thickness less than 1.5 microns.
8. Composant électronique selon l'une quelconque des revendications précédentes, caractérisé en ce que la couche C2 est une couche d'oxyde de silicium et la couche C3 est une couche de nitrure de silicium ou de silicium amorphe.8. Electronic component according to any one of the preceding claims, characterized in that the layer C2 is a silicon oxide layer and the layer C3 is a layer of silicon nitride or amorphous silicon.
9. Composant électronique selon l'une quelconque des revendications9. Electronic component according to any one of the claims
1 à 7, caractérisé en ce que la couche C2 est une couche de nitrure d'aluminium et la couche C3 est une couche de nitrure de gallium ou de nitrure d'aluminium-gallium ou de nitrure de gallium-indium ou un composé de nitrure d'aluminium-gallium-indium ou de carbure de silicium.1 to 7, characterized in that the layer C2 is a layer of aluminum nitride and the layer C3 is a layer of gallium nitride or aluminum-gallium nitride or gallium-indium nitride or a nitride compound of aluminum-gallium-indium or silicon carbide.
10. Composant électronique selon l'une quelconque des revendications 1 à 7, caractérisé en ce que la couche C2 est une couche de carbone ou de composés carbone-azote et la couche C3 est une couche de carbure de silicium ou de silicium.10. Electronic component according to any one of claims 1 to 7, characterized in that the layer C2 is a layer of carbon or carbon-nitrogen compounds and the layer C3 is a layer of silicon carbide or silicon.
11. Composant électronique selon la revendication précédente, caractérisé en ce que le carbone est du SP3 ou du diamant.11. Electronic component according to the preceding claim, characterized in that the carbon is SP3 or diamond.
12. Composant électronique selon l'une quelconque des revendications précédentes, caractérisé en ce que le composant est un transistor (1 ).12. Electronic component according to any one of the preceding claims, characterized in that the component is a transistor (1).
13. Composant électronique selon la revendication précédente, caractérisé en ce que le transistor (1) est un transistor de type MESFET ou HEMT ou MOS.13. Electronic component according to the preceding claim, characterized in that the transistor (1) is a MESFET type transistor or HEMT or MOS.
14. Composant électronique selon l'une quelconque des revendications précédentes, caractérisé en ce que le composant est un transistor hyperfréquence de puissance. 14. Electronic component according to any one of the preceding claims, characterized in that the component is a microwave power transistor.
15. Utilisation du composant électronique selon l'une quelconque des revendications précédentes, à des tensions crêtes comprises entre 50 et 350 V. 15. Use of the electronic component according to any one of the preceding claims, at peak voltages of between 50 and 350 V.
PCT/FR2006/002383 2005-10-21 2006-10-20 Device for passivating a transversal semiconductor component WO2007045772A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0510775A FR2892562B1 (en) 2005-10-21 2005-10-21 DEVICE FOR PASSIVATING A LATERAL SEMICONDUCTOR COMPONENT
FR0510775 2005-10-21

Publications (1)

Publication Number Publication Date
WO2007045772A1 true WO2007045772A1 (en) 2007-04-26

Family

ID=36609505

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2006/002383 WO2007045772A1 (en) 2005-10-21 2006-10-20 Device for passivating a transversal semiconductor component

Country Status (2)

Country Link
FR (1) FR2892562B1 (en)
WO (1) WO2007045772A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030205812A1 (en) * 2000-06-22 2003-11-06 Swanson Leland S. Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and method of fabrication
US20040056360A1 (en) * 2002-03-13 2004-03-25 Macronix International Co., Ltd. Memory device and method for forming a passivation layer thereon
WO2005117129A1 (en) * 2004-05-22 2005-12-08 Cree, Inc. Improved dielectric passivation for semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030205812A1 (en) * 2000-06-22 2003-11-06 Swanson Leland S. Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and method of fabrication
US20040056360A1 (en) * 2002-03-13 2004-03-25 Macronix International Co., Ltd. Memory device and method for forming a passivation layer thereon
WO2005117129A1 (en) * 2004-05-22 2005-12-08 Cree, Inc. Improved dielectric passivation for semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BERNAT J ET AL: "Influence of layer structure and surface passivation on performance of AlGaN/GaN HEMTs on Si and SiC substrates", SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, 2003 INTERNATIONAL DEC. 10-12, 2003, PISCATAWAY, NJ, USA,IEEE, 10 December 2003 (2003-12-10), pages 437 - 438, XP010686808, ISBN: 0-7803-8139-4 *

Also Published As

Publication number Publication date
FR2892562A1 (en) 2007-04-27
FR2892562B1 (en) 2008-01-18

Similar Documents

Publication Publication Date Title
FR3009131B1 (en) SEMICONDUCTOR SYSTEM AND METHOD OF MANUFACTURING
JP7369725B2 (en) nitride semiconductor device
FR2969386A1 (en) HIGH ELECTRONIC MOBILITY TRANSISTOR WITH GALLIUM NITRIDE AND INDIUM LAYER
EP3240041A1 (en) Normally-off heterojunction transistor with high threshold voltage
EP3913687A1 (en) Electronic component with heterojunction comprising a field plate and a p-doped floating region
EP3350841A1 (en) Enhancement-mode field-effect transistor comprising an algan/gan heterojunction and a p-doped diamond gate
EP3369115A1 (en) Field-effect transistor with optimised performance and gain
WO2017085413A1 (en) Heterojunction diode having an increased non-repetitive surge current
EP3127160B1 (en) Optimized buffer layer for high mobility field-effect transistor
WO2019224448A1 (en) Enhancement-mode high-electron-mobility transistor
EP0055968A2 (en) Field effect transistor, normally in "off" position, having a short switching time
EP4099397A1 (en) Electronic transistor device
WO2007045772A1 (en) Device for passivating a transversal semiconductor component
FR3050573B1 (en) DEVICE WITH SEGMENTED FIELD PLATES
FR2700221A1 (en) Field effect transistor having improved stray capacitance and transconductance properties.
WO2021149599A1 (en) Method for manufacturing nitride semiconductor device and nitride semiconductor device
FR3078198A1 (en) HIGH ELECTRONIC MOBILITY TRANSISTOR IN ENRICHMENT MODE
US20070196993A1 (en) Semiconductor element
FR3047609A1 (en) NORMALLY OPEN TYPE HEMT TRANSISTOR HAVING HIGH THRESHOLD VOLTAGE AND REDUCED CONDUCTION RESISTANCE
JP2017063089A (en) Semiconductor device and method of manufacturing the same
EP4165687A1 (en) Transistor
EP4044251A1 (en) Transistor
EP0145566B1 (en) Power field effect transistor and process for its manufacture
EP4044252A1 (en) Transistor
EP4084085A1 (en) Microelectronic device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06830999

Country of ref document: EP

Kind code of ref document: A1