WO2007034936A1

WO2007034936A1 - Processor, compiler apparatus and program

Info

Publication number: WO2007034936A1
Application number: PCT/JP2006/318920
Authority: WO
Inventors: Yasunori Sakakibara; Shinichi Iwamoto; Takayuki Sugawara
Original assignee: Sonac Incorporated
Priority date: 2005-09-26
Filing date: 2006-09-25
Publication date: 2007-03-29
Also published as: JP3985829B2; JP2007087264A

Abstract

A processor wherein the same executable program can be used regardless of the number of execution calculating parts on board. The processor comprises execution calculating parts, an intermediate data storing part, and a control part that holds information of the wiring between the execution calculating parts and also holds information of the wiring between the intermediate data storing part and each of the execution calculating parts. An executable program, which includes a plurality of pieces of calculation information defining the contents of processings in the execution calculating parts and also includes connection information defining the input/output relationships of the intermediate data between the pieces of calculation information, is divided, in one or more stages, for execution, based on the number of the execution calculating parts, the wiring information and the connection information. At this moment, the control part outputs control information to the execution calculating parts and/or the intermediate data storing part such that an intermediate data of the information of unexecuted calculation is acquired from the intermediate data storing part or stored into the intermediate data storing part.

Description

Specification

Processor, compiler apparatus and program

Technical field

The present invention relates to a processor including one or more execution calculation units that execute a program and a compiler device that generates an executable program for the plug processor.

Background art

[0002] For the purpose of improving the processing speed, various processors including a plurality of execution calculation units for executing a program have been proposed and put into practical use (for example, see Non-Patent Document 1). According to 1, operating system power Executable programs can be processed in parallel in multiple execution calculation units by disposing the executable program into processes and threads and assigning processing to multiple execution calculation units Making it possible.

[0003] In addition, Non-Patent Document 2 describes a processor that executes data processing by setting processing contents in each arithmetic unit and connection between arithmetic units by programming in arithmetic units arranged in a matrix. It is described. When creating executable programs for these processors, it is necessary to consider the number of computing units implemented. In other words, in order to execute the same processing as an executable program created with a processor having a certain number of arithmetic units as targets, for example, with a processor having a smaller number of arithmetic units than the target processor, again, It is necessary to modify the program in consideration of the number of arithmetic units.

[0004] Non-Patent Document 1: Akira Nakamori, "Introduction to Microprocessor 'Architecture", CQ Publishing Co., Ltd., published on April 41, 2004, p. 231 -p. 233

Non-Patent Document 2: Design Wave Magazine, CQ Publisher, August 2004, p. 24-p. 29 Disclosure of Invention

Accordingly, an object of the present invention is to provide a processor that can use the same executable program without an operating system regardless of the number of execution calculation units that execute the program. It is another object of the present invention to provide a compiler device and a program for the processor.

[0006] According to the processor of the present invention, It has one or more execution calculation means that have one or more ports for input and output, each of which has multiple calculation information that defines the processing contents of one execution calculation means, and intermediate data between the calculation information This is a processor that executes an executable program that includes connection information that defines the input / output relationship of the program in one or more stages, and each port has an intermediate data storage means and each execution calculation means. Intermediate data storage means that can be connected and control means for holding connection information that is information about Z or other execution calculation means. The control means, at each stage, includes the number of execution calculation means, connection information, and connection information. Based on the connection information, the calculation information to be executed in the stage is determined, and the execution calculation means for executing the calculation information is performing input / output with the calculation information not executed in the stage. The intermediate data is input / output to / from the intermediate data storage means.

[0007] According to another embodiment of the processor of the present invention,

The execution calculation means is provided corresponding to each port, and selects one intermediate data storage means or another execution calculation means from the connected intermediate data storage means and Z or other execution calculation means, and corresponds. Selection means for connecting to the port, and the control means outputs control information based on the operation information and connection information to be executed at each stage, and the selection means determines whether the intermediate data storage means or the other is in accordance with the control information. It is also preferable to select an execution calculation method.

[0008] Also, according to another embodiment of the processor of the present invention,

The execution calculation means can select a port for inputting / outputting intermediate data, and the control means can select a port for inputting / outputting intermediate data at each stage based on calculation information and connection information to be executed. preferable.

According to the compiler apparatus of the present invention,

A compiler device that outputs an executable program for a processor having one or more predetermined execution calculation units, which analyzes a source program and determines the number of execution calculation units required and the number of execution calculation units in each execution calculation unit. Optimization means for determining the processing contents and the connection relation for input / output of intermediate data between each execution calculation section, operation information for each execution calculation section that encodes the processing contents in each execution calculation section, and The connection information describing the input / output relationship of the intermediate data between the execution calculation units as the input / output relationship of the calculation information executed by the execution calculation unit And a code generation means for generating an executable program.

[0010] According to the program of the present invention,

A computer is caused to function as the compiler apparatus.

Each executable program has calculation information that defines the processing content to be executed by one execution calculation unit, and connection information that specifies the input / output relationship of intermediate data between the calculation information. Based on the number of execution calculation means installed in the processor, between the execution calculation means and between the execution calculation means and the intermediate data storage means, the calculation information to be executed at each stage is determined. By storing intermediate data with computation information that is not executed at each stage in the intermediate data storage means and acquiring it from the Z or intermediate data storage means, the same executable program can be installed regardless of the number of execution calculation means. Grams can be used.

[0012] The execution calculation means has a selection means for each port, and switches between the execution calculation means or the intermediate data storage means as the connection destination. In addition, by providing the execution calculation means with an input / output port selection function for inputting / outputting intermediate data, restrictions on the selection of operation information to be executed are relaxed.

Brief Description of Drawings

[0013] FIG. 1 is a block diagram of a processor according to the present invention.

FIG. 2 is a block diagram of an execution calculation unit.

FIG. 3 is a diagram showing an embodiment of a processor of the present invention configured with four execution calculation units.

FIG. 4 is a diagram showing an embodiment of a processor of the present invention configured with two execution calculation units.

FIG. 5 is a diagram showing one form of a processor of the present invention configured by one execution calculation unit.

FIG. 6 is a diagram showing one form of an executable program output by the compiler apparatus according to the present invention.

FIG. 7 is a diagram showing another form of an executable program output by the compiler apparatus according to the present invention.

FIG. 8 is a diagram illustrating a processing mode assumed by the compiler apparatus.

FIG. 9 is a diagram showing an executable program corresponding to the processing mode shown in FIG. 8.

FIG. 10 is a diagram for explaining an execution method of the executable program shown in FIG. 9. FIG. 11 is a diagram showing another processing mode assumed by the compiler apparatus.

FIG. 12 is a diagram showing an executable program corresponding to the processing mode shown in FIG. 11.

FIG. 13 is a diagram for explaining an execution method of the executable program shown in FIG. 12.

FIG. 14 is a diagram showing connection information.

FIG. 15 is a block diagram of a compiler apparatus according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the following embodiment.

FIG. 1 is a block diagram of a processor according to the present invention. According to FIG. 1, the processor includes one or more execution calculation units 1, an intermediate data storage unit 2, and a control unit 3. Execution calculation unit 1 is connected to other execution calculation units 1 and Z or intermediate data storage unit 2 by line 5. The connection between the execution calculation units 1 is an example, and is not limited to the configuration of FIG. The control unit 3 is connected to the execution calculation unit 1 and the intermediate data storage unit 2 via a bus (not shown), and an execution calculation unit for an executable program stored in a main storage device (not shown) outside the processor. Has a function to control loading to 1.

FIG. 2 is a block diagram of the execution calculation unit 1. According to FIG. 2, the execution calculation unit 1 includes a calculation unit 100, one or more input side multiplexers 101, one or more output side multiplexers 102, and an input / output control unit 103.

[0017] The computing unit 100 also includes, for example, a RISC (Reduced Instruction Set Computer) core, a VLIW (Very Long Instruction Word) core, or computing power arranged in a predetermined number of matrices, and includes one or more input ports and outputs. A port is provided, and the calculation information 602 of the executable program 6 shown in FIG. 6 and FIG. 7 is loaded, and has a function of executing processing according to the calculation information 602. Note that the plurality of execution calculation units 1 provided in the processor shown in FIG. In addition, the input port and output port of the arithmetic unit 100 are also referred to as the input port and output port of the execution calculation unit 1.

[0018] The input side multiplexer 101 is provided for each input port of the arithmetic unit 100, and based on the selection signal 104 from the input / output control unit 103, the output side multiplexer 102 and Z or intermediate data of the other execution calculation unit 1 One line from multiple lines 5 connected to storage 2 This function has a function to select 5 and connect to the corresponding input port of the arithmetic unit 100.

The output-side multiplexer 102 is provided for each output port of the arithmetic unit 100, and based on the selection signal 104 from the input / output control unit 103, the input-side multiplexer 101 and Z or intermediate data of the other execution calculation unit 1 It has a function of selecting one line 5 from a plurality of lines 5 connected to the storage unit 2 and connecting it to the corresponding output port of the arithmetic unit 100.

Based on the control information from the control unit 3, the input / output control unit 103 outputs a selection signal 104 for determining the line 5 to be selected to each input-side multiplexer 101 and output-side multiplexer 102.

Returning to FIG. 1, the intermediate data storage unit 2 temporarily stores the intermediate data output by the execution calculation unit 1 based on the control information from the control unit 3, and also stores the intermediate data temporarily stored. Is output to the execution calculation unit 1.

[0022] The control unit 3 connects the connection information, that is, the information of the intermediate data storage unit 2 and Z or the execution calculation unit 1 to which each input and Z or output port can be connected. The executable program 6 shown in FIG. 6 or 7 is read from a main storage device (not shown), and is based on the number of execution calculation units 1, connection information, and connection information 601 of the executable program 6, 1 The execution calculation unit 1 and the intermediate data storage unit 2 are controlled so as to divide the process into more stages. A more detailed description of the control unit 3 will be described later.

FIGS. 3 to 5 are diagrams showing a configuration example of a processor according to the present invention, and the control unit 3 is omitted for simplicity. In FIG. 3, four execution calculation units 10 to 13 are provided, and the execution calculation units 10 to 13 are bidirectionally connected to all the other execution calculation units and the intermediate data storage unit 2. In FIG. 4, two execution calculation units 10 and 11 are provided. The execution calculation units 10 and 11 are bidirectionally connected to the intermediate data storage unit 2, and the execution calculation units 10 and 11 are actually connected. Connection is made only in the direction from the line calculation unit 10 to the execution calculation unit 11. Furthermore, in FIG. 5, only 10 execution calculation units are provided, and the intermediate data storage unit 2 is connected bidirectionally. The execution calculation units 10 to 13 and the execution calculation unit 1 in FIG. 1 are the same, and the line 5 represents one or more lines collectively.

FIG. 6 and FIG. 7 are diagrams showing the structure of the executable program 6 output from the conoiler device according to the present invention. The compiler apparatus according to the present invention analyzes a source program and Outputs executable program 6 for the processor according to Ming. At this time, the compiler apparatus calculates the required number of execution calculation units 1 regardless of the number of execution calculation units 1 installed in the processor that executes the executable program 6 that is actually output, An executable program 6 is generated based on the calculated number.

According to FIG. 6, the executable program 6 executed by the processor according to the present invention comprises a plurality of execution calculation information 60. The calculation information 602 of each execution calculation information 60 is an instruction to be loaded and executed by one execution calculation unit, and the connection information 601 is the other execution calculation information 60 of the calculation information 602 in the same execution calculation information 60. This information specifies the input / output relationship of intermediate data with the calculation information 602. That is, when the calculation information 602 is loaded into the execution calculation unit 1 and executed, the execution calculation unit 1 is executed by the port number for inputting / outputting intermediate data and the execution calculation unit 1 on the other side. And the information of the port number that the execution calculation unit 1 on the other side inputs / outputs intermediate data.

FIG. 7 is a diagram showing another structure of the executable program 6 output from the compiler apparatus according to the present invention. FIG. 6 differs from FIG. 7 in that only one piece of connection information 601 is provided as the entire connection information 601 in the structure shown in FIG.

Subsequently, the executable program 6 will be described more specifically with reference to FIGS. 8 and 9. FIG. 8 shows a processing mode assumed by the compiler apparatus according to the present invention, and a square frame shows calculation information executed by the execution calculation unit 1. According to Fig. 8, the compiler unit analyzes the source program, uses two execution calculation units, and sets output port # 1 of one execution calculation unit and input port # 1 of the other execution calculation unit to one of the execution calculation units. The processing described in the source program is executed by connecting the output port # 2 of the execution calculation unit and the input port # 2 of the other execution calculation unit to transfer intermediate data.

FIG. 9 shows an executable program 6 corresponding to the processing mode assumed by the conoiler device shown in FIG. Here, the executable program is shown in the structure of FIG. As shown in FIG. 9, the executable program 6 comprises execution calculation information A executed by one execution calculation unit and execution calculation information B executed by the other execution calculation unit. The calculation information included in each execution calculation information defines the processing contents in the execution calculation unit. The connection information of A depends on the output ports # 1 and # 2 of the execution calculation unit 1 that executes the calculation information A, and the input ports # 1 and # 2 of the execution calculation unit that executes the calculation information B and the line 5 respectively. Connect and transfer intermediate data, that is, specify the input / output relationship of intermediate data between computation information!

Next, the operation when the executable program 6 shown in FIG. 9 is executed by the processor having the execution calculation units 10 and 11 shown in FIG. 4 will be described. Here, the input side multiplexer 101 corresponding to the input ports # 1 to # 4 of the execution calculation unit 10 is connected only to the intermediate data storage unit 2, and the output port #k (k = l, 2 of the execution calculation unit 10). , 3, and 4) are connected to the input side multiplexer 101 corresponding to the intermediate data storage unit 2 and the input port #k of the execution calculation unit 11, and to the input port # of the execution calculation unit 11. Input side multiplexer 101 corresponding to k (k = l, 2, 3, 4) corresponds to output port #k (k = l, 2, 3, 4) of intermediate data storage unit 2 and execution calculation unit 10 It is assumed that the output multiplexer 102 corresponding to the output ports # 1 to 4 of the execution calculation unit 11 is connected only to the intermediate data storage unit 2. Accordingly, the connection information held by the control unit 3 is as shown in FIG. Further, the above connection is an example, and the connection of the port numbers on the input side and output side of each execution calculation unit is not limited to the same number.

[0030] The control unit 3 acquires the executable program 6 shown in FIG. 9 from a main storage (not shown) and analyzes it, and the executable program 6 requires two execution calculation units, Connect the output port # 1 of the execution calculator to the input port # 1 of the other execution calculator, and connect the output port # 2 of one execution calculator to the input port # 2 of the other execution calculator Recognize what you need. From the connection information shown in FIG. 14, the control unit 3 causes the execution calculation unit 10 to execute the calculation information A and the calculation information B to be executed by the execution calculation unit 11, and outputs the output port # 1 and the output of the execution calculation unit 10. By causing the output multiplexer 102 corresponding to the port # 2 to select the execution calculator 11 and causing the input multiplexer 101 corresponding to the input port # 1 and the input port # 2 of the execution calculator 11 to select the execution calculator 10. Recognize that the conceiver device can realize the assumed configuration. Therefore, the control unit 3 controls the load of the calculation information A to the execution calculation unit 10 and the load control of the calculation information B to the execution calculation unit 11. Do it. Further, the input / output control units 103 of the execution calculation unit 10 and the execution calculation unit 11 output control information for outputting the selection signal 104 for selecting the line 5 described above. The load control of the calculation information to the execution calculation units 10 and 11 is performed by the control unit 3 even if the control unit 3 acquires the main storage device power (not shown) and loads it to the execution calculation units 10 and 11. Sections 10 and 11 store the calculation information to be loaded !, not shown !, notify the address of the main memory, and each execution calculation section 10 and 11 based on the notification from the control section 3, Not shown! /, The configuration may be such that the calculation information is obtained directly from the main memory.

Thus, the processor having the execution calculation units 10 and 11 shown in FIG. 4 executes the executable program 6 in one stage.

Next, an operation when the executable program 6 shown in FIG. 9 is executed by a processor having only the execution calculation unit 10 shown in FIG. 5 will be described with reference to FIG. It is assumed that the connection information held by the control unit 3 is obtained by removing the execution calculation unit 11 from the connection information of the execution calculation unit 10 in FIG. As shown in FIG. 5, when there is only one execution calculation unit 10 or when there is no execution calculation unit 1 even if there are multiple execution calculation units, the input side multiplexer 101 and the output The side multiplexer 102 can be omitted.

The control unit 3 acquires the executable program 6 shown in FIG. 9 from a main storage (not shown) and analyzes it, and the executable program 6 requires two execution calculation units, Connect the output port # 1 of the execution calculator to the input port # 1 of the other execution calculator, and connect the output port # 2 of one execution calculator to the input port # 2 of the other execution calculator Recognize what you need. Since the control unit 3 recognizes that there is only one execution calculation unit 10 on the processor, the control unit 3 analyzes the connection information, and calculates the calculation information A without any intermediate data input from the other as the first calculation unit A. As the calculation information to be executed on the stage, load control of calculation information A to the execution calculation unit 10 is performed. In addition, since the calculation information B, which is the output destination of the intermediate data of the calculation information A, is not executed at the same time, the control unit 3 performs control for storing the intermediate data required by the calculation information B in the intermediate data storage unit 2. Information is output to the execution calculation unit 10 and the intermediate data storage unit 2. The control information for the execution calculation unit 10 includes information for causing the output side multiplexer 102 corresponding to the output port # 1 and output port # 2 of the execution calculation unit 10 that outputs intermediate data to select the intermediate data storage unit 2. Contains. Further, the control information for the intermediate data storage unit 2 includes information for causing the intermediate data storage unit 2 to store the intermediate data output from the output ports # 1 and # 2 of the execution calculation unit 10.

Reference numeral 40 in FIG. 10 represents the connection state of the execution calculation unit 10 in the first stage, and reference numeral 90 represents calculation information B that does not actually exist when the execution calculation unit 10 executes the calculation information A. This represents an execution calculation unit to be executed. In the connection state indicated by reference numeral 40, the calculation unit 100 of the execution calculation unit 10 executes the calculation information A and outputs intermediate data to the intermediate data storage unit 2.

After the end of the first stage, the control unit 3 uses the remaining calculation information B as calculation information to be executed in the second stage, and performs load control of the calculation information B to the execution calculation unit 10. At the same time, the control unit 3 outputs the intermediate data to the execution calculation unit 10 that executes the calculation information B from the intermediate data storage unit 2 stored in the first stage according to the connection information. Control the execution calculation unit 10 so that the input side multiplexer 101 corresponding to the input ports # 1 and # 2 selects the intermediate data storage unit 2 and the arithmetic unit 100 inputs the intermediate data from the input ports # 1 and # 2. Output information. In addition, control information for causing the intermediate data stored in the first stage to be output to the input ports # 1 and # 2 of the execution calculation unit 10 is output from the intermediate data storage unit 2 to the intermediate data storage unit 2, respectively.

Reference numeral 41 denotes a connection state of the execution calculation unit 10 in the second stage, and reference numeral 90 denotes an execution for executing the calculation information A that does not actually exist when the execution calculation unit 10 executes the calculation information B. Represents the calculation unit. In the connection state indicated by reference numeral 41, the calculation unit 100 of the execution calculation unit 10 executes the calculation information B using the intermediate data from the intermediate data storage unit 2 as an input. As a result, the executable program 6 shown in FIG. 8 is executed by only one execution calculation unit 10.

FIG. 11 and FIG. 12 are diagrams for explaining another example of the executable program 6. FIG. 11 is a diagram illustrating a processing mode assumed by the conoiler device according to the present invention, and a square frame indicates calculation information executed by the execution calculation unit. According to Fig. 11, the compiler device analyzes the source program and uses the five execution calculators to realize the processing described in the source program! / Speak. FIG. 12 shows an executable program 6 corresponding to the processing mode assumed by the compiler apparatus shown in FIG. Here, the executable program is shown in the structure of FIG. As shown in Fig. 12, the executable program 6 includes the operation information A, B, C, D, and E executed by one execution calculation unit 1 and the intermediate data input / output relationship between each operation information. Connection information.

Next, an operation when the executable program 6 shown in FIG. 12 is executed by the processor having the execution calculation units 10 and 11 shown in FIG. 4 will be described with reference to FIG. The connection information held by the control unit 3 is as shown in FIG.

[0040] The control unit 3 acquires the executable program 6 shown in FIG. 12 from a main storage (not shown) and analyzes it, and recognizes that the executable program 6 requires five execution calculation units. . Since control unit 3 recognizes that there are only two execution calculation units 10 and 11 on the processor, it analyzes the connection information and needs intermediate data from other calculation information in the first stage. Toshin ヽ It decides to execute the calculation information A and assigns the execution calculation unit 10 as the execution destination. Subsequently, when the calculation information A decided to be executed is removed from the connection information, calculation information B and calculation information C that do not require intermediate data from other calculation information are executed in the first stage. Candidate for computation information. Subsequently, if one of the candidate computation information, here, computation information B is executed by the execution calculation unit 11, the calculation information to be executed in this stage is placed in the execution calculation unit of the execution destination, and the stage It is determined whether or not a configuration in which the operation information not executed in step 1 is replaced with the intermediate data storage unit 2 can be realized. Here, since it is feasible, the execution calculation unit 11 decides to execute the calculation information B. As a result, the number of pieces of computation information to be executed becomes equal to the number of installed execution calculation units, so the process moves to the execution of the first stage. If this is not possible, other candidates are determined in the same manner.

[0041] For execution of the process, the control unit 3 performs load control of the calculation information A to the execution calculation unit 10, load control of the calculation information B to the execution calculation unit 11, and outputs of the execution calculation unit 10 Select execution calculator 11 for output multiplexer 102 corresponding to ports # 1 and # 2, and select intermediate data storage 2 for output multiplexer 102 corresponding to output ports # 3 and # 4 Control information is output to the execution calculation unit 10 so that the execution calculation unit 11 Execution calculation so that the input side multiplexer 101 corresponding to the output ports # 1 and # 2 selects the execution calculation unit 10, and the output side multiplexer 102 corresponding to the output port # 1 selects the intermediate data storage unit 2. Output control information to part 11. The intermediate data is also received by the intermediate data storage unit 2 and the control information is output so as to be stored. As a result, the processor is in the state indicated by reference numeral 42.

[0042] In the connection state indicated by reference numeral 42, the calculation unit 100 of the execution calculation unit 10 executes the calculation information A. Of the intermediate data output from the execution calculator 10, the intermediate data output from the output ports # 1 and # 2 is input to the execution calculator 11 and output from the output ports # 3 and # 4. Is stored in the intermediate data storage unit 2. The calculation unit 100 of the execution calculation unit 11 receives the intermediate data from the execution calculation unit 10 and executes calculation information B. The intermediate data output from the execution calculation unit 11 is stored in the intermediate data storage unit 2. Is done.

Subsequently, the control unit 3 does not need intermediate data from other calculation information when the calculation information A and B already executed is removed! The execution calculation section 10 is assigned as the execution destination. Subsequently, when the operation information C decided to be executed and the operation information A and B that have already been executed are removed, the operation information D and the operation information E are not obtained without requiring intermediate data from other operation information. Candidates for computation information to be executed at stage 2. Subsequently, when one of the candidate calculation information, here, calculation information E is executed by the execution calculation unit 11, the calculation information to be executed in the stage is placed in the execution calculation unit of the execution destination, and the stage If not, it is determined whether or not it is possible to realize a configuration in which the operation information is replaced with the intermediate data storage unit 2. Here, since it can be realized, it is determined that the execution calculation unit 11 executes the calculation information E. As a result, the number of pieces of calculation information to be executed becomes equal to the number of installed execution calculation units, so that the process moves to the execution of the second stage.

Note that the control unit 3 generally repeats the above processing until each candidate stage has no computation information or until the number of computation information to be executed is equal to the number of execution calculation means. The operation information to be executed is determined.

[0045] For execution of the process, the control unit 3 performs load control of the calculation information C to the execution calculation unit 10 and load control of the calculation information E to the execution calculation unit 11, and executes based on the connection information. The input side multiplexer 101 corresponding to the input port # 4 of the calculation unit 10 selects the intermediate data storage unit 2 and the output side multiplexer 102 corresponding to the output port # 2 selects the intermediate data storage unit 2, and the output port Output control information is output to the execution calculation unit 10 so that the output side multiplexer 10 2 corresponding to # 3 and # 4 selects the execution calculation unit 11, and corresponding to the input ports # 3 and # 4 of the execution calculation unit 11 The control information is output to the input / output control unit 103 of the execution calculation unit 11 so that the input side multiplexer 101 selects the execution calculation unit 10. In addition, intermediate data received from the output port # 4 of the execution calculation unit 10 that executed the calculation information A in the previous stage is also executed for the intermediate data storage unit 2 in the stage. Output to the input port # 4 of the execution calculation unit 10 and output control information so as to store the intermediate data newly received at the relevant stage. As a result, the processor enters a state indicated by reference numeral 43.

In the connection state indicated by reference numeral 43, the calculation unit 100 of the execution calculation unit 10 executes the calculation information C using the intermediate data from the intermediate data storage unit 2 as an input. Of the intermediate data output from the execution calculation unit 10, the intermediate data output from the output port # 2 is stored in the intermediate data storage unit 2, and the intermediate data output from the output ports # 3 and # 4 is Is input to the execution calculation unit 11. The calculation unit 100 of the execution calculation unit 11 receives the intermediate data from the execution calculation unit 10 and executes calculation information E.

Finally, the control unit 3 determines the remaining calculation information D as calculation information to be executed in the third stage, and performs load control to the execution calculation unit 10.

At the same time, the control unit 3 sends control information to the execution calculation unit 10 in order to cause the execution calculation unit 10 to input intermediate data to the execution calculation unit 10 already stored in the intermediate data storage unit 2. Is output. Based on this control information, the input / output control unit 103 of the execution calculation unit 10 selects the intermediate data storage unit 2 by the input side multiplexer 101 corresponding to the input ports # 1, # 2, and # 3. Is output. Also for intermediate data storage unit 2, intermediate data received from output port # 3 of execution calculation unit 10 that executed operation information A in the first stage is input to input port # 3 of execution calculation unit 10. The intermediate data received from output port # 1 of execution calculation unit 11 that has been output and executed operation information B in the first stage is output to input port # 1 of execution calculation unit 10 and output in the second stage. Calculation information C Executed execution The control information is output so that the intermediate data received from the output port # 2 of the calculation unit 10 is output to the input port # 2 of the execution calculation unit 10. As a result, the processor is in a state indicated by reference numeral 44.

In the connection state indicated by reference numeral 44, the calculation unit 100 of the execution calculation unit 10 executes the calculation information D with the intermediate data from the intermediate data storage unit 2 as an input. As a result, the executable program 6 shown in FIG. 11 is executed by the two execution calculation units 10 and 11.

[0050] As described above, the executable program 6 has a relation between the calculation information 602 that defines the processing content to be executed by one execution calculation unit 1 and the intermediate data input / output relationship between the calculation information 602. Based on the number of execution calculation units 1 installed in its own processor, connection information, and connection information 601, the processor control unit 3 has the specified connection information 601, and the executable program 6 is put into multiple stages. By dividing and executing, the same executable program 6 can be used regardless of the number of execution calculation units 1 installed!

[0051] With this, the same software can be used between processors having different numbers of execution calculation units 1 to be mounted due to the mounting area, cost, and the like that are limited depending on the target device.

[0052] In the above description, the port for inputting / outputting intermediate data of the execution calculation unit 1 that executes the calculation information 602 is fixed. That is, the port number indicated by the connection information is the port number of the execution calculation unit that executes the corresponding calculation information. However, for example, it is possible to select an input port for inputting intermediate data and an output port for output in the arithmetic unit 100, or to input / output intermediate data by rewriting a certain area in the arithmetic information 602. By changing the port number for inputting / outputting intermediate data based on the connection information, the control unit 3 increases the degree of freedom in selecting computation information to be executed at each stage, and execution calculation The number of lines 5 set between part 1 can be reduced. In this case, the connection information defines the connection relationship of the logical port numbers between the calculation information, and the control unit 3 determines the logical port number based on the connection information and the calculation information to be executed. Control information for each execution calculation unit 1 so that the intermediate data is input / output from the corresponding input port and output port corresponding to the physical port number of the execution calculation unit 1 that actually inputs / outputs intermediate data. Is output. [0053] In the above description, it has been described that the calculation information power that does not require the input of intermediate data from other calculation information 602 is also executed. However, depending on the processing content, there may be a situation where a loop is required in whole or in part. Here, a loop is an execution calculation when the execution calculation unit 1 is a node and the input / output relationship of intermediate data is represented by an arrow from the execution calculation unit 1 that outputs the intermediate data to the execution calculation unit 1 that is input. It follows that there is a route that goes back in the direction of the arrow from part 1 and returns to the same execution calculation part 1.

[0054] If there is a loop, the executable program 6 includes information specifying one or more pieces of calculation information to be executed first, and the control unit 3 determines the execution order of the calculation information based on the information. Can be dealt with. After the calculation information to be executed first, the calculation information of the intermediate data output destination of the executed calculation information is executed in order.

[0055] Finally, a compiler apparatus according to the present invention will be described. FIG. 15 is a block diagram of a conoiler device according to the present invention. According to FIG. 15, the compiler apparatus has a syntax analysis unit 81, an optimization unit 82, and a code generation unit 83. The compiler apparatus has information on the type of the target execution calculation unit 1, that is, the type of hardware constituting the calculation unit 100 such as the RISC core, the VLIW core, or a predetermined number of arithmetic units arranged in a matrix. Then, with the source program 7 as an input, an executable program 6 that is executed by a processor equipped with one or more target execution calculation units 1 is output.

[0056] The syntax analysis unit 81 performs lexical analysis and syntax analysis of the source program 7, and the optimization unit 82 performs semantic analysis and performs optimization based on the type of the target execution calculation unit 1. Among them, the compiler device is required for the number of execution calculation units 1, the processing contents to be executed by each execution calculation unit 1, and the connection relation for input / output of intermediate data between each execution calculation unit 1. Determine. Finally, the code generation unit 83 generates code as processing information for the processing executed by each execution calculation unit 1, and establishes a connection relation for input / output of intermediate data between the execution calculation units 1. The connection information described as the connection relation of the computation information executed in 1 is generated, and the executable program 6 is output.

[0057] When the connection relationship for inputting / outputting intermediate data between the execution calculation units 1 is in a loop state, the optimization unit 82 selects one or more pieces of calculation information to be executed first. Decide and The mode generation unit 83 outputs an executable program including information for specifying one or more pieces of calculation information to be executed first.

The compiler apparatus according to the present invention can also be realized by a program that causes a computer to execute the above functions.

Claims

The scope of the claims

[1] It has one or more execution calculation means that have one or more ports for input and output, each of which is between multiple pieces of calculation information that defines the processing contents of one execution calculation means and the calculation information An executable program including connection information that defines the input / output relationship of intermediate data is divided into one or more stages and executed.

Intermediate data storage means;

For each execution calculation means, there are intermediate data storage means to which each port can be connected and control means for holding connection information, which is information about Z or other execution calculation means, and

The control means determines calculation information to be executed in each stage based on the number of execution calculation means, connection information, and connection information in each stage.

Execution calculation means for executing calculation information is characterized in that intermediate data input / output to / from calculation information that is not executed at the stage is input / output to / from intermediate data storage means. Processor.

[2] Execution calculation means is provided corresponding to each port, and from the connected intermediate data storage means and Z or other execution calculation means, one intermediate data storage means or other execution calculation means is provided. Selecting means for selecting and connecting to the corresponding port;

The control means outputs control information based on the operation information and connection information to be executed at each stage.

The selection means selects an intermediate data storage means or other execution calculation means according to the control information,

The processor according to claim 1, wherein:

[3] Execution calculation means can select the port to input / output intermediate data,

In each stage, the control means selects a port for inputting / outputting intermediate data based on calculation information and connection information to be executed,

The processor according to claim 1, wherein:

[4] A compiler device that outputs an executable program for a processor having one or more predetermined execution calculation units, An optimization method that analyzes the source program and determines the number of execution calculation units required, the processing contents of each execution calculation unit, and the connection relationship for input / output of intermediate data between each execution calculation unit When,

The operation information for each execution calculation unit that encodes the processing contents in each execution calculation unit and the input / output relationship of the intermediate data between each execution calculation unit is input in the calculation information that is executed by the execution calculation unit. Code generation means for generating an executable program including connection information described as output relations;

A compiler apparatus comprising:

A program that causes a computer to function as a compiler device that outputs an executable program for a processor having one or more predetermined execution calculation units,

On the computer,

Analyzing the source program, determining the number of execution calculation units required, the contents of processing in each execution calculation unit, and the connection relationship for input / output of intermediate data between each execution calculation unit,

The operation information for each execution calculation unit that encodes the processing contents in each execution calculation unit and the input / output relationship of the intermediate data between each execution calculation unit is input in the calculation information that is executed by the execution calculation unit. A step for generating an executable program including connection information described as output relations;

A program characterized by having executed.