WO2007031778A1 - A method of etching a feature in a silicone substrate - Google Patents

A method of etching a feature in a silicone substrate Download PDF

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Publication number
WO2007031778A1
WO2007031778A1 PCT/GB2006/003443 GB2006003443W WO2007031778A1 WO 2007031778 A1 WO2007031778 A1 WO 2007031778A1 GB 2006003443 W GB2006003443 W GB 2006003443W WO 2007031778 A1 WO2007031778 A1 WO 2007031778A1
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WO
WIPO (PCT)
Prior art keywords
etch
deposition
chamber
gas
mask
Prior art date
Application number
PCT/GB2006/003443
Other languages
French (fr)
Inventor
Yipping Song
Original Assignee
Aviza Technology Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0518896A external-priority patent/GB0518896D0/en
Application filed by Aviza Technology Limited filed Critical Aviza Technology Limited
Publication of WO2007031778A1 publication Critical patent/WO2007031778A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process

Definitions

  • the invention relates to an improved method of anisotropically etching structures, and in particular of silicon through a mask.
  • Anisotropic etching is a general requirement in the formation of electronic, photonic, optical and MEMS devices. At its most general, anisotropy is achieved by a polymer, deposited on the substrate surface, protecting side walls of features defined by the mask better than the base of the features that are directly facing a source of bombardment- typically ions but may also be photons and other forms of electromagnetic radiation. As the etch front progresses further polymer is deposited either during the etching step or as part of a discrete deposition step interleaved with etching steps. Typically this polymer is a by-product of organic mask breakdown though it is known to add polymerising etch gasses such as CHF 3 particularly for etches requiring heavy ion bombardment such as the reactive ion etching of silicon dioxide.
  • etch gasses such as CHF 3 particularly for etches requiring heavy ion bombardment such as the reactive ion etching of silicon dioxide.
  • anisotropic etch depth is at the cost of mask destruction and there is a practical limit to how deep a structure can be etched without mask
  • Deep silicon etching presents another problem however.
  • Relatively shallow structures as might be found in typical micro electronics devipes, e.g. with a depth of about 1 micron may be etched conventionally, however deeper structures require a polymer deposition.
  • Using the polymerizing etch approach, as used for silicon dioxide, is not very successful because the polymer preferentially deposits onto the silicon (to be etched) rather than the mask, and the etch selectively to the mask is therefore poor.
  • Various attempts have been made to solve the problem of deep silicon etching and an alternative concept was introduced by Hitachi in US 4,795,529, US 4,985,114 and Bosch in US 5,501 ,893 and related filings.
  • Bosch process has thus far uniquely enabled the commercial etching of deep silicon structures to depths of e.g. 150 microns, which is far in excess of the micron range depths typical of microelectronics.
  • silicon structures are defined by an organic or inorganic mask, typically photoresist, silicon dioxide, or metal.
  • a single step polymerizing (or 'dirty') etch process does not deposit enough polymer to protect the mask and selectivity of etching to the mask erosion is insufficient to achieve deep etches- say of the order of 10s of microns.
  • a passivation component such as (atomic) O, N, C, CF x , CH x may be added to the etch gas or "equally, and for the same purpose, it is desirable to reduce the chemical reactivity of the etched (sic) gas". Further it is suggested that the etch gas may be replaced with "one of lower reactive species liberating gas such as SF ⁇ being replaced by CF x ,” though no process examples are offered.
  • the '503 patent discloses partially mixing the etching and deposition steps e.g. by smooth transitions between the etch and deposition stages. This is achieved by varying the flow of etch and deposition gasses sinusoidally over time, preferably 90 degrees out of phase, such that the etch and deposition steps overlap to some degree.
  • a gas capable of polymer deposition and used in the deposition step of the cyclic etch process is used throughout predominately all of the etch step(s) of a cyclic etching process consisting of sequential deposition and etch steps repeated 'n' times.
  • the process therefore is most preferably one whereby a polymer depositing gas is flowed continuously for at least a substantial part of the etch depth and only the etch gas is cycled on and off.
  • etchant radical density created by the source power and ion bombardment energy level provided- by a 'bias' power is adjusted so that the desirable etch surface is kept free from polymer deposition while polymers are allowed to continue deposition on areas such as sidewalls during etching.
  • Additional gas such as O2 and N2 may be added to help keep the desirable etch surface free from polymer deposition.
  • the etching step of the invention, with polymerizing gas added may be thought of as an anisotropic etch step whilst the cyclic deposition step preferentially pastes additional polymer upon the mask thereby aiding its survival throughout the deep etch.
  • the process chamber is plasma cleaned between each substrate processing (to remove excessive polymer deposits) and therefore some kind of chamber conditioning is needed before starting the substrate etching deposition/etching cycle.
  • an initial deposition step is used before the cyclic etching loop. This is preferably and surprisingly carried out with the substrate within the chamber. Due to the high aspect ratio of a typical mask for a deep etch process, the deposition is mostly upon the chamber wall and top of mask, and not the desirable etch surface which receives less flux from deposition precursors.
  • the invention includes a method of etching a feature in a silicon substrate located in a chamber and having a patterned mask thereon including performing a cyclic etch process through the mask to form the feature, the process including successive etch and deposition steps using etch and deposition gases flowed into the chamber characterised in that the deposition gas is flowed into the chamber continuously throughout a plurality of successive etch and deposition cycles.
  • the rate of flow of the deposition gas is higher during the deposition parts between the etch parts of the cycles.
  • the rate of flow in the etch parts may be between 5 and 7 times less than the rate of flow during the deposition parts.
  • the deposition gas and/or deposition conditions may be selected such that the deposition takes place preferentially on the mask at least during the deposition stage.
  • the etch is principally chemical.
  • the deposition gas may be flowed at the start of the method to condition the chamber and the substrate may be located in the chamber during the conditioning. It is also preferred that a plasma is present in the chamber during the process and the deposition gas may be flowed substantially throughout the method and in particular when there is a plasma present.
  • the mask may be silicon dioxide.
  • the etch gas may be SF 6 whilst the deposition gas may be C 4 Fs.
  • the substrate is preferably placed on a platen, which may be biased for at least the cyclic etch process, in which place the bias may be higher during the etch part of the cycle.
  • the chamber pressure may be higher during the deposition part of the process than during the etch part, in which case nitrogen may also be flowed into the chamber during the periods when a higher chamber pressure is required.
  • FIGS. 1 and 2 are prior art 'Bosch' process and figs 3 and 4 show the results from this invention using the same design and construction of etch masks. As can be seen scallops 2 are greatly reduced or entirely removed by this process. The top etch of the silicon is along a plane 3, these images being taken looking down at a cleaved substrate. In figs 1 and 3 can be seen even trench and spacing and in figs 2 and 4 can be seen trenches placed close together. These test structures are relatively small.
  • the mask (removed) was of the order of 1 to 2 microns thick and the desired trench widths were of the order of 0.1 to 0.15 microns wide.
  • the etched trenches are about 2 microns deep in these figures but could, for example, be up to 7 ⁇ m.
  • the deposition gas flow is maintained throughout the cyclic etching process, though flow rate is changed during etching and polymerization steps.
  • the deposition gas is on continuously whilst a plasma is present in the chamber including plasma initiation (strike) and initial chamber conditioning ('seasoning').
  • plasma initiation plasma initiation
  • initial chamber conditioning 'seasoning'
  • Other additional gasses could however be used for keeping etch surface free from polymer deposition and chamber conditioning may be carried out with a different gas or gas mix- though this would be at the expense of additional process and equipment complexity (and cost).
  • the etchant gas is switched on only for the etching steps in the cyclic etching (consisting of both etching and deposition steps). Where zero flow is shown for the etchant during net deposition steps, it is within the scope of this invention that very low flow rates may be included as long as they are not detrimental to the process. Such a low flow may for example allow a mass flow controller to be cycled on and nominally off (or to a low value) thereby obviating the need for a shut off valve.
  • Table 1 Step Duration Cycles Pressure Substrate Plasma SF6 C4F8 bias power power Etch Deposition

Abstract

This invention relates to a method of etching a feature in a silicon substrate located in a chamber and having a patterned mask thereon including performing a cyclic etch process through the mask to form the feature, the process including successive etch and deposition steps using etch and deposition gases flowed into the chamber characterised in that the deposition gas is flowed into the chamber continuously throughout a plurality of successive etch and deposition cycles.

Description

A METHOD OF ETCHING A FEATURE IN A SILICON SUBSTRATE
Field of invention
The invention relates to an improved method of anisotropically etching structures, and in particular of silicon through a mask.
Related Art
Anisotropic etching is a general requirement in the formation of electronic, photonic, optical and MEMS devices. At its most general, anisotropy is achieved by a polymer, deposited on the substrate surface, protecting side walls of features defined by the mask better than the base of the features that are directly facing a source of bombardment- typically ions but may also be photons and other forms of electromagnetic radiation. As the etch front progresses further polymer is deposited either during the etching step or as part of a discrete deposition step interleaved with etching steps. Typically this polymer is a by-product of organic mask breakdown though it is known to add polymerising etch gasses such as CHF3 particularly for etches requiring heavy ion bombardment such as the reactive ion etching of silicon dioxide.
Clearly therefore anisotropic etch depth is at the cost of mask destruction and there is a practical limit to how deep a structure can be etched without mask
'pull back' (thereby loosing mask definition) or complete loss of the mask.
Deep silicon etching presents another problem however. Relatively shallow structures, as might be found in typical micro electronics devipes, e.g. with a depth of about 1 micron may be etched conventionally, however deeper structures require a polymer deposition. Using the polymerizing etch approach, as used for silicon dioxide, is not very successful because the polymer preferentially deposits onto the silicon (to be etched) rather than the mask, and the etch selectively to the mask is therefore poor. Various attempts have been made to solve the problem of deep silicon etching and an alternative concept was introduced by Hitachi in US 4,795,529, US 4,985,114 and Bosch in US 5,501 ,893 and related filings. This concept alternated a polymer deposition step with an etching step in a cyclic process e.g. deposition-etch-deposition-etch and on until the required etch depth is achieved. Whereas Hitachi in their '529 patent chose a single gas mix that could either deposit or etch depending on process conditions, in their later '114 patent they switch gasses as does Bosch.
The so-called Bosch process has thus far uniquely enabled the commercial etching of deep silicon structures to depths of e.g. 150 microns, which is far in excess of the micron range depths typical of microelectronics.
Such deep etches have enabled the formation of micro mechanical structures and have become a commonplace.
These silicon structures are defined by an organic or inorganic mask, typically photoresist, silicon dioxide, or metal. A single step polymerizing (or 'dirty') etch process does not deposit enough polymer to protect the mask and selectivity of etching to the mask erosion is insufficient to achieve deep etches- say of the order of 10s of microns.
In contrast the Bosch process suffers from some loss of Critical Dimension (CD, etched structures may be wider than that defined by the mask) and scalloping, as the etch front is at the micro level quite isotropic. Etch depth at reasonable speed and selectivity to the mask is achieved and in MEMS structures the structures etched are quite wide, such as about 1 micron or greater in width, so some CD loss and scalloping is not critical. There has been considerable research since 1992 (when the Bosch process was developed) to improve upon this basic process concept and various improvements have been proposed. This including the ramping of process parameters and the inclusion of 2 different etch processes- such that the sequence is dep-etch-etch-dep. These improvements have principally sought to address one or more of the following three criteria, which are to some degree mutually exclusive: Etch selectivity to mask: Great etch depths require the etching of the mask to proceed very slowly.
Speed: Great etch depths imply long etch times. Clearly if the etch depth for a MEMS structure is 150 times greater than for a microelectronics device then, all things being equal, the etch time will be 150 times as long. In fact faster etching speeds have been obtained, but still the etching times are far in excess of microelectronics devices and makes MEMS device production far more expensive. Smoothness of side walls: Typically 'Bosch Process' etching yields side walls with 'scallops' or 'notching'.
A discussion of these trade offs and a proposed solution may be found in US 6,720,268. There is also the case of silicon etches that are sub micron in width and of intermediate depth e.g. greater than 1 micron, but less than 10 microns. Here the Bosch process, with its scalloping and CD loss may not give 'good' results, and neither will conventional organic mask or polymerizing etches, where 'good' means an acceptable mix of etch rate, selectivity to mask, CD loss and etch speed.
In Surface Technology Systems' 6,051 ,503 it is suggested that a passivation component such as (atomic) O, N, C, CFx, CHx may be added to the etch gas or "equally, and for the same purpose, it is desirable to reduce the chemical reactivity of the etched (sic) gas". Further it is suggested that the etch gas may be replaced with "one of lower reactive species liberating gas such as SFβ being replaced by CFx," though no process examples are offered.
Also the '503 patent discloses partially mixing the etching and deposition steps e.g. by smooth transitions between the etch and deposition stages. This is achieved by varying the flow of etch and deposition gasses sinusoidally over time, preferably 90 degrees out of phase, such that the etch and deposition steps overlap to some degree.
Thus '503 teaches a reduction in chemical reactivity to limit "roughness" and partial overlap of deposition and etch steps to smooth transitions. Summary of invention
From one further aspect in the method of this invention, a gas capable of polymer deposition and used in the deposition step of the cyclic etch process is used throughout predominately all of the etch step(s) of a cyclic etching process consisting of sequential deposition and etch steps repeated 'n' times. The process therefore is most preferably one whereby a polymer depositing gas is flowed continuously for at least a substantial part of the etch depth and only the etch gas is cycled on and off. During the etch cycle, etchant radical density created by the source power and ion bombardment energy level provided- by a 'bias' power is adjusted so that the desirable etch surface is kept free from polymer deposition while polymers are allowed to continue deposition on areas such as sidewalls during etching. Additional gas such as O2 and N2 may be added to help keep the desirable etch surface free from polymer deposition. By way of explanation, but without limiting the generality of the invention the process may be understood as this. The etching step of the invention, with polymerizing gas added, may be thought of as an anisotropic etch step whilst the cyclic deposition step preferentially pastes additional polymer upon the mask thereby aiding its survival throughout the deep etch. This may be contrasted with the prior art Bosch type process where the visible scalloping clearly demonstrates that each etch step within the cycle is essentially isotropic and that this etching must be halted before too much CD loss is suffered. A deposition step is then run to recoat the side walls of the etched structure. This analysis of the 'Bosch' process can be found in US 6,720,268 which shares the same inventors as the 'Bosch' process.
Preferably the process chamber is plasma cleaned between each substrate processing (to remove excessive polymer deposits) and therefore some kind of chamber conditioning is needed before starting the substrate etching deposition/etching cycle. To do so an initial deposition step is used before the cyclic etching loop. This is preferably and surprisingly carried out with the substrate within the chamber. Due to the high aspect ratio of a typical mask for a deep etch process, the deposition is mostly upon the chamber wall and top of mask, and not the desirable etch surface which receives less flux from deposition precursors.
From another aspect the invention includes a method of etching a feature in a silicon substrate located in a chamber and having a patterned mask thereon including performing a cyclic etch process through the mask to form the feature, the process including successive etch and deposition steps using etch and deposition gases flowed into the chamber characterised in that the deposition gas is flowed into the chamber continuously throughout a plurality of successive etch and deposition cycles.
Preferably the rate of flow of the deposition gas is higher during the deposition parts between the etch parts of the cycles. For example the rate of flow in the etch parts may be between 5 and 7 times less than the rate of flow during the deposition parts. The deposition gas and/or deposition conditions may be selected such that the deposition takes place preferentially on the mask at least during the deposition stage.
Preferably the etch is principally chemical. The deposition gas may be flowed at the start of the method to condition the chamber and the substrate may be located in the chamber during the conditioning. It is also preferred that a plasma is present in the chamber during the process and the deposition gas may be flowed substantially throughout the method and in particular when there is a plasma present.
The mask may be silicon dioxide. The etch gas may be SF6 whilst the deposition gas may be C4Fs.
The substrate is preferably placed on a platen, which may be biased for at least the cyclic etch process, in which place the bias may be higher during the etch part of the cycle.
The chamber pressure may be higher during the deposition part of the process than during the etch part, in which case nitrogen may also be flowed into the chamber during the periods when a higher chamber pressure is required. Detailed description
The figures are scanning electron micrographs of trenches 1 etched in silicon. Figs 1 and 2 are prior art 'Bosch' process and figs 3 and 4 show the results from this invention using the same design and construction of etch masks. As can be seen scallops 2 are greatly reduced or entirely removed by this process. The top etch of the silicon is along a plane 3, these images being taken looking down at a cleaved substrate. In figs 1 and 3 can be seen even trench and spacing and in figs 2 and 4 can be seen trenches placed close together. These test structures are relatively small. The mask (removed) was of the order of 1 to 2 microns thick and the desired trench widths were of the order of 0.1 to 0.15 microns wide. The etched trenches are about 2 microns deep in these figures but could, for example, be up to 7μm.
The best known process is shown in table 1. Note that the deposition gas flow is maintained throughout the cyclic etching process, though flow rate is changed during etching and polymerization steps. Preferably the deposition gas is on continuously whilst a plasma is present in the chamber including plasma initiation (strike) and initial chamber conditioning ('seasoning'). Other additional gasses could however be used for keeping etch surface free from polymer deposition and chamber conditioning may be carried out with a different gas or gas mix- though this would be at the expense of additional process and equipment complexity (and cost).
The etchant gas is switched on only for the etching steps in the cyclic etching (consisting of both etching and deposition steps). Where zero flow is shown for the etchant during net deposition steps, it is within the scope of this invention that very low flow rates may be included as long as they are not detrimental to the process. Such a low flow may for example allow a mass flow controller to be cycled on and nominally off (or to a low value) thereby obviating the need for a shut off valve. Table 1 Step Duration Cycles Pressure Substrate Plasma SF6 C4F8 bias power power Etch Deposition
Seconds mT Watts Watts seem seem
Plasma strike 1 1 30 0 1500 0 330
Conditioning 5 1 70 20 2500 0 330
Cycling etching
Deposition step 4.5 n 70 20 2500 0 330
Etching step 4 n 20 50 2500 200 50

Claims

Claims
1. A method of etching a feature in a silicon substrate located in a chamber and having a patterned mask thereon including performing a cyclic etch process through the mask to form the feature, the process including successive etch and deposition steps using etch and deposition gases flowed into the chamber characterised in that the deposition gas is flowed into the chamber continuously throughout a plurality of successive etch and deposition cycles.
2. A method as claimed in claim 1 wherein the rate of flow of the deposition gas is higher between the etch parts of the cycles than it is during the deposition parts.
3. A method as claimed in claims 2 wherein the rate of flow of the deposition gas in the etch parts is between 5 and 7 times less than the rate flow during the deposition parts.
4. A method as claimed in any one of the preceding claims wherein the deposition gas and/or deposition conditions are such that deposition takes place preferentially on the mask.
5. A method as claimed in any one of the preceding claims wherein the etch is principally chemical.
6. A method as claimed in any one of the preceding claims wherein the deposition gas is flowed at the start of the method to condition the chamber.
7. A method as claimed in claim 6 wherein the substrate is located in the chamber during conditioning.
8. A method as claimed in any one the preceding claims wherein a plasma is present in the chamber.
9. A method as claimed in claim 8 wherein the deposition gas is flowed substantially through the method.
10. A method as claimed in any one of the preceding claims wherein the mask is silicon dioxide.
11. A method as claimed in any one of the preceding claims wherein the etch
gas is SF6.
12. A method as claimed in any one of the preceding claims wherein the deposition gas is C4Fa.
13. A method as claimed in any one of the preceding claims wherein the substrate is placed on a platen.
14. A method as claimed in claim 13 wherein the platen is biased for at least the cyclic etch process.
15. A method as claimed in claim 14 wherein the bias is higher during the etch part of the cycle.
16. A method as claimed in any one of the preceding claims wherein the pressure in the chamber is higher during the deposition part of the process than during the etch part.
17. A method of processing a substrate including exposing the substrate to a gas capable of polymer deposition and used in the deposition step of a cyclic etch process throughout predominately all of the etch steps of the cyclic etch process which consists of sequential deposition and etch steps repeated 'n' times.
PCT/GB2006/003443 2005-09-16 2006-09-18 A method of etching a feature in a silicone substrate WO2007031778A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US71718905P 2005-09-16 2005-09-16
US60/717,189 2005-09-16
GB0518896.6 2005-09-16
GB0518896A GB0518896D0 (en) 2005-09-16 2005-09-16 A method of etching a feature in a substrate

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150145065A1 (en) * 2013-11-25 2015-05-28 International Business Machines Corporation finFET Isolation by Selective Cyclic Etch
KR20160078477A (en) * 2013-11-06 2016-07-04 도쿄엘렉트론가부시키가이샤 Method for deep silicon etching using gas pulsing

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000026956A1 (en) * 1998-11-04 2000-05-11 Surface Technology Systems Limited A method and apparatus for etching a substrate
WO2000062328A1 (en) * 1999-04-14 2000-10-19 Surface Technology Systems Limited Method and apparatus for stabilising a plasma
EP1047122A2 (en) * 1999-04-21 2000-10-25 Alcatel Method of anisotropic etching of substrates
WO2004102642A2 (en) * 2003-05-09 2004-11-25 Unaxis Usa Inc. Envelope follower end point detection in time division multiplexed processes
US20050130436A1 (en) * 2003-03-25 2005-06-16 Sumitomo Precision Products Co., Ltd. Method for etching of a silicon substrate and etching apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000026956A1 (en) * 1998-11-04 2000-05-11 Surface Technology Systems Limited A method and apparatus for etching a substrate
WO2000062328A1 (en) * 1999-04-14 2000-10-19 Surface Technology Systems Limited Method and apparatus for stabilising a plasma
EP1047122A2 (en) * 1999-04-21 2000-10-25 Alcatel Method of anisotropic etching of substrates
US20050130436A1 (en) * 2003-03-25 2005-06-16 Sumitomo Precision Products Co., Ltd. Method for etching of a silicon substrate and etching apparatus
WO2004102642A2 (en) * 2003-05-09 2004-11-25 Unaxis Usa Inc. Envelope follower end point detection in time division multiplexed processes

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160078477A (en) * 2013-11-06 2016-07-04 도쿄엘렉트론가부시키가이샤 Method for deep silicon etching using gas pulsing
KR101880831B1 (en) * 2013-11-06 2018-07-20 도쿄엘렉트론가부시키가이샤 Method for deep silicon etching using gas pulsing
US20150145065A1 (en) * 2013-11-25 2015-05-28 International Business Machines Corporation finFET Isolation by Selective Cyclic Etch
US9209178B2 (en) * 2013-11-25 2015-12-08 International Business Machines Corporation finFET isolation by selective cyclic etch

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