WO2007022375A3 - Multiple independent coherence planes for maintaining coherency - Google Patents
Multiple independent coherence planes for maintaining coherency Download PDFInfo
- Publication number
- WO2007022375A3 WO2007022375A3 PCT/US2006/032174 US2006032174W WO2007022375A3 WO 2007022375 A3 WO2007022375 A3 WO 2007022375A3 US 2006032174 W US2006032174 W US 2006032174W WO 2007022375 A3 WO2007022375 A3 WO 2007022375A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- coherence
- plane
- planes
- address
- independent
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
Abstract
In one embodiment, a node comprises at least one processor core and a plurality of coherence units. The processor core is configured to generate an address to access a memory location. The address maps to a first coherence plane of a plurality of coherence planes. Coherence activity is performed within each coherence plane independent of other coherence planes, and a mapping of the address space to the coherence planes is independent of a physical location of the addressed memory in a distributed system memory. Each coherence unit corresponds to a respective coherence plane and is configured to manage coherency for the node and for the respective coherence plane. The coherence units operate independent of each other, and a first coherence unit corresponding to the first coherence plane is coupled to receive the address if external coherency activity is needed to complete the access to the memory location.
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/205,652 | 2005-08-17 | ||
US11/205,690 | 2005-08-17 | ||
US11/205,690 US7398360B2 (en) | 2005-08-17 | 2005-08-17 | Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors |
US11/205,706 US7529894B2 (en) | 2005-08-17 | 2005-08-17 | Use of FBDIMM channel as memory channel and coherence channel |
US11/205,652 US7353340B2 (en) | 2005-08-17 | 2005-08-17 | Multiple independent coherence planes for maintaining coherency |
US11/205,706 | 2005-08-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007022375A2 WO2007022375A2 (en) | 2007-02-22 |
WO2007022375A3 true WO2007022375A3 (en) | 2007-05-10 |
Family
ID=37499549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2006/032174 WO2007022375A2 (en) | 2005-08-17 | 2006-08-17 | Multiple independent coherence planes for maintaining coherency |
Country Status (1)
Country | Link |
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WO (1) | WO2007022375A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103716882B (en) * | 2012-10-08 | 2017-03-15 | 成都鼎桥通信技术有限公司 | The method of control semi-persistent scheduling implicit expression release function, base station and user equipment |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010010068A1 (en) * | 1998-05-29 | 2001-07-26 | International Business Machines Corporation | State-based allocation and replacement for improved hit ratio in directory caches |
US20050138298A1 (en) * | 2003-12-18 | 2005-06-23 | Downer Wayne A. | Secondary path for coherency controller to interconnection network(s) |
-
2006
- 2006-08-17 WO PCT/US2006/032174 patent/WO2007022375A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010010068A1 (en) * | 1998-05-29 | 2001-07-26 | International Business Machines Corporation | State-based allocation and replacement for improved hit ratio in directory caches |
US20050138298A1 (en) * | 2003-12-18 | 2005-06-23 | Downer Wayne A. | Secondary path for coherency controller to interconnection network(s) |
Also Published As
Publication number | Publication date |
---|---|
WO2007022375A2 (en) | 2007-02-22 |
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