WO2007020712A1

WO2007020712A1 - Signal output circuit

Info

Publication number: WO2007020712A1
Application number: PCT/JP2005/015298
Authority: WO
Inventors: Yoshito Tanaka
Original assignee: Test Research Laboratories Inc.
Priority date: 2005-08-17
Filing date: 2005-08-17
Publication date: 2007-02-22

Abstract

A plurality of switch circuits (5-1 to 5-4, 6-1 to 6-4) are connected in parallel to a plurality of voltage-dividing capacitors (3-1 to 3-4, 4-1 to 4-4) arranged at the first stage of sample hold circuit units (1-1 to 1-4). By turning on the switch circuits ( 5-1 to 5-4, 6-1 to 6-4) at a predetermined timing, it is possible to reset the voltage-dividing capacitors (3-1 to 3-4, 4-1 to 4-4) at a predetermined timing and again accumulate charge in accordance with the signal voltage so as to correctly perform voltage division operation even if electric charge leaks from the voltage-dividing capacitors (3-1 to 3-4, 4-1 to 4-4) little by little during voltage division operation of the signal voltage.

Description

Description Signal output circuit Technical field

The present invention relates to a signal output circuit, and is particularly suitable for use in a circuit that sequentially outputs an input signal while being sampled and held by a sample hold circuit. Background art

For example, two methods can be used to convert n analog signals to digital signals. The first is a method of providing n AZD converters and simultaneously converting n analog D signals to digital signals by n A / D converters. The second is a multiplexer and 1 In this method, n analog signals are multiplexed and n analog signals are multiplexed and input one by one to the A / D converter to convert them into agital signals.

In the case of the former method, it is possible to speed up the A-to-D conversion process.

Requires a D converter. For this reason, there is a problem that when the circuit scale of the AZD conversion device is large, there is a problem that a lot of manufacturing costs are required. When the latter method is adopted, there is a problem in terms of circuit scale and manufacturing costs. However, it is difficult to speed up the A / D conversion process.

That is, an AZD conversion device employing the latter method is generally configured by connecting a multiplexer, a sample hold circuit, and an AZD conversion circuit in this order. N analog signals are input to the multiplexer, and n analog signals are multiplexed by the multiplexer and output one by one. N items output one by one from the multiplexer The analog input signal is sampled by the sample-and-hold circuit and then sequentially sampled.

-Loaded and AZ D converted by the A Z D conversion circuit. Because of this configuration, the A / D conversion speed is dominated by the sampling processing and holding processing time in the sample hold circuit.Therefore, the processing of the A / D conversion circuit is simply accelerated. A /

D conversion processing cannot be accelerated. Also, the sampling interval is long

Therefore, the time resolution of A Z D conversion cannot be increased.

Conventionally, in view of such problems, there has been proposed an A / D conversion device that increases the AZ D conversion processing speed without causing an increase in cost (see, for example, Patent Document 1).

Patent Document 1: Japanese Patent Application Laid-Open No. 1 1-3 1 2 3 1 3

In the A / D converter described in Patent Document 1, a plurality of sample hold circuits are provided in front of a multiplexer, and these sampling and home

-By alternating the timing of the rud- ing, the sampling time is equivalently lost. As a result, the apparent appearance of the A Z D converter

The AD conversion process is speeded up.

However, in the technique described in Patent Document 1, a plurality of analog signal is held while shifting the timing in a plurality of sample hold circuits, so that a plurality of analog signals cannot be held at the same time. . In particular, if the number of input analog signals is large, it takes a long time to hold all analog signals in the sample-and-hold circuit.

Also, for example, in semiconductor test equipment, it may be required to accurately observe the waveform of the analog signal output from the semiconductor equipment, but the A / D conversion resolution is poor (sampling time interval). If it is long), an accurate waveform cannot be measured. In contrast, multiple sample-hold circuits are connected in parallel to the analog output section of the analog port circuit. ό

However, by sampling the analog signal using multiple timing signals that are sequentially delayed at regular time intervals, the apparent resolution can be improved and the output waveform can be observed. This technology has also been proposed (see, for example, Patent Document 2).

Patent Document 2: Japanese Patent Laid-Open No. 2 0 0 1 — 1 4 7 2 5 6

By the way, there is an upper limit to the voltage value of the analog signal that can be held by the sample hold circuit, and the voltage value of the analog signal output from the semiconductor device exceeds the allowable value of the sample hold circuit. The output voltage waveform cannot be measured. To solve this inconvenience, a possible solution is to divide and reduce the voltage value of the analog signal and hold the divided voltage in the sample hold circuit. For example, a D converter has been proposed in which the voltage of an analog signal is divided by a capacitor array and the divided voltage is held by a sample hall circuit and output (for example,

And Patent Document 3).

Patent Document 3: Japanese Patent Laid-Open No. 9 1 2 7 5 3 4 5

However, when a capacitor is used for voltage division, the chained charge gradually leaks over time, and the balance of the amount of chain is lost. When the balance of the charge amount is lost, the divided voltage is distorted, and the correct voltage value of the analog signal cannot be output, but the output waveform cannot be measured accurately. A resistor may be used instead of a capacitor, but a voltage dividing resistor may not be used depending on the application of the A / D converter. For example, when an AZD converter is applied to a liquid crystal display device, the liquid crystal display panel is a capacitive load, and accordingly, it is necessary to use a capacitor for voltage division. In that case, the above-mentioned problem will occur. Disclosure of the invention

The present invention has been made to solve such a problem, and in a signal output circuit having a voltage dividing capacitor in the previous stage of a sample hold circuit, a plurality of input analog signals are sampled. The purpose is to ensure the simultaneous holding ability when holding in the hold circuit.

Another object of the present invention is to suppress a ^ 3 voltage drift caused by a charge charge from a capacitor provided for voltage division and to output a signal voltage having a correct value. To do.

In the signal output circuit of the present invention,

(N> 2 integer) sample hold circuits are connected in parallel to form a sample hold and circuit section, and this sample hold circuit section is equipped with multiple sample hold circuit sections N Sample-and-hold circuits

Each one is operated sequentially at a certain delay time, and the i-th sample hold circuit provided in each of the multiple sample hold circuit sections is controlled to operate simultaneously. In another aspect of the signal output circuit according to the present invention, a plurality of switch circuits connected to the ground are connected to a plurality of voltage dividing capacitors.

い Make sure that a number of switch circuits are turned on at a given timing.

According to the present invention configured as described above, a plurality of input signals can be simultaneously held by a plurality of sample hold circuit units, and the simultaneously held signals can be output to a subsequent multiplexer. Therefore, the simultaneous retention of multiple signals can be ensured. In addition, the analog signal generated from each sample hole circuit section is sampled sequentially at a fixed delay time, and the apparent resolution is improved by shortening the delay time < It becomes possible to do. Therefore, for example, when measuring the waveform of multiple analog signals, high resolution is achieved while ensuring the simultaneous retention of analog signals. It is possible to perform detailed waveform measurements.

According to another feature of the present invention, while the plurality of switch circuits connected to the plurality of voltage dividing capacitors are off, the load corresponding to the signal voltage is stored and shelled in the voltage dividing capacitor. However, when a plurality of switch circuits are turned on at a predetermined timing, the charge that has been loaded on the voltage dividing capacitor is changed to the data via the plurality of switch circuits. The system is reset and the capacitor for pressure division is reset. As a result, even if the voltage leaks gradually from the voltage dividing capacitor during the voltage dividing operation of the signal voltage and a voltage droop occurs, it is reset at a predetermined timing, and the signal again Charges corresponding to ¾ pressure are accumulated and partial pressure ft operation is performed. Therefore, it is possible to suppress the B¾ shift caused by the U-curing of charges from the voltage dividing capacitor, and to output a correct divided voltage. Brief Description of Drawings

FIG. 1 is a block diagram showing a configuration example of the signal output circuit according to the first embodiment.

FIG. 2 is a diagram showing an example of the internal configuration of the sample-and-hold circuit unit shown in FIG.

FIG. 3 is a diagram showing a measurement example when the waveform of an analog signal is measured by applying the signal output circuit according to the first embodiment.

FIG. 4 is a block diagram showing a configuration example of the signal output circuit according to the second embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

(First embodiment)

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Figure 1 shows the first 1 is a block diagram illustrating a configuration example of a signal output circuit according to an embodiment of 1. FIG. As shown in FIG. 1, the signal output circuit of the first embodiment is configured to include sample hole circuit units 1_, _1-4 and multiplexers 2-, 2. Multiplexers 2 2 _ ₃ are connected in a tree structure. Of these, the first and second multiplexers 2 2 _ ₂ belong to the first layer, and the third multiplexor 2 _ ₃ belongs to the second layer, one layer above it.

These plurality of multiplexers 2, 2 _ _3, and outputs them one by one sequentially switching a plurality of signals are entered in parallel. That is, the first multiplexer 2 includes the first and second sample and hold circuit sections 1

1 - 2 second multiplexer 2 _ ₂ to force out a plurality of signals, one switched sequentially inputted in parallel from the third and fourth sample-hold 'circuit sounds 15 1- _3, Switches multiple signals input in parallel from 1-4 and outputs them one by one. Third multiplexer 2 _{- 3,} the first multiplexer 2, and a second multiplexer 2 - outputting a plurality of signals inputted from ₂ sequentially switched from one output terminal OUT by one.

The front of the sample-and-hold circuit unit 1 1 _4, a first voltage dividing Capacity evening 3 -, _3-4 and the second voltage dividing Capacity evening 4 4 _ ₄ is provided. The first voltage dividing capacitors 3—, _3-4 and the second voltage dividing capacitor 4 4 — ₄ are connected in series between the signal voltage input line and the ground. Then, the divided voltage appearing at the connection node between the first voltage dividing capacitors 3-, 3 — ₄ and the second voltage dividing capacitors 4-, 4 _ ₄ is the sample-hold circuit section 1 „, 1— ₄ is entered.

In other words, the first voltage-dividing capacitor 31 and the second voltage-dividing capacitor 4 are connected between the signal voltage input terminal In 1 and the ground in the first stage of the first sample-hold circuit section 1. Connected in series. And first Capacitor for partial pressure 3—, and 4th for partial pressure Capacitor

The divided voltage that appears at the contact node with is input to the first sample-hold circuit 1-,.

The second of the preceding sample-hold circuit part 1, the first voltage dividing capacitor _3-2 and the second voltage dividing capacitor 4 _2, and input terminals I n 2 and ground signal voltage Are connected in series. Then, I like the first divided voltage Ru appear in connection Roh one and dividing capacitor 3 _ ₂ and the second voltage dividing capacitor _4-2 is input to the second sample-and-hold circuit unit 1 _ ₂ It is.

Further, in the front of the third sample-and-hold circuit unit 1 _ _3, first dividing capacitor 3 = a eg.

— ₃ and second voltage dividing capacitor 4— ₃ /

But, IB ^ Ό o and are connected in series between the input terminals I n 3 and ground of ¾ pressure, first dividing Capacity evening 3 - ₃ and the second voltage dividing Capacity evening _4-3 connection Bruno and - the divided voltage Ru appear are such One as input to the third sample-and-hold circuit unit 1 _ _3.

The first sample-hold circuit section _1-4 is preceded by a first voltage divider.

/ = Mouth srs,

Capacity evening _3-4 and the second voltage dividing capacitor 4 ₄ are connected in series between the input terminals I n 1 and ground for 15 ¾ pressure. Then, the divided voltage Ru appear in connection Roh one first dividing Capacity evening 3 _ ₄ and the second voltage dividing Capacity evening _4-4 is input to the fourth sample-hold circuit part 1- ₄ It ’s good.

The first to fourth sample and hold circuit section 1 to 1 - _4, sampling the divided voltage of the input Ana port grayed signals and Holdings Ngushi, first and second multiplexers 2 - There 2- ₂ Output to.

In a first embodiment, the first and second voltage dividing capacitors 3 and 3 _4, 4-4 - for each of _4, the first sweep rate Tutsi circuit 5 _, ~ 5 _{- 4} and the The second sweep rate latch circuit 6 to 6 ₄ are connected in parallel.

In other words, the first and second switch circuits 5 and 6 are connected in parallel to the first and second voltage dividing capacitors 3 and 4 connected to the front stage of the first sample hold circuit section 1, respectively. Connected. As a result, the first and second switch circuits 56 are connected in series between the signal voltage input terminal In 1 and the ground.

The first contact and the second voltage dividing capacitor 3 connected to the front stage of the second sample-hold circuit unit 1 _ ₂ - _2, 4 for each _-2 first and second sweep rate Tsu H circuit 5 _-2 and 6 _ ₂ are connected in parallel. Thus, the first contact and the second sweep rate latch circuit _5-2, _6-2 is a form of being connected in series between the input terminal I n 2 and Dara down de signal voltage.

The third sample hold for each of the circuit portions 1 _ ₃ of the first contact and the second voltage dividing Capacity evening 3 ₃ connected to the front stage, 4 _-3, the first and second sweep rate latch circuit 5 - ₃ connects the 6 ₃ in parallel. Thus, the first contact and the second sweep rate latch circuit _5-3, 6 _ ₃ is a form of being connected in series between the input terminal I n 3 and Dara down de signal voltage.

The first contact and the second voltage dividing capacitor 3 is connected in front of the fourth sample-hold circuit unit 1 ₄ - ₄ for 4 _ _4, respectively, the first and second sweep rate Tsu latch circuit 5 - ₄ connects the 6 ₄ in parallel. Thus, the first contact and second switch circuits _5-4, 6 _4, a form of being connected in series between the input terminal I n 4 and Gras down de signal voltage.

Furthermore, in the first embodiment, the first and second voltage dividing Capacity evening 3-3- _4, 4, ~ 4_ ₄ and the first and second sweep rate latch circuit 5 _ i to 5-4, 6 - for parallel circuit composed of the ~ 6-4 is provided with a third switch circuit 7 ~ _7-4 which are connected in series on the input line of the signal voltage.

That is, the first and second partial pressure capacitors 3—, 4—, and the first and second A third switch circuit 7 is connected between the parallel circuit composed of the second switch circuits 5 and 6 and the signal voltage input terminal In 1. The first and second voltage dividing capacitors _3-2, 4 - ₂ and the parallel circuit composed of a first and second Sui tree latch circuit 5 _ _2, 6- _2, the input terminal of the signal voltage connecting the third sweep rate latch circuit 7 ₂ between the I n 2. The first and second voltage dividing Capacity evening 3 - a parallel circuit composed of the _3, 4 _ ₃ and the first and second sweep rate latch circuit 5 _ _3, 6 _ _3, the input signal voltage connecting the third sweep rate latch circuit 7 _ ₃ between the terminals I n 3. The first and second voltage dividing capacitor 3 - _4, 4 ₄ and the first and second sweep rate latch circuit 5 _-4, and a parallel circuit consists of a 6 _ _4, the input terminal of the signal voltage It connects the ₄ - third Sui Tsu latch circuit 7 between the I n 4.

Control unit 8, the first sweep rate latch circuit 5-i to 5 - _4, a second sweep rate latch circuit 6 _, ~ 6 _ ₄ and the third sweep rate Tutsi circuit 7 to 7 _ ₄ ON / OFF To control the operation. That is, the normal signal output operation, the first and second sweep rate Tutsi circuit 5 _, ~ _5-4, 6-6 _ ₄ off, the third sweep rate latch circuit 7, 1-7 ^ ON And In this state, the first and second voltage dividing Capacity evening 3, 1-3 _ _4, 4 ~ 4 _ ₄ charge corresponding to the signal voltage is charged to cracking divider action rows, the divided signal voltage is input to the sample-and-hold circuit unit 1 to 1 _4. Then, a plurality of signal multiplexer 2 _ held by the sample hold circuit units 1 ~ 1 _ ₄ ~ 2 - ₃ are selected by and outputted from one output terminal OUT in order.

Control unit 8 at a predetermined timing, first and second sweep rate latch circuit 5 to 5 _ _4, 6, on the ~ 6 _4, the third sweep rate latch circuit 7 _, ~ _7-4 Switch off. This ensures that the first and second voltage dividing Capacity evening 3 to 3 _-4, 4, charges accumulated in ~ 4 _ ₄ the first and second sweep rate latch circuit 5, 1-5 — ₄ , 6-, ~ 6 ₄ are discharged to ground via the first and Second dividing capacitor 3 _ ~ 3 _ _4, 4 _, ~ _4-4 is reset. After resetting, the first and second switch circuits 5-, ~ 5 _-4 , 6-, ~ 6 _-4 are switched off again.

The control unit 8 first and second sweep rate Tutsi circuits 5, ~ 5 _4, 6, - timing for switching the 6 _ ₄ O emissions is a 1. 3 spare second dividing Capacity evening 3 to

3-4, 4-, ~ 4 '-4 Charge ^: is determined in advance within the time that the total leak amount when the U-cooking over time is expected to exceed the allowable value The evening was held. For example, the control unit 8 includes first and second switch circuits for each such evening.

0 to 5-'D-i 6 -4 can be changed to 0

And Shino Unisuru, the signal voltage of the voltage dividing operation when the first and second voltage dividing Capacity evening 3-° -4, 4 -, and U Ichiku From _4-4 little by little charge voltage de oice occur Even if it is reset at a predetermined timing, charge corresponding to the signal voltage is accumulated again and voltage division operation is performed. 3-3--

4> 4: -1 4 - 4 color electrostatic load suppresses the pressure drill oice caused by re one click, it was _0, such as it is possible to output a divided voltage of the correct value, § The waveform of the naguchi signal can be accurately measured.

Here, it is preferable that the first switch circuits 5—, _˜5-4 and the second switch circuits δ—, δ- ₄ are simultaneously turned on. At the same time do not turn, the first and second voltage dividing capacitors 3 to 3 _ _4, 4 -, - 4 - ₄ the accumulated electric load on because there may not be successfully Day scan charge towards ground is there.

The first sweep rate latch circuit 5 -, - _5-4 and the second sweep rate latch circuit 6, turning on simultaneously the 1-6 _ _4, an input terminal iota New 1-iota New 4 ground and during the first sweep rate latch circuit et ~ and second sweep rate latch circuit 6 -, ~ 6 - ₄ and is turned on It is equivalent to connecting in series. In other words, the input terminals IN 1 to IN 4 and the ground are shorted. Therefore, the first and second sweep rate latch circuit 5 to 5 _4, 6 _, not check ~ 6 _ ₄ simultaneously Rutoki, the third sweep rate latch circuit 7 -, ~ 7 - ₄ off This prevents shorting between the input terminals IN1 to IN4 and ground.

Controller 8, the sample-and-hold circuit unit 1 to 1 - ₄ of the operation is also controlled. FIG. 2 is a diagram showing an example of the internal configuration of the first sample and hold circuit unit 1. Incidentally, the second to fourth sample-and-hold Hj path unit 1 _-2 to 1 _ ₄ is also configured in FIG.

As shown in Fig. 2, N sample-and-hold circuits are connected in parallel inside the first sample-hold circuit section 1-1. One sample-hold circuit consists of an input buffer 1 2 _ capacitor 13 and an output buffer 1 4, and an input switch circuit 1 1-i and an output switch circuit 1 5 are connected before and after that. (All i = 1, 2, ..., N). The control unit 8 sequentially turns on the input switch circuit 1 1 — i (i = l, 2,..., N) by the timing signal sequentially delayed by a fixed time interval. As a result, the input analog signal is sampled in order at a constant time interval and held in the capacitor 13 i (i = 1, 2,..., Ν). In addition, the control unit 8 sequentially turns on the output switch circuits 15 (i = 1, 2,..., N) by the timing signal sequentially delayed at a constant time interval. As a result, the analog signals held in the capacity 1 3— = 2,... N) are sequentially output at regular time intervals.

By controlling the control unit 8 so that the switch circuits 11 and 15_i are switched on at a time interval shorter than the time required to sample the analog signal with one sample-hold circuit. Therefore, the apparent resolution can be increased only when analog signals are sampled. For example, enter If you want to measure the waveform by sampling the input analog signal finely, perform sampling at a slight delay time t as shown in Figure 3, and set the signal voltage value at each sample point to the capacitor 1 3 Can be output while being held in This makes it possible to observe the entire analog output waveform in a single shot. In addition, it is possible to measure the rise time and fall time of the waveform.

(So, the control unit 8 has N input switch circuits 1 1 —i (1 = 1, 2

In together when the N), one going to sequentially turned on every predetermined delay time t, the i-th input sweep rate latch circuit 1 I comprising first to fourth sample and hold circuit section 1 to 1 _ _4, respectively Turn on at the same time. That is,敢初the first to fourth sample and hold circuit section 1 to 1 _ ₄ is first four input sweep rate latch circuit comprising respectively 1 1 - to turn on at the same time. Then, after the delay time t has elapsed, all the input switch circuits 1 1 1 of each sample hold circuit section 1 to 1 are turned off, and the next four input switch circuits 1 1 are turned on simultaneously. . In the same manner, the input switch circuits 1 _1-3 to 1 1 _{-x included} in each of the sample hold circuit units 1 to _1-4 are sequentially turned on at intervals of the delay time t.

Similarly to the N input switch circuits 11, the N output switch circuits 15 -i included in the first to fourth sample and hold circuit sections 1 to 1 to ₄ , respectively, are connected to the output switches. Circuits 15—i (i = l, 2,..., N) are sequentially turned on one by one at a constant delay time t, and the first to fourth sample hold circuit sections 1-,. The i-th output switch circuit 1 5-i of _1-4 is turned on at the same time. Note that the i-th input switch circuit 1 1 — and the i-th output switch circuit 15 do not necessarily have to be turned on simultaneously o

In this way, analog signals input from the four input terminals IN 1 to IN 4 can be simultaneously received by the four sample and hold circuit sections 1 to _1–4 . Held Reniyo Ru is out to output them simultaneously to the multiplexer 2 2 _ ₂ is, data acquisition at the time of measuring the waveform of the four input terminals IN 1 IN 4 good Ri § Na D grayed signal input Simultaneity can be guaranteed, and the processing speed can be increased. In addition, the analog signals from each sample-hold circuit section 1 1 _ ₄ are sampled sequentially with a short delay time t, and the apparent resolution is getting higher. It can be performed.

(Second embodiment)

Next, a second embodiment of the present invention is illustrated in the drawings.

Fig. 4 is a block diagram showing a configuration example of the signal output circuit according to the second embodiment. In Fig. 4, the same reference numerals as those shown in Fig. 1 are given. In this case, the signal output circuit of the second embodiment is the same as that of FIG. 1 in addition to the components according to the first embodiment, as shown in FIG. sweep rate latch circuit 9 '9 - ₄ and the third voltage dividing capacitors 1 0 1 0 _ ₄ and the fourth sweep rate Tutsi circuit 9 9 _ ₄ and a third voltage dividing capacitors 1 0, 1 0 bets are connected in series, the series circuit and the second voltage dividing Capacity evening 4 _ 4 and the second scan I Tutsi circuits 6-6 _ ₄ are connected in parallel to each other.

That is, the fourth switch is connected to the second voltage dividing capacitor 4 and the second switch circuit 6—, which are connected in parallel with each other in the previous stage of the first sample hold circuit section 1. Circuit 9 and the third voltage-dividing capacitor 1

A series circuit consisting of 0 is further connected in parallel.

The second sample-hold circuit part 1 _- second dividing capacitor 4 _ ₂ connected in parallel with each other in the _second preceding and second sweep rate Tutsi circuit 6 _{- 2} Respect, the fourth sweep rate latch circuit 9 _-2 third voltage dividing capacitors 1 0 ₂ Toka et consisting series circuit is further connected in parallel.

The third sample hold circuit 1 - ₃ of parallel connected for ¾ 2 dividing capacitor 4 ₃ and the second one another in front sweep rate latch circuit 6 - for _three, fourth sweep rate Tsu a latch circuit 9 _ ₃ third dividing Capacity evening 1 0 _ ₃ Toka et consisting series circuit is further connected in parallel.

The fourth sample hold circuit second dividing Capacity evening connected in parallel with each other in front of the 1 _ ₄ 4 ₄ and the second sweep rate latch circuit 6 - for _four, the fourth sweep rate latch circuit 9 _ ₄ and the third voltage dividing Capacity evening 1 0 ₄ Toka et consisting series circuit is further connected in parallel.

Control unit 8, the first sweep rate latch circuit 5 _ ~ 5 _4, the second sweep rate pitch circuit 6 ~ _6-4, the third sweep rate latch circuit 7 _, in addition to ~ _7-4, the fourth switch circuit 9 - ~ 9 - controlling the operation regarding the _fourth on Z off.

: In the second embodiment, there are three operation modes during normal signal output. The first mode is a mode in which the voltage of the analog signal input from the input terminals IN 1 to IN 4 is input to the sample-and-hold circuit sections 1 to 1 to ₄ without being divided. In this mode, the first sweep rate latch circuit 5-5 _ ₄ and the third sweep rate latch circuit 7 to 7 _ ₄ is turned on, the second sweep rate latch circuit 6, 1-6 - ₄ Turn off the _4th switch circuit 9_, ~ 9-4.

In this state, the signal voltage input from the input terminals IN 1 to IN 4 is passed through the third switch circuit 7-, ~ 7 _-4 and the first switch circuit 5 _, ~ 5 _ _4. is input to the sample-and-hold circuit unit 1 to 1 _4. The plurality of signals held in the sample hold circuit units 1 and 1 _ ₄ is selected and output by the multiplexer 2 to 2 _ _3, each of the output terminals OU T sequentially.

In the first mode as described above, the signal voltage input from the input terminals IN 1 to IN 4 is not very large (for example, the signal voltage is a ± 5 [V] range). Di), the sample-hold circuit section 1 - is effective when it is within the allowable voltage value that can be held in ~ 1 _ _4.

The second mode is an input terminal IN 1 - IN 4 first and the voltage of analog signal inputted from the second voltage dividing Capacity evening 3- ~ 3- _4, 4, ~ 4 - ₄ it is a mode one de inputting more divides the sample-and-hold circuit section 1 to 1 _4. In this mode, the third sweep rate latch circuit 7 to _7-4 is turned on, the first switch's circuits - et a second sweep rate latch circuit .delta., .delta. ₄ and fourth sweep rate Switch off circuits 9 to _9-4 .

In this state, the first and second voltage dividing capacitor 3 -, ~ 3 _ _4, 4 -, ~ _4.4 charge corresponding to the signal voltage is performed is charged divider action in, is the partial pressure signal voltage sample and hold circuit section 1 - is input to the ~ 1- _4. And, the sample-and-hold circuit unit 1, a plurality of signals held in ~ _1-4 multiplexer 2 ~ is selected by _2-3, is output one by one from the output terminal Omicron U Ding sequentially.

In the second mode as described above, the signal voltage input from the input terminals Ι Ν 1 to Ι Ν 4 is large (for example, the signal voltage is within the range of ± 20 [V]), and the sample hold circuit part 1, is effective technique when it exceeds the allowable voltage value that can be held in ~ 1 _ _4.

In mode 3, the voltage of the analog signal input from the input terminals I Ν 1 to Ι Ν 4 is set to the first, second and third voltage dividing capacitors 3-, ~ 3— ₄ , 4 _, 1-4 _ _4, 1 0 _ a mode for inputting by dividing by ~ 1 0 _ ₄ to the sample-hold circuit section 1 to 1 _-4. In this mode, the third sweep rate latch circuit 7, 1-7 one ₄ and the fourth and sweep rate latch circuit 9 to 9 _ ₄ is turned on, the first sweep rate latch circuit 5-5 _-4 the second sweep rate latch circuit 6 _"| ~ 6 - to ₄ and the O off.

In this state, the first to third voltage-dividing capacitors 3 and 3 _4, 4, 1-4 - _4, 1 0 -, charges corresponding to the signal voltage to ~ 1 0 ₄ is charged by divider action Done 1 b

Is, the divided signal voltage sample and hold circuit section 1 to 1 - are entered into _four. Then, the sample-and-hold circuit section 1 - ~ 1 a plurality of signal held in _-4 multiplexer 2, is selected by the 1-2 _ _3, is outputted from one output terminal OUT in order.

In the third mode as described above, the signal S pressure input from the input terminals I N 1 to I N 4 is very large (for example, the signal voltage is in the range of 60 [V].

), The sample and hold circuit section 1 -, ~ 1 - voltage tolerance can be kept at ₄ is effective when a large skill <exceeds.

The control unit 8 performs the first and second switch circuits 5 to 5—4> 6 −〗 to 6 at a predetermined timing when operating in the second mode as described above. - 4 O emissions, switching to a third sweep rate latch circuit 7 to _7-4 off (fourth sweep rate, one latch circuit 9 to 9 _ ₄ remains off). This ensures that the first and second voltage dividing capacitors 3 and 3 _4, 4 ~ _4-4 charges accumulated in the first and second sweep rate Tutsi circuit [delta] -, [delta], 6 -, - 6 - ₄ is de Suchaji toward the ground via the first and second voltage dividing capacitors 3, ~ 3 _4, 4 _, ~ _4-4 it is reset. Reset after the first and second sweep rate latch circuit et ~ al, 6-6 _ ₄ again off, the third sweep rate latch circuit 7, to 7 to switch to _-4 again on.

The control unit 8 at a predetermined evening Lee Mi ring when operating in the third mode, the first and second sweep rate latch circuit 5 -, ~ 5 _ _4, 6, 1-6 _ ₄ oN, third sweep rate latch circuit 7 _, ~ _7-4 switch off (fourth sweep rate latch circuit 9 to 9 ₄ still on). Thus, the first to third voltage-dividing capacitor 3 _, ~ 3 _4, 4 ～'4 - _4, 1 0, - 1 0 ₄ charges accumulated in the first and second sweep rate latch circuit 5 to 5 _4, 6 _, toward the ground via 1-6 ₄ is Day scan charge, first to third voltage dividing Capacity evening 3 -, ~ 3 _ _4, 4_, 1-4 _ _4, 1 0-1 0 - ₄ is reset. After reset, the first and second The sweep rate latch circuit δ -, δ, 6-, ~ 6- 4 again off, the third sweep rate latch circuit 7 _, switched on ~ _7-4 again.

The control unit 8 first to third sweep rate latch circuit 5 -, - 5 ₄ 6 - 6 - _4, 7, Thailand Mi ring switching the ~ 7 4, first to third voltage dividing Capacitive evening 3 to 3 _ ₄ , 4 to 4 _ ₄ , 10 −, to 10 _ ₄ Expected that the total leakage amount when the charge leaks over time exceeds the allowable value Within a predetermined time. For example, the control unit 8, its good Unatai Mi first to third sweep rate for each ring latch circuit 5 to 5 _4, 6 _, ~ 6 _ _4, 7 -, ~ 7 ₄ as described above Switch to.

In this way, the first to third partial pressure caps 3-1 4 4:-1 ~

4-4 Even if voltage drift occurs from 10 to 10 _-4 little by little, it is reset at a predetermined timing, and m load corresponding to the signal voltage is accumulated again. Will come to be. Accordingly, the first to third voltage dividing Kyaha ° Sita 3 3 _ _4, 4 1 4 ₄ 1 0! ~ 1 0 force, et charge voltage drill off Bok which occurs good when you leak Suppressing and outputting the correct value of the voltage will cause a failure. Therefore, the waveform of the analog signal can be accurately measured.

In the above-described first and second embodiments, an example has been described with four samples e Ichiru de circuit 1 to 1 _-4, this number is merely exemplary and more or less than this May be. For example, if the purpose is to suppress the voltage drift due to charge leakage without considering the simultaneous retention of analog signals, only one sample hold circuit section 1 should be provided. Also good. However, in this case, the multiplexer 2 ~ 2 _ ₃ in the subsequent stage of the sample-and-hold circuit unit 1 is unnecessary, 5 out dregs Lee latch circuit 1 shown in FIG. 2, and 1 5 - by _x, the delay time t Each sampled and held signal is output sequentially. In the configuration shown in FIG. 2, the input sweep rate latch circuit 1 1 _- may be using a multiplexer in place of the output sweep rate latch circuit 1 5 - - ₃ to 1 1, instead of ~ 1 5 _ _x A multiplexer may be used.

In the first and second embodiments, N sample hold circuits are provided in one sample hold circuit section 1 as shown in FIG. 2, and these are sequentially operated at intervals of the delay time t. Although an example has been described, N == 1 may be used. In this case, although the resolution of one analog signals that a small, four instead the sample-and-hold circuit section 1 -, by sequential operation at intervals of ~ 1 _ ₄ the delay time t, the four input terminals IN High-speed selection of analog signals input from 1 to IN 4 can be realized. For example, if an AZD converter is provided after the output terminal OUT, an A / D converter that can operate at high speed can be realized.

In the first and second embodiments described above, an example in which a plurality of sample-and-hold circuit units 1-, to _1-4 are provided in front of the multiplexers 2 to 2 to ₃ has been described. to the configuration downstream of ~ 2 _ ₃ comprises one sample ho one field circuitry portion, or one sample-hold circuit is also possible to apply the present invention.

In the first and second embodiment, the sample-hold circuit section 1 to 1 _ ₄ and the multiplexer 2, to 2 _{- 3} but with showing a configuration example of a signal output circuit having a present invention It is not limited to this. For example, if circuitry required partial pressures of the capacitor when there is tolerance of the input voltage may be used a circuit other than the sample-hold circuit section 1 to 1 _ _4. In this case, by applying the present invention, voltage drift due to leakage of charges accumulated in a capacitor provided for voltage division can be suppressed.

In the above first and second embodiments, the third sweep rate latch circuit 7, 1-7 - ₄ is not an essential component. That is, it depends on the application of the signal output circuit. In some cases, there is no particular problem even if the analog signal input terminal is shorted to the ground. In such a case, the third sweep rate latch circuit 7 to 7 _{- 4} may not be provided.

In the second embodiment, the second voltage dividing capacitor A—! A and the second switch circuits 6 —, to 6 — ₄ connected in parallel to each other are

Although an example in which a set of series circuits consisting of _four switch circuits 9-, ~ 9_4 and a third voltage dividing capacitor 10-, ~ 10 is connected in parallel has been explained, A plurality of sets of series circuits may be connected in parallel. In the second embodiment, the fourth switch circuits 9 to 9 and the

3 voltage-dividing capacitors 1 0-1 0 - ₄ a series circuit formed by connecting in series a

It has been described Te As the configuration of connecting in parallel with the second voltage dividing Capacity evening 4-4 _ _4, but is not limited thereto. For example, the first partial pressure capacitor

3 to relative ~ 3 _ ₄ may be connected in parallel, first and second voltage dividing capacitors 3 ~ 3 - _4, 4 to connect in parallel with the series circuit of 1-4 _ ₄ You may do it.

In addition, each of the first and second embodiments described above is merely an example of a specific embodiment for carrying out the present invention, which limits the technical scope of the present invention. It should not be construed. Ie

The present invention can be implemented in various forms without departing from the spirit or the main features thereof. Industrial applicability

The signal output circuit of the present invention is useful for a circuit that sequentially outputs an input signal while being sampled and held by a sample and hold circuit. For example, it is output from an AZD conversion device that multiplexes multiple analog signals into digital signals, for example, a semiconductor device. This is useful for test devices that test the circuit functions of semiconductor devices by measuring the voltage of analog signals.

Claims

Seeking

1. first and second voltage divider capacitors connected in series between the signal voltage input line and ground;

First and second switch circuits connected in parallel to the first and second voltage dividing capacitors, respectively;

A signal output circuit comprising: a control unit that controls the first and second switch circuits to be turned on at a predetermined timing.

2. The signal output circuit according to claim 1, wherein the control unit controls the first and second switch circuits to be turned on simultaneously.

3. A parallel circuit composed of the first and second voltage dividing capacitors and the first and second switch circuits is connected in series on the input line of the signal voltage. With 3 switch circuits,

2. The signal output circuit according to claim 1, wherein the control unit controls the third switch circuit to turn off at a predetermined timing.

4. The control unit turns on the first and second switch circuits at the same time, and turns on the third switch as long as the first and second switch circuits are turned on. 4. The signal output circuit according to claim 3, wherein the signal output circuit is controlled to be turned off.

5. A series circuit formed by connecting the fourth switch circuit and the third voltage dividing capacitor in series is connected in parallel to at least one of the first and second voltage dividing capacitors. The signal output circuit according to claim 1, wherein the signal output circuit is configured as described above.

6. The input signal is sampled by the sample and hold circuit. And a signal output circuit that sequentially outputs while holding, the sample hold circuit section, the first and second voltage dividing capacitors, and the first and second switches. Each of the above sample and hold circuit units is configured by connecting N (integer N≥2) sample and hold circuits in parallel.

The control unit sequentially operates the N sample and hold circuits included in the sample and hold circuit unit one by one for each fixed delay time, and the number i includes each of the plurality of sample and hold circuit units. 2. The signal output circuit according to claim 1, wherein the sample hold circuits of huge (i = 1, 2,..., N) are controlled to operate at the time of 1 mouth J. .

7 Sampling and holding the input signal, and a plurality of sample and hold circuit units configured by paralleling N (N ≥ 2) sample hold circuits, and

Multiplexers that select one by one while switching among the plurality of signals output from the plurality of sample hold circuit sections, and sequentially output them,

The N sample hold circuits included in the sample hold circuit unit are sequentially operated one by one for each fixed delay time, and the i th (i = 1, 2, ·

• · ·, N) A signal output circuit characterized by having a control unit that controls the sample and hold circuits to operate simultaneously.