WO2007018913A2

WO2007018913A2 - Reduction of programming time in electrically programmable devices

Info

Publication number: WO2007018913A2
Application number: PCT/US2006/026925
Authority: WO
Inventors: Johnny Chan; Jeffrey Ming-Hung Tsai; Tin-Wai Wong
Original assignee: Atmel Corp
Current assignee: Atmel Corp
Priority date: 2005-07-25
Filing date: 2006-07-10
Publication date: 2007-02-15
Anticipated expiration: 2008-01-25
Also published as: TW200713285A; US7233528B2; US20070019471A1; WO2007018913A3

Abstract

A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data 'one” value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data 'zero' is to be applied to the bit cell, a charge pump engages to bias the cell and activate a hot electron injection process to affect the programming. If a data 'one' is to be applied to the bit cell, no programming activity is undertaken and the process increments to the next bit cell in the data structure. Therefore, total programming time is reduced proportionally to the number of data 'one' bits to be programmed. Where more than one charge pump is engaged in parallel to a data structure, total programming time is further reduced when two data 'one' values are to be programmed in parallel.

Description

REDUCTION OF PROGRAMMING TIME IN ELECTRICALLY PROGRAMMABLE DEVICES

TECHNICAL FIELD

The present invention relates to programming electrically programmable devices. More particularly, the invention relates to a method for determining programming of data based on an input data value.

BACKGROUND ART

Semiconductor memory devices are typically classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are subdivided into dynamic random access memories (DRAMs) and static random access memories (SRAMs) . Non-volatile memory types include mask read-only memories (MROMs) , programmable read-only memories (PROMs) , erasable programmable read-only memories (EPROMs) , and electrically erasable programmable read-only memories (EEPROMs) . Additionally, flash EEPROMs are advantageous as mass storage devices because their integration density is high compared with conventional EEPROMs. Non-volatile semiconductor memories have attained broad utilization due to an ability to retain data within a device, even after power has been suspended. EEPROMs are non-volatile semiconductor memories that possess these abilities and additionally are able to store data by electrically erasing and writing storage devices. This programming process can be repeated over hundreds of thousands of cycles .

A flash memory is a type of non-volatile memory where all bit cells or pages of bit cells are erased simultaneously to a logic one or logic zero level before programming occurs. A bit cell is programmed by hot electron injection (HEI) . Each bit cell of the flash memory is erased by tunneling of electrons through a thin tunnel diode window from a conductive channel to a floating polysilicon gate. The bit cell contains a select transistor and a sense or memory transistor. With an NMOSFET device used for the memory transistor, erasure produces a logic level of "1" in the cell. A PMOSFET memory transistor produces a complementary result. A charge pump is used for generating the voltages required for programming the bit cells of the flash memory. The size of a charge pump on a substrate is large due to the size of a typical capacitor used and the number of stages of capacitors required. It is desirable to keep the number of charge pumps per byte small in order to save space on the substrate due to the relatively large size of each charge pump.

Programming of a bit cell takes one programming time, t_P. A charge pump programs one bit cell at a time. For the NMOSFET-type memory device, programming (writing) each bit cell involves setting the cell to a "0" logic level by biasing the cell with a charge pump and inducing hot electron injection for the programming time, t_P. In a bit cell to be programmed to a logic level "1," no programming is required. The initial bulk erasing operation places each bit cell into a "1" logic level condition by default.

One or more charge pumps may engage a particular data structure. For instance, two charge pumps may be associated with a byte of data at a time. A total time for programming a data structure is given by

BCxtp — , where BC is a number of bit cells in the data

CP structure, t_P is an amount of time for programming one bit cell, and CP is a number of charge pumps engaged in programming the data structure. For example, in the case of programming a single byte data structure with two charge pumps, the total programming time is equal to

8x3 msec or ,12„ mi.l-,l-,i.second,s (msec_λ) w-huere the programming time, t_P, for a single bit cell is 3 msec.

With reference to Fig. 1, a prior art process flow diagram 100 of a single charge pump programming a byte wide data structure commences with writing 110 Bit (7) , where a bit cell index, i, equals 7. The process continues with writing 120 Bit (6) and continues through each bit position of the byte by decrementing the bit cell index, i, by one to engage each successive bit cell location. The process continues until reaching the step of writing 180 Bit(0) . The process concludes with ending 190 the flow. The programming time for this process is

8xt_p, where there are eight bit cells (BC=8) for the byte data structure and one charge pump (CP=I) .

With reference to Fig. 2, a prior art process flow diagram 200 for two charge pumps programming a byte wide data structure commences with writing 210 Bits (7, 6), where a bit cell pair index, i:j, equals 7, 6. The process continues with writing 220 Bits (5, 4) and continues through bit pairs of the byte by decrementing each element of the bit cell pair index by two. The process continues until reaching the step of writing 240 Bits(l, 0). The process concludes with ending 250 the flow. A programming time for the dual charge pump process, substituting the prior art values into the

expression given supra, i ^•s ^{8x t}P— or 4Ax 4t._p .

However, the direct approach of the prior art of engaging the charge pumps to the data structure does not take into account any correlation of a logic level set by the initial erasing of the bit cells and a logic level to be programmed. A direct programming approach applies an equal programming time per bit cell regardless of the final logic level of programmed data. A device not taking into account a lack of required programming for one gender of input data is expending programming time with no effective programming transpiring. This lack of effective programming happens with each occurrence of an input data value equaling the erased logic level . It would be ideal if a device would take into account the gender of data to be programmed and skip the programming of bit cell locations with an erased logic level equal to the gender of data to be programmed. Combining data gender coordinated programming with an ability to engage multiple charge pumps would truncate overall programming time in proportion to the amount of data equal to the logic level of the erased bit cells.

SUMMARY OF THE INVENTION

A process of programming a flash memory device incorporates, for example, two charge pumps per byte of bit cells to be programmed. In an exemplary embodiment, the entirety of bit cells in the device is first erased. Erasure of a bit cell places the cell in a data "one" value. As the programming process progresses through the cells, a data content to be applied to the cell is scrutinized. If a data "zero" condition is to be applied to the bit cell, a charge pump is engaged to bias the cell and activate a hot electron injection process to affect the programming. If a data "one" value is to be applied to the bit cell, no programming activity is undertaken and the process increments to the next bit cell to be programmed and one bit cell programming time is saved. In this way total programming time is reduced in direct proportion to the number of data "one" bits to be programmed. Where more than one charge pump is engaged in parallel to a data structure, a further reduction in total programming time is realized with each pair of data "one" values occurring in parallel .

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a prior art process flow diagram of programming a byte wide data structure with a single charge pump.

Fig. 2 is a prior art process flow diagram of programming a byte wide data structure with two charge pumps .

Fig. 3 is a process flow diagram of an exemplary method of programming a memory cell data content based on data value. Figs. 4a and 4b are exemplary bit sequence programming arrays for a two charge pump approach to programming an electrically programmable device.

DETAILED DESCRIPTION OF THE INVENTION With reference to Fig. 3, an exemplary process flow diagram 300 of a data content based programming method, commences with setting 305 the variable test quantity, ZC, equal to the number of zeros in a sequence of input data to be stored. The method continues with setting 310 an index, i, equal to zero and determining

315 if ZC is equal to zero. If ZC is equal to zero, the process ends 320. If ZC is not equal to zero, a determination 325 is made whether an i^th data bit is equal to zero. If the i^th data bit is not equal to zero, a step of incrementing 340 the index, i, by one is made. If the i^th data bit is equal to zero, a next step of writing 330 the i^th data bit to a respective bit cell is taken and a step of decrementing 335 ZC by one is taken. The process flow continues with the step of incrementing 340 the index, i, by one, as described supra. A next step is determining 315 if ZC is equal to zero with the incremented index, i, and subsequently proceeding as described supra. The total amount of programming time for a byte data structure, per the exemplary process

f-_Fliow, is given _Xb-.y —%zerosxBCxt_p— , where %zeros i-s ^the

percentage of zeros (expressed as a decimal) in the sequence of input data.

With reference to Fig. 4a, a first exemplary bit cell programming sequence array 405, two charge pump programming rows CPl, CP2 are labeled on the ordinate with four programming time slots tχ-t₄ sequenced along the abscissa. Each programming time slot signifies a duration of programming time equal to t_P. A first charge pump CPl programs Bit (7) in a first programming time slot ti, Bit (6) in a second programming time slot t_2/ Bit (5) in a third programming time slot t₃, and Bit (4) in a fourth programming time slot t₄. A second charge pump CP2 programs Bit (3) through Bit(O) in the same sequence of four programming time slots ti-t₄. Each of the two charge pumps CPl, CP2 sequences through the four bit cell programming stages during the four respective programming time slots tχ-t₄. For either charge pump, a data "one" value to be programmed by the data content programming method (Fig. 3), described supra, means that the respective programming time slot may be skipped; saving one programming time, t_P. With each charge pump operating independently, any sequence of zeros may be operated on with the greatest optimization of data "one" contents within the input data sequence and minimizes an overall programming time for the data structure.

For instance, a data byte with a value

10111000, engaged with the bit cell programming sequence above (Fig. 4a) , would have the first charge pump CPl programming the sequence 1011 and the second charge pump CP2 programming the sequence 1000 in parallel. The first charge pump CPl requires one programming time slot t_P to program the single zero within the input data sequence. The second charge pump CP2 requires three programming time slots or 3xt_Pto program the three zeros in the input data. A limiting factor in bit cell programming optimization, therefore, is the number of zeros in the input data for a given charge pump .

In a further example, a data byte with a value 10010011 has an equal number of zeros to program for each charge pump CPl, CP2. The first charge pump CPl programs the sequence 1001 and the second charge pump CP2 programs the sequence 0011. The total amount of programming time,

%zeros x BC x t_p , , 0.5x8xt_p using the expression — _cp — ,, is eq_^ual to ₂ or 2xt_p, where t_P is the programming time for one bit cell. Therefore, both charge pumps CPl, CP2 finish programming at the same time and finish in half the time of a conventional bit cell programming sequence.

With reference to Fig. 4b, a second exemplary bit cell programming sequence array 415, two charge pump programming rows CPl, CP2 are labeled on the ordinate with four programming time slots t_x-t₄ sequenced along the abscissa. Each programming time slot signifies a programming duration equal to t_P. A first charge pump CPl programs Bit (7) in a first programming time slot t_x,

Bit (5) in a second programming time slot t₂, Bit (3) in a third programming time slot t₃, and Bit(l) in a fourth programming time slot t₄. A second charge pump CP2 programs Bit (6) through Bit(0) in the same sequence of four programming time slots t_x-t₄. Each of the two charge pumps CPl, CP2 sequences through the four bit cell programming stages during the four respective programming time slots ti-t₄. For either charge pump, a data "one" value programmed by the data content programming method (Fig. 3) , described supra, means that the respective programming time slot may be skipped; saving one programming time, t_P. With each charge pump operating independently, any sequence of zeros may be operated on with the greatest optimization of data "one" content within the input data sequence and minimizes an overall programming time for the data structure.

For instance, a data byte with a value 10111000, engaged with the bit cell programming sequence above (Fig. 4b), would have the first charge pump CPl programming the sequence 1110 and the second charge pump CP2 programming the sequence 0100 in parallel. The first charge pump CPl requires one programming time slot t_P to program the single zero within the input data sequence. The second charge pump CP2 requires three programming time slots or 3xt_Pto program the three zeros in the input data. A limiting factor in bit cell programming optimization, therefore, is the number of zeros in the input data for a given charge pump. In a further example, a data byte with a value

10010011 has an equal number of zeros to program for each charge pump CPl, CP2. The first charge pump CPl programs the sequence 1001 and the second charge pump CP2 programs the sequence 0101. The total amount of programming time, . _^1 . %zeros^χBCχt_p , _π 0.5χ8xt_p using the expression — — , is equal to —

GJr 2 or 2xt_P, where t_P is the programming time for one bit cell. Therefore, both charge pumps CPl, CP2 finish programming at the same time and finish in half the time of a conventional bit cell programming sequence. From the two examples cited above (Figs. 4a,

4b), two different bit cell programming sequences 405, 415 produce the same net total programming time when two charge pumps engage the same data byte value. An artisan would appreciate that certain data structures may contain a predetermined distribution or a probability distribution (or density) function (PDF) of occurrences of ones or zeros within certain fields of a data structure or data word. For instance, a microprocessor architecture may have a particular distribution of opcodes and operand encodings within an instruction set encoding scheme. The distribution of encodings may accentuate a number of ones or zeros within a particular field or subfield within each instruction word across a range of storage locations. When an electrically programmable storage device is matched to a data structure with a known probability distribution function within subfields, a bit cell programming sequence may be crafted to optimize a total programming time of the device.

A person skilled in the art would also readily identify a similar situation occurring within the probability distribution of opcodes within the encodings of instructions for typical programming. For example, certain logical or arithmetic operations may occur more often than operations to test equivalence or to perform comparisons. The respective operations and their encodings therefore, will occur with different likelihood. A bit cell programming sequence may be tailored to optimize programming time in view of the distribution of encoding.

In a further example of operand encoding, a RISC processor targeted to operate with the C programming language, may also operate within a recommend procedural call standard (PCS) . A PCS is employed to coordinate a conformity in register usage between calling and called program segments. The use of a PCS will specify a subset of registers to contain a finite set of operand locations. The instructions used at subprogram calls will have a limited set of register location (operand) encodings and therefore, a limited distribution of data within the operand subfield of storage instructions. The limited operand encodings make an opportunity for a bit cell programming sequencing approach similar to those presented supra. Knowing the distribution of the opcodes from typical programs would allow an artisan to tailor a bit cell programming sequence to optimize storage of such programs and reduce the total bit cell programming time. While examples have been presented of matching bit cell programming sequences to particular data distribution probabilities, one skilled in the art would readily recognize that many different bit cell programming sequences may be incorporated to store the same data. The skilled artisan would also recognize that there may exist a probability of distribution in the data that will make certain selections of bit cell programming sequences more effective in reducing total bit cell programming time for a memory device. The exemplary embodiments contained herein should thus be considered in an illustrative rather than restrictive sense.

Claims

1. A method of programming a nonvolatile electrically programmable device comprising: ascertaining a count, the count indicating a quantity of data values of a first gender in a sequence of input data; indexing the sequence of input data; making a first determination whether a data content at the position indexed in the sequence of input data is equal to the first gender; programming a bit cell location if the first determination is true that the data content is equal to the first gender; decrementing the count if the first determination is true that the data content is equal to the first gender; and incrementing the index of the position in the sequence of input data.

2. The method of claim 1, further comprising making a second determination whether the count is equal to a defined value, the defined value being determined by a number of locations desired to be processed.

3. The method of claim 2 , further comprising ending the programming if the second determination is true that the count is equal to the defined value.

4. The method of claim 1, further comprising saving a programming time of the bit cell location if the input data content is not equal to the first gender.

5. The method of claim 1, further comprising reducing an overall bit cell programming time by adding one or more charge pumps .

6. The method of claim 5, further comprising assigning a bit cell programming sequence of the two or more charge pumps based on an input data probability distribution function.

7. The method of claim 1, wherein the data values of the first gender are zeros.

8. The method of claim 1, wherein the data values of the first gender are ones.