WO2007017803A2 - Ldmos transistor - Google Patents

Ldmos transistor Download PDF

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Publication number
WO2007017803A2
WO2007017803A2 PCT/IB2006/052644 IB2006052644W WO2007017803A2 WO 2007017803 A2 WO2007017803 A2 WO 2007017803A2 IB 2006052644 W IB2006052644 W IB 2006052644W WO 2007017803 A2 WO2007017803 A2 WO 2007017803A2
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WO
WIPO (PCT)
Prior art keywords
region
drain
ldmos transistor
metal layer
top metal
Prior art date
Application number
PCT/IB2006/052644
Other languages
French (fr)
Other versions
WO2007017803A3 (en
Inventor
Stephan J. C. H. Theeuwen
Freerk Van Rijs
Petra C. A. Hammes
Original Assignee
Nxp B.V.
Zawilski, Peter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Nxp B.V., Zawilski, Peter filed Critical Nxp B.V.
Priority to EP06780280A priority Critical patent/EP1915783A2/en
Priority to KR1020087005555A priority patent/KR100932363B1/en
Priority to JP2008525687A priority patent/JP2009505391A/en
Priority to US11/997,209 priority patent/US20080237705A1/en
Publication of WO2007017803A2 publication Critical patent/WO2007017803A2/en
Publication of WO2007017803A3 publication Critical patent/WO2007017803A3/en

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53219—Aluminium alloys
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L29/402—Field plates
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to an LDMOS transistor.
  • RF power amplifiers are the key components.
  • RF radio frequency division multiple access
  • LDMOS Laterally Diffused Metal Oxide Semiconductor, generally abbreviated as LDMOS, transistors are now the preferred choice of technology, because of their excellent high power capabilities, gain and linearity. To be able to meet the demands imposed by new communication standards, the performance of the LDMOS transistors with constantly shrinking dimensions is subject to continuous improvements.
  • an LDMOS transistor which comprises a source and a drain region in a semiconductor substrate, in which the source and the drain region are mutually connected through a channel region.
  • the source region and the substrate are electrically connected through a first metal layer.
  • the LDMOS transistor further comprises a gate electrode on the semiconductor substrate for influencing an electron distribution in the channel region.
  • the drain region comprises a drain contact region and a drain extension region extending from the drain contact region towards the channel region.
  • the drain contact region is electrically connected via a drain contact to a top metal layer, which extends only over the drain contact region and does not extend over the drain extension region.
  • the top metal layer negatively influences the depletion of the drain extension region, because the series resistance of the drain extension region would become more voltage dependent if the top metal layer would extend over the drain extension region thereby reducing the performance of the LDMOS transistor.
  • the top metal layer needs to have a high current capability, which results in a wide and thick top metal layer to be able to withstand a high current level without suffering from electromigration. Because the top metal layer is allowed to extend only over the drain contact region and because the top metal layer is wide enough to be able to withstand a high current level, the drain contact region occupies a relatively large area, which disadvantageously increases the total area occupied by the LDMOS transistor.
  • the output capacitance of the LDMOS transistor is, amongst others, determined by the capacitive coupling between the source region and the drain region, and comprises the drain extension region to source region capacitance and the drain contact region to source region capacitance.
  • the drain extension region is almost completely depleted and hence the output capacitance of the LDMOS transistor is, at this typical bias condition, mainly determined by the drain contact region to source region capacitance.
  • the relatively large output capacitance disadvantageously decreases the RF power output efficiency of the LDMOS transistor, which is defined as the RF output power divided by the DC input power of the LDMOS transistor.
  • the LDMOS transistor according to the invention comprises a source region and a drain region, both of a second semiconductor type, in a semiconductor substrate of a first semiconductor type, that are mutually connected through a channel region of the first semiconductor type.
  • a gate electrode extends over the channel region and is able to influence an electron distribution in the channel region.
  • the drain region comprises a drain contact region and a drain extension region, which drain extension region is adjacent to the channel region.
  • the LDMOS transistor according to the invention further comprises a top metal layer which is electrically connected to the drain contact region through a drain contact and which extends over the drain extension region with a distance between the top metal layer and the drain extension region that is substantially larger than 2 ⁇ m.
  • the invention is based on the insight that if the distance between the top metal layer and the drain extension region is such that the top metal layer hardly influences the depletion of the drain extension region, it becomes possible to allow the top metal layer to extend over the drain extension region without affecting the performance of the LDMOS transistor. Thereby it becomes possible to give the top layer any size needed to obtain the desired current capability, without a need to have an equally large size for the drain contact region. Furthermore, the area of the drain contact region and hence the output capacitance of the LDMOS transistor may be reduced in comparison with the prior art, because the area of the drain contact region does not need to be as large as the size of the top metal layer. The reduced output capacitance beneficially increases the RF power output efficiency of the LDMOS transistor.
  • Another advantage is that the reduction of the area of the drain contact region enables a reduction of the total area occupied by the LDMOS transistor.
  • the distance between the top metal layer and the drain contact region is such that the top metal layer does not affect the feedback capacitance.
  • the feedback capacitance is the capacitance between the drain region and the gate electrode. A shorter distance between the top metal layer and the drain contact region would increase the feedback capacitance thereby reducing the RF performance of the LDMOS transistor.
  • the distance between the top metal layer and the drain extension region is such that the drain to source breakdown voltage of the LDMOS transistor at zero gate voltage (B Vdss) is not affected by the top metal layer.
  • the distance between the top metal layer and the drain extension region is 5 ⁇ m. At this distance the influence of the top metal layer on the performance of the LDMOS transistor appeared to be sufficiently small.
  • the electrical connection to the drain contact region via the drain contact further comprises at least one intermediate metal layer and at least one inter-metal contact between the intermediate metal layer and the top metal layer.
  • the introduction of the at least one intermediate layer beneficially increases the distance between the top metal layer and the drain extension region and advantageously introduces a degree of freedom for the interconnection scheme of the LDMOS transistors and other devices on the IC (Integrated Circuit).
  • the top metal layer comprises a mixture of Al and Cu.
  • the drain contact region of a first LDMOS transistor is common with the drain contact region of a second LDMOS transistor, which second LDMOS transistor is mirror-symmetrical with respect to the first LDMOS transistor.
  • the advantage of the reduced area of the drain contact region is now shared by two LDMOS transistors, which will reduce the total area occupied by LDMOS transistors on the IC even further.
  • the LDMOS transistor comprises a substrate contact region of the first semiconductor type, which adjoins the source region in which the substrate contact region and the source region are electrically connected via a suicide layer.
  • the suicide layer is thinner than the first metal layer, which is used in the prior art to electrically connect the substrate contact region and the source region, thereby further reducing the feedback capacitance and hence further increasing the RF power output efficiency of the LDMOS transistor, because the dimensions of the suicide layer are smaller than those of the standard metal layer.
  • the LDMOS transistor comprises a shield layer between the gate electrode and the drain contact region, wherein the shield layer extends over a part of the drain extension region. The introduction of the shield layer reduces the feedback capacitance between the gate electrode and the drain region, which is beneficial for the RF performance of the LDMOS transistor.
  • Fig. 1 shows a diagrammatical cross-sectional view of an LDMOS transistor according to the prior art
  • Fig. 2 shows a diagrammatical cross-sectional view of an LDMOS transistor according to an embodiment of the invention
  • Fig. 3 shows a diagrammatical cross-sectional view of an LDMOS transistor according to a second embodiment of the invention
  • Fig. 4 shows a diagrammatical cross-sectional view of an LDMOS transistor according to a third embodiment of the invention.
  • Fig. 1 depicts a cross-sectional view of a conventional LDMOS transistor 99 according to the prior art, comprising a substrate 2 of a semiconductor material, in this case p-type silicon, on which a p-type epitaxial layer 12 is formed.
  • the LDMOS transistor 99 further comprises an n-type source region 3, an n-type drain region 5 and a poly silicon gate electrode 10, which may optionally be provided with a suicide layer and which extends over a channel region 4, which is in this example a laterally diffused p-type region.
  • the source region 3 and the drain region 5 are mutually connected through the channel region 4.
  • a p- type substrate contact region 11 electrically connects to the substrate 2 and adjoins the source region 3 on a side opposite to the side, which adjoins the channel region 4.
  • the channel region 4, the substrate contact region 11, the source region 3 and the drain region 5 are provided in the epitaxial layer 12.
  • the gate electrode 10 is separated from the substrate 2 by a gate oxide layer 18, which for example comprises thermally grown silicon dioxide.
  • the source region 3 is electrically connected to the substrate contact region 11 through a source contact 41, a first metal layer 21 and a substrate contact 40. Hence the source region 3 is, via the substrate contact region 11, electrically connected to the bottom surface of the substrate 2.
  • the drain region 5 comprises an n-type drain extension region 7, which accommodates the high voltage operation of the LDMOS transistor 99, and an n-type drain contact region 6.
  • the drain extension region 7 has a lower doping level than the drain contact region 6 and is optimized for a maximum output power of the LDMOS transistor 99. It should be noted that the drain extension region 7 may also comprise multiple different-type doping levels, which improves the lifetime of the device.
  • the LDMOS transistor 99 further comprises a shield layer 31, which serves as a dummy gate electrode and improves the feedback capacitance.
  • the shield layer 31 in this case extends over a portion of the gate electrode 10 and the drain extension region 7 and is separated from the gate electrode 10 by an insulation layer 14, which for example comprises a plasma oxide.
  • the shield layer 31 is separated from the epitaxial layer 12, and hence the drain extension region 7, by the gate oxide layer 18 and the insulation layer 14. Due to the close proximity of the shield layer 31 to the gate electrode 10 and the drain extension region 7, the electric field distribution in the drain extension region 7 is improved, thereby reducing the feedback capacitance, which is beneficial for the RF performance.
  • the drain contact region 6 is used to electrically connect the drain region 5 to a first metal layer 21 and a top metal layer 23 via, respectively, a drain contact 20 and a first inter-metal contact 22.
  • the distance between the top metal layer 21 and the drain extension region 7 is, in this example, 2 ⁇ m. It appeared that the performance of the LDMOS transistor 99, such as the source to drain breakdown voltage and the output capacitance, was negatively influenced when the top metal layer 21 extended over the drain extension region 7. Therefore, both the first metal layer 21 and the top metal layer 23 do not extend over the drain extension region 7 in order to prevent any negative influence of the metal layers on the performance of the LDMOS transistor 99.
  • the top metal layer 23 has dimensions, for example the width and thickness, that are large enough to enable the top metal layer 23 to withstand a high current level without suffering from electromigration. Furthermore, the material of the top metal layer 23 comprises Au, which material is able to withstand a higher current level than other, more conventional, materials, such as Al and Cu, without suffering from electromigration.
  • the area of the drain contact region 6 is relatively large, because the top metal layer 23 has a large width and is not allowed to extend over the drain extension region 7. The large area of the drain contact region 6 allows for applying a multiple of drain and first inter-metal contacts 20, 22.
  • Fig. 2 depicts a cross-sectional view of a first embodiment of an LDMOS transistor 1 according to the invention.
  • the LDMOS transistor 1 similar to the LDMOS transistor 99 of the prior art, comprises the substrate 2, the substrate contact region 11, the epitaxial layer 12, the gate electrode 10, the shield layer 31, the insulation region 14, the gate oxide layer 18, the channel region 4, the source region 3 and the drain region 5, which comprises the drain contact region 6 and the drain extension region 7.
  • the top metal layer 23 of the LDMOS transistor 1 according to the invention extends over the drain extension region 7 with a distance 723, in this example, of 5 ⁇ m between the drain contact region 7 and the top metal layer 23.
  • the top metal layer comprises a mixture of Al and Cu, which is a more common material used in IC technologies. Because this material cannot withstand the same high current level as Au, which material was applied in the LDMOS transistor 99 of the prior art, the top metal layer 23 has a larger width than the top metal layer of the LDMOS transistor 99 of the prior art to enable the top metal layer 23 to withstand the same high current level as the prior art without suffering from electromigration.
  • the drain contact region 6 is electrically connected to the top metal layer through the drain contact 20, the first metal layer 21, the first inter-metal contact 22, a second metal layer 24, a second inter-metal contact 25, a third metal layer 26 and a third inter-metal contact 27.
  • This stack of metal layers and inter-metal contacts creates a distance 723 between the top metal layer 23 and the drain extension region 7 that is large enough to allow the top metal layer 23 to extend over the drain extension region 7 without influencing the performance of the LDMOS transistor.
  • the extra metal layers give an extra degree of freedom for designing a less area-consuming interconnection scheme of the LDMOS transistors and other devices on the IC.
  • the drain contact region 6 is electrically connected to the first metal layer 21 with one drain contact 20, which allows a substantive reduction of the area of the drain contact region 6. This area is then defined by the size of the drain contact 20 and the lithographic capabilities of the applied technology. The reduced area of the drain contact region 6 improves the RF power output efficiency of the LDMOS transistor 1, because of a reduction of the output capacitance.
  • Fig. 3 depicts a cross-sectional view of a second embodiment of the LDMOS transistor 1 according to the invention.
  • the source region 3 and the substrate contact region 11 are electrically connected through a suicide layer 32, which is thinner than the first metal layer 21 and which reduces the capacitive coupling between the source region 3 and the drain region 5.
  • the output capacitance is reduced with a corresponding further increase of the RF power output efficiency of the LDMOS transistor 1.
  • Fig. 4 depicts a cross-sectional view of a third embodiment of the LDMOS transistor 1 according to the invention in which the drain contact region 6 of the LDMOS transistor 1 is common with the drain contact region 6 of a second LDMOS transistor 91, which second LDMOS transistor 91 is mirror-symmetrical with respect to the LDMOS transistor 1 along the axis A-A'. Furthermore, two LDMOS transistors 1 and 91 now share the advantage of the reduced area of the drain contact region 6. This way the area occupied by the LDMOS transistor 1 and the second LDMOS transistor 91 is even smaller than the case when the LDMOS transistor 1 and the LDMOS transistor 91 each would have their own separate drain contact region 6.
  • Results of measurements performed on the LDMOS transistor 1 show an increase of the RF power output efficiency of around 4 percent point, depending on the measurement conditions, compared to the LDMOS transistor 99 of the prior art. Furthermore, it is shown that the output capacitance is decreased by around 15%, depending on the measurement conditions, compared to the LDMOS transistor 99 of the prior art.
  • the LDMOS transistor of the invention comprises a substrate, a gate electrode, a substrate contact region, a source region, a channel region and a drain region, which drain region comprises a drain contact region and a drain extension region.
  • the drain contact region is electrically connected to a top metal layer, which extends over the drain extension region, with a distance between the top metal layer and the drain extension region that is larger than 2 ⁇ m. This way the area of the drain contact region may be reduced and the RF power output efficiency of the LDMOS transistor increased.
  • the source region is electrically connected to the substrate contact region via a suicide layer instead of a first metal layer, thereby reducing the capacitive coupling between the source region and the drain region and hence increasing the RF power output efficiency of the LDMOS transistor further.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and a drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2μm. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.

Description

LDMOS transistor
This invention relates to an LDMOS transistor.
In base stations for personal communications systems (GSM, EDGE, W- CDMA), RF power amplifiers are the key components. For these power amplifiers, RF
Laterally Diffused Metal Oxide Semiconductor, generally abbreviated as LDMOS, transistors are now the preferred choice of technology, because of their excellent high power capabilities, gain and linearity. To be able to meet the demands imposed by new communication standards, the performance of the LDMOS transistors with constantly shrinking dimensions is subject to continuous improvements.
In WO 2005/022645 an LDMOS transistor is disclosed, which comprises a source and a drain region in a semiconductor substrate, in which the source and the drain region are mutually connected through a channel region. The source region and the substrate are electrically connected through a first metal layer. The LDMOS transistor further comprises a gate electrode on the semiconductor substrate for influencing an electron distribution in the channel region. The drain region comprises a drain contact region and a drain extension region extending from the drain contact region towards the channel region. The drain contact region is electrically connected via a drain contact to a top metal layer, which extends only over the drain contact region and does not extend over the drain extension region. This way it is prevented that the top metal layer negatively influences the depletion of the drain extension region, because the series resistance of the drain extension region would become more voltage dependent if the top metal layer would extend over the drain extension region thereby reducing the performance of the LDMOS transistor. Furthermore, the top metal layer needs to have a high current capability, which results in a wide and thick top metal layer to be able to withstand a high current level without suffering from electromigration. Because the top metal layer is allowed to extend only over the drain contact region and because the top metal layer is wide enough to be able to withstand a high current level, the drain contact region occupies a relatively large area, which disadvantageously increases the total area occupied by the LDMOS transistor. Another disadvantage is that the relatively large area of the drain contact region results in a relatively large output capacitance of the LDMOS transistor. The output capacitance of the LDMOS transistor is, amongst others, determined by the capacitive coupling between the source region and the drain region, and comprises the drain extension region to source region capacitance and the drain contact region to source region capacitance. At a typical drain bias condition of 28V the drain extension region is almost completely depleted and hence the output capacitance of the LDMOS transistor is, at this typical bias condition, mainly determined by the drain contact region to source region capacitance. The relatively large output capacitance disadvantageously decreases the RF power output efficiency of the LDMOS transistor, which is defined as the RF output power divided by the DC input power of the LDMOS transistor.
It is an object of the invention to provide an LDMOS transistor with an improved RF power output efficiency. According to the invention, this object is achieved by providing an LDMOS transistor as claimed in claim 1.
The LDMOS transistor according to the invention comprises a source region and a drain region, both of a second semiconductor type, in a semiconductor substrate of a first semiconductor type, that are mutually connected through a channel region of the first semiconductor type. A gate electrode extends over the channel region and is able to influence an electron distribution in the channel region. The drain region comprises a drain contact region and a drain extension region, which drain extension region is adjacent to the channel region. The LDMOS transistor according to the invention further comprises a top metal layer which is electrically connected to the drain contact region through a drain contact and which extends over the drain extension region with a distance between the top metal layer and the drain extension region that is substantially larger than 2μm. The invention is based on the insight that if the distance between the top metal layer and the drain extension region is such that the top metal layer hardly influences the depletion of the drain extension region, it becomes possible to allow the top metal layer to extend over the drain extension region without affecting the performance of the LDMOS transistor. Thereby it becomes possible to give the top layer any size needed to obtain the desired current capability, without a need to have an equally large size for the drain contact region. Furthermore, the area of the drain contact region and hence the output capacitance of the LDMOS transistor may be reduced in comparison with the prior art, because the area of the drain contact region does not need to be as large as the size of the top metal layer. The reduced output capacitance beneficially increases the RF power output efficiency of the LDMOS transistor.
Another advantage is that the reduction of the area of the drain contact region enables a reduction of the total area occupied by the LDMOS transistor. Further, the distance between the top metal layer and the drain contact region is such that the top metal layer does not affect the feedback capacitance. The feedback capacitance is the capacitance between the drain region and the gate electrode. A shorter distance between the top metal layer and the drain contact region would increase the feedback capacitance thereby reducing the RF performance of the LDMOS transistor. Further, the distance between the top metal layer and the drain extension region is such that the drain to source breakdown voltage of the LDMOS transistor at zero gate voltage (B Vdss) is not affected by the top metal layer. A shorter distance between the top metal layer and the drain contact region would disadvantageously decrease the drain to source breakdown voltage of the LDMOS transistor. In a first embodiment of the LDMOS transistor according to the invention, the distance between the top metal layer and the drain extension region is 5μm. At this distance the influence of the top metal layer on the performance of the LDMOS transistor appeared to be sufficiently small.
In a second embodiment of the LDMOS transistor according to the invention, the electrical connection to the drain contact region via the drain contact further comprises at least one intermediate metal layer and at least one inter-metal contact between the intermediate metal layer and the top metal layer. The introduction of the at least one intermediate layer beneficially increases the distance between the top metal layer and the drain extension region and advantageously introduces a degree of freedom for the interconnection scheme of the LDMOS transistors and other devices on the IC (Integrated Circuit).
In a third embodiment of the LDMOS transistor according to the invention, the top metal layer comprises a mixture of Al and Cu. The fact that the dimensions of the top metal layer are not bound by the area of the drain contact region, allows for the use of a more common and cheaper metal material, as compared to Au. Because the mixture of Al and Cu material cannot withstand the same high current level as Au, the top metal layer has a larger width than the top metal layer of the prior art to enable the top metal layer to withstand the same high current level as the prior art without suffering from electromigration. In a fourth embodiment of the LDMOS transistor according to the invention, the drain contact region of a first LDMOS transistor is common with the drain contact region of a second LDMOS transistor, which second LDMOS transistor is mirror-symmetrical with respect to the first LDMOS transistor. In this embodiment the advantage of the reduced area of the drain contact region is now shared by two LDMOS transistors, which will reduce the total area occupied by LDMOS transistors on the IC even further.
In a fifth embodiment the LDMOS transistor comprises a substrate contact region of the first semiconductor type, which adjoins the source region in which the substrate contact region and the source region are electrically connected via a suicide layer. The suicide layer is thinner than the first metal layer, which is used in the prior art to electrically connect the substrate contact region and the source region, thereby further reducing the feedback capacitance and hence further increasing the RF power output efficiency of the LDMOS transistor, because the dimensions of the suicide layer are smaller than those of the standard metal layer. In a sixth embodiment the LDMOS transistor comprises a shield layer between the gate electrode and the drain contact region, wherein the shield layer extends over a part of the drain extension region. The introduction of the shield layer reduces the feedback capacitance between the gate electrode and the drain region, which is beneficial for the RF performance of the LDMOS transistor.
These and other aspects of the invention will be further elucidated and described with reference to the drawings, in which:
Fig. 1 shows a diagrammatical cross-sectional view of an LDMOS transistor according to the prior art;
Fig. 2 shows a diagrammatical cross-sectional view of an LDMOS transistor according to an embodiment of the invention;
Fig. 3 shows a diagrammatical cross-sectional view of an LDMOS transistor according to a second embodiment of the invention; and Fig. 4 shows a diagrammatical cross-sectional view of an LDMOS transistor according to a third embodiment of the invention.
The Figures are not drawn to scale. In general, identical components are denoted by the same reference numerals in the Figures. Fig. 1 depicts a cross-sectional view of a conventional LDMOS transistor 99 according to the prior art, comprising a substrate 2 of a semiconductor material, in this case p-type silicon, on which a p-type epitaxial layer 12 is formed. The LDMOS transistor 99 further comprises an n-type source region 3, an n-type drain region 5 and a poly silicon gate electrode 10, which may optionally be provided with a suicide layer and which extends over a channel region 4, which is in this example a laterally diffused p-type region. The source region 3 and the drain region 5 are mutually connected through the channel region 4. A p- type substrate contact region 11 electrically connects to the substrate 2 and adjoins the source region 3 on a side opposite to the side, which adjoins the channel region 4. The channel region 4, the substrate contact region 11, the source region 3 and the drain region 5 are provided in the epitaxial layer 12. The gate electrode 10 is separated from the substrate 2 by a gate oxide layer 18, which for example comprises thermally grown silicon dioxide. The source region 3 is electrically connected to the substrate contact region 11 through a source contact 41, a first metal layer 21 and a substrate contact 40. Hence the source region 3 is, via the substrate contact region 11, electrically connected to the bottom surface of the substrate 2.
The drain region 5 comprises an n-type drain extension region 7, which accommodates the high voltage operation of the LDMOS transistor 99, and an n-type drain contact region 6. The drain extension region 7 has a lower doping level than the drain contact region 6 and is optimized for a maximum output power of the LDMOS transistor 99. It should be noted that the drain extension region 7 may also comprise multiple different-type doping levels, which improves the lifetime of the device.
The LDMOS transistor 99 further comprises a shield layer 31, which serves as a dummy gate electrode and improves the feedback capacitance. The shield layer 31 in this case extends over a portion of the gate electrode 10 and the drain extension region 7 and is separated from the gate electrode 10 by an insulation layer 14, which for example comprises a plasma oxide. The shield layer 31 is separated from the epitaxial layer 12, and hence the drain extension region 7, by the gate oxide layer 18 and the insulation layer 14. Due to the close proximity of the shield layer 31 to the gate electrode 10 and the drain extension region 7, the electric field distribution in the drain extension region 7 is improved, thereby reducing the feedback capacitance, which is beneficial for the RF performance.
The drain contact region 6 is used to electrically connect the drain region 5 to a first metal layer 21 and a top metal layer 23 via, respectively, a drain contact 20 and a first inter-metal contact 22. The distance between the top metal layer 21 and the drain extension region 7 is, in this example, 2μm. It appeared that the performance of the LDMOS transistor 99, such as the source to drain breakdown voltage and the output capacitance, was negatively influenced when the top metal layer 21 extended over the drain extension region 7. Therefore, both the first metal layer 21 and the top metal layer 23 do not extend over the drain extension region 7 in order to prevent any negative influence of the metal layers on the performance of the LDMOS transistor 99. The top metal layer 23 has dimensions, for example the width and thickness, that are large enough to enable the top metal layer 23 to withstand a high current level without suffering from electromigration. Furthermore, the material of the top metal layer 23 comprises Au, which material is able to withstand a higher current level than other, more conventional, materials, such as Al and Cu, without suffering from electromigration. The area of the drain contact region 6 is relatively large, because the top metal layer 23 has a large width and is not allowed to extend over the drain extension region 7. The large area of the drain contact region 6 allows for applying a multiple of drain and first inter-metal contacts 20, 22. Fig. 2 depicts a cross-sectional view of a first embodiment of an LDMOS transistor 1 according to the invention. The LDMOS transistor 1, similar to the LDMOS transistor 99 of the prior art, comprises the substrate 2, the substrate contact region 11, the epitaxial layer 12, the gate electrode 10, the shield layer 31, the insulation region 14, the gate oxide layer 18, the channel region 4, the source region 3 and the drain region 5, which comprises the drain contact region 6 and the drain extension region 7.
The main difference with the LDMOS transistor 99 of the prior art is that the top metal layer 23 of the LDMOS transistor 1 according to the invention extends over the drain extension region 7 with a distance 723, in this example, of 5μm between the drain contact region 7 and the top metal layer 23. Another difference is that the top metal layer comprises a mixture of Al and Cu, which is a more common material used in IC technologies. Because this material cannot withstand the same high current level as Au, which material was applied in the LDMOS transistor 99 of the prior art, the top metal layer 23 has a larger width than the top metal layer of the LDMOS transistor 99 of the prior art to enable the top metal layer 23 to withstand the same high current level as the prior art without suffering from electromigration. Yet another difference with the LDMOS transistor 99 of the prior art is that in this case the drain contact region 6 is electrically connected to the top metal layer through the drain contact 20, the first metal layer 21, the first inter-metal contact 22, a second metal layer 24, a second inter-metal contact 25, a third metal layer 26 and a third inter-metal contact 27. This stack of metal layers and inter-metal contacts creates a distance 723 between the top metal layer 23 and the drain extension region 7 that is large enough to allow the top metal layer 23 to extend over the drain extension region 7 without influencing the performance of the LDMOS transistor. Furthermore the extra metal layers give an extra degree of freedom for designing a less area-consuming interconnection scheme of the LDMOS transistors and other devices on the IC.
The drain contact region 6 is electrically connected to the first metal layer 21 with one drain contact 20, which allows a substantive reduction of the area of the drain contact region 6. This area is then defined by the size of the drain contact 20 and the lithographic capabilities of the applied technology. The reduced area of the drain contact region 6 improves the RF power output efficiency of the LDMOS transistor 1, because of a reduction of the output capacitance.
Fig. 3 depicts a cross-sectional view of a second embodiment of the LDMOS transistor 1 according to the invention. In this embodiment the source region 3 and the substrate contact region 11 are electrically connected through a suicide layer 32, which is thinner than the first metal layer 21 and which reduces the capacitive coupling between the source region 3 and the drain region 5. Hence the output capacitance is reduced with a corresponding further increase of the RF power output efficiency of the LDMOS transistor 1.
Fig. 4 depicts a cross-sectional view of a third embodiment of the LDMOS transistor 1 according to the invention in which the drain contact region 6 of the LDMOS transistor 1 is common with the drain contact region 6 of a second LDMOS transistor 91, which second LDMOS transistor 91 is mirror-symmetrical with respect to the LDMOS transistor 1 along the axis A-A'. Furthermore, two LDMOS transistors 1 and 91 now share the advantage of the reduced area of the drain contact region 6. This way the area occupied by the LDMOS transistor 1 and the second LDMOS transistor 91 is even smaller than the case when the LDMOS transistor 1 and the LDMOS transistor 91 each would have their own separate drain contact region 6.
Results of measurements performed on the LDMOS transistor 1 show an increase of the RF power output efficiency of around 4 percent point, depending on the measurement conditions, compared to the LDMOS transistor 99 of the prior art. Furthermore, it is shown that the output capacitance is decreased by around 15%, depending on the measurement conditions, compared to the LDMOS transistor 99 of the prior art.
In summary, the LDMOS transistor of the invention comprises a substrate, a gate electrode, a substrate contact region, a source region, a channel region and a drain region, which drain region comprises a drain contact region and a drain extension region. The drain contact region is electrically connected to a top metal layer, which extends over the drain extension region, with a distance between the top metal layer and the drain extension region that is larger than 2μm. This way the area of the drain contact region may be reduced and the RF power output efficiency of the LDMOS transistor increased. In another embodiment the source region is electrically connected to the substrate contact region via a suicide layer instead of a first metal layer, thereby reducing the capacitive coupling between the source region and the drain region and hence increasing the RF power output efficiency of the LDMOS transistor further.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Claims

CLAIMS:
1. An LDMOS transistor (1) provided in a semiconductor substrate (2) of a first semiconductor type, the LDMOS transistor (1) comprising a source region (3) and a drain region (5) both of a second semiconductor type and being mutually connected through a channel region (4) over which a gate electrode (10) extends, the drain region (5) comprising a drain contact region (6) and a drain extension region (7) extending from the channel region (4) towards the drain contact region (6), wherein the drain contact region (6) is electrically connected to a top metal layer (23) via a drain contact (20), characterized in that the top metal layer (23) extends over at least a part of the drain extension region (7) with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2μm.
2. An LDMOS transistor (1) as claimed in claim 1 wherein the distance (723) between the top metal layer (23) and the drain extension region (7) is 5μm.
3. An LDMOS transistor (1) as claimed in claim 1 wherein the drain contact (20) and the top metal layer (23) are electrically connected through at least one intermediate metal layer (21, 24, 26) and at least one inter-metal contact (22, 25, 27).
4. An LDMOS transistor (1) as claimed in claim 1 wherein the top metal layer (23) comprises a mixture of Al and Cu.
5. An LDMOS transistor (1) as claimed in claim 1 wherein the drain contact region (6) is electrically connected to the top metal layer (23) with one drain contact (20).
6. An LDMOS transistor (1) as claimed in claim 1 wherein the drain contact region (6) of the LDMOS transistor (1) is common with the drain contact region (6) of a second LDMOS transistor (91), which second LDMOS transistor (91) is mirror-symmetrical with respect to the LDMOS transistor (1).
7. An LDMOS transistor (1) as claimed in claim 1 wherein the LDMOS transistor (1) further comprises a substrate contact region (11) of the first semiconductor type, which adjoins the source region (3) at a side opposite to the side that adjoins the channel region (4), and in which the substrate contact region (11) and the source region (3) are electrically connected via a suicide layer (32).
8. An LDMOS transistor (1) as claimed in any of the preceding claims further comprising a shield layer (11) between the gate electrode (10) and the drain contact region (6), the shield layer (11) covering a part of the drain extension region (7).
PCT/IB2006/052644 2005-08-10 2006-08-02 Ldmos transistor WO2007017803A2 (en)

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JP2008525687A JP2009505391A (en) 2005-08-10 2006-08-02 LDMOS transistor
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009144616A1 (en) * 2008-05-26 2009-12-03 Nxp B.V. Ldmos transistor
WO2009144617A1 (en) * 2008-05-26 2009-12-03 Nxp B.V. Ldmos transistor
WO2010010506A1 (en) 2008-07-22 2010-01-28 Nxp B.V. Ldmos having a field plate
WO2010016008A1 (en) * 2008-08-05 2010-02-11 Nxp B.V. Ldmos with discontinuous metal stack fingers
EP3288074B1 (en) * 2016-03-15 2021-10-27 NXP USA, Inc. Transistor with shield structure, packaged device, and method of manufacture

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7859336B2 (en) * 2007-03-13 2010-12-28 Astec International Limited Power supply providing ultrafast modulation of output voltage
US7994761B2 (en) * 2007-10-08 2011-08-09 Astec International Limited Linear regulator with RF transistors and a bias adjustment circuit
JP5487852B2 (en) * 2008-09-30 2014-05-14 サンケン電気株式会社 Semiconductor device
US8698240B2 (en) * 2010-05-25 2014-04-15 Macronix International Co., Ltd. Double diffused drain metal-oxide-simiconductor devices with floating poly thereon and methods of manufacturing the same
JP5712579B2 (en) * 2010-11-30 2015-05-07 富士通セミコンダクター株式会社 Semiconductor device
CN102569381A (en) * 2010-12-07 2012-07-11 上海华虹Nec电子有限公司 LDMOS structure with shield grid and preparation method thereof
CN102723329A (en) * 2012-07-13 2012-10-10 上海先进半导体制造股份有限公司 High-density submicro high-voltage binary-coded decimal (BCD) semiconductor device and manufacturing method thereof
CN103855210A (en) * 2012-12-03 2014-06-11 上海华虹宏力半导体制造有限公司 Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof
CN103871881B (en) * 2012-12-14 2017-04-05 上海华虹宏力半导体制造有限公司 The groove and preparation method of p-type LDMOS device
US9041127B2 (en) 2013-05-14 2015-05-26 International Business Machines Corporation FinFET device technology with LDMOS structures for high voltage operations
CN104465772A (en) * 2014-11-10 2015-03-25 上海华虹宏力半导体制造有限公司 High-efficiency radio frequency LDMOS device and manufacturing method thereof
US9281379B1 (en) 2014-11-19 2016-03-08 International Business Machines Corporation Gate-all-around fin device
US10205024B2 (en) * 2016-02-05 2019-02-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having field plate and associated fabricating method
TWI597847B (en) * 2016-09-05 2017-09-01 新唐科技股份有限公司 High voltage semiconductor device
CN106960879B (en) * 2017-05-23 2020-09-15 上海华虹宏力半导体制造有限公司 MOSFET structure for improving radio frequency switch characteristic
US20200144381A1 (en) * 2018-11-07 2020-05-07 Monolithic Power Systems, Inc. Ldmos device with a drain contact structure with reduced size
US11003498B1 (en) 2020-08-10 2021-05-11 Coupang Corp. Computerized systems and methods for fail-safe loading of information on a user interface using a circuit breaker

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757362A (en) * 1980-05-30 1988-07-12 Sharp Kabushiki Kaisha High voltage MOS transistor
US20010012671A1 (en) * 1999-09-21 2001-08-09 Yutaka Hoshino Semiconductor device and a method of manufacturing the same
WO2005022645A2 (en) * 2003-08-27 2005-03-10 Koninklijke Philips Electronics N.V. Electronic device comprising an ldmos transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2616966B1 (en) * 1987-06-22 1989-10-27 Thomson Semiconducteurs STRUCTURE OF POWER MOS TRANSISTORS
JPH09120995A (en) * 1995-08-22 1997-05-06 Mitsubishi Electric Corp Semiconductor device and its manufacture
US5841166A (en) * 1996-09-10 1998-11-24 Spectrian, Inc. Lateral DMOS transistor for RF/microwave applications
JP2002270830A (en) * 2001-03-12 2002-09-20 Fuji Electric Co Ltd Semiconductor device
EP1435648A1 (en) * 2002-12-30 2004-07-07 STMicroelectronics S.r.l. Process of making CMOS and drain extension MOS transistors with silicided gate
US7109562B2 (en) * 2005-02-07 2006-09-19 Leadtrend Technology Corp. High voltage laterally double-diffused metal oxide semiconductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757362A (en) * 1980-05-30 1988-07-12 Sharp Kabushiki Kaisha High voltage MOS transistor
US20010012671A1 (en) * 1999-09-21 2001-08-09 Yutaka Hoshino Semiconductor device and a method of manufacturing the same
WO2005022645A2 (en) * 2003-08-27 2005-03-10 Koninklijke Philips Electronics N.V. Electronic device comprising an ldmos transistor

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CONTIERO C ET AL: "Progress in power ICs and MEMS, analog technologies to interface the real world" PROCEEDINGS OF THE 16TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD '04), KITAKYUSHU, JP, MAY 24-27, 2004, 24 May 2004 (2004-05-24), - 27 May 2004 (2004-05-27) pages 3-12, XP010723316 IEEE, PISCATAWAY, NJ, USA ISBN: 4-88686-060-5 *
FUJISHIMA N ET AL: "A 700V lateral power MOSFET with narrow gap double metal field plates realizing low on-resistance and long-term stability of performance" PROCEEDINGS OF THE 13TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS (ISPSD'01), OSAKA, JP, JUNE 4-7, 2001, 4 June 2001 (2001-06-04), - 7 June 2001 (2001-06-07) pages 255-258, XP010551614 IEEE, PISCATAWAY, NJ, USA ISBN: 4-88686-056-7 *
MOSCATELLI A ET AL: "LDMOS implementation in a 0.35 mum BCD technology (BCD6)" PROCEEDINGS OF THE 12TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD 2000). TOULOUSE, FR, MAY 22-25, 2000, 22 May 2000 (2000-05-22), - 25 May 2000 (2000-05-25) pages 323-326, XP000987879 IEEE, PISCATAWAY, NJ, USA ISBN: 0-7803-6269-1 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009144616A1 (en) * 2008-05-26 2009-12-03 Nxp B.V. Ldmos transistor
WO2009144617A1 (en) * 2008-05-26 2009-12-03 Nxp B.V. Ldmos transistor
WO2010010506A1 (en) 2008-07-22 2010-01-28 Nxp B.V. Ldmos having a field plate
CN102099920A (en) * 2008-07-22 2011-06-15 Nxp股份有限公司 LDMOS having a field plate
US8450802B2 (en) 2008-07-22 2013-05-28 Nxp B.V. LDMOS having a field plate
WO2010016008A1 (en) * 2008-08-05 2010-02-11 Nxp B.V. Ldmos with discontinuous metal stack fingers
EP3288074B1 (en) * 2016-03-15 2021-10-27 NXP USA, Inc. Transistor with shield structure, packaged device, and method of manufacture

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US20080237705A1 (en) 2008-10-02
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WO2007017803A3 (en) 2007-10-18

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