WO2007015925A1 - Elimination des verrous au moyen de l'execution transactionnelle de sections critiques - Google Patents

Elimination des verrous au moyen de l'execution transactionnelle de sections critiques Download PDF

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Publication number
WO2007015925A1
WO2007015925A1 PCT/US2006/028152 US2006028152W WO2007015925A1 WO 2007015925 A1 WO2007015925 A1 WO 2007015925A1 US 2006028152 W US2006028152 W US 2006028152W WO 2007015925 A1 WO2007015925 A1 WO 2007015925A1
Authority
WO
WIPO (PCT)
Prior art keywords
critical section
transactional execution
program
critical
transactionally
Prior art date
Application number
PCT/US2006/028152
Other languages
English (en)
Inventor
Mark S. Moir
Marc Tremblay
Shailender Chaudhry
Original Assignee
Sun Microsystems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/195,093 external-priority patent/US7398355B1/en
Application filed by Sun Microsystems, Inc. filed Critical Sun Microsystems, Inc.
Priority to JP2008524994A priority Critical patent/JP2009508187A/ja
Priority to EP06787947A priority patent/EP1913473A1/fr
Publication of WO2007015925A1 publication Critical patent/WO2007015925A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G06F9/528—Mutual exclusion algorithms by using speculative mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/52—Binary to binary

Definitions

  • attempting to re-execute the critical section involves attempting to transactionally re-execute the critical section.
  • the program is modified so that if the critical section is not successfully completed after one or more attempts at transactional execution, the program: acquires a lock associated with the critical section; non- transactionally executes the critical section; and releases the lock associated with the critical section.
  • FIG. 2A illustrates how a critical section is executed in accordance with an embodiment of the present invention. ⁇ .
  • Processor 101 additionally includes a level one (Ll) data cache 115, which stores data items that are likely to be used by processor 101.
  • Ll data cache 115 includes load-marking bits 116, which indicate that a data value from the line has been loaded during transactional execution. These load-marking bits 116 are used to determine whether any interfering memory references take place during transactional execution as is described below with reference to FIGs. 3-8.
  • Processor 101 also includes an Ll instruction cache (not shown).
  • Ll instruction cache in processor 101, and with Ll data cache 117 (and a corresponding Ll instruction cache) in processor 102.
  • L2 cache 120 is associated with a coherency mechanism 122, such as the reverse directory structure described in U.S. Patent Application No. 10/186,118, entitled, "Method and Apparatus for Facilitating Speculative Loads in a Multiprocessor System," filed on June 26, 2002, by inventors Shailender Chaudhry and Marc Tremblay (Publication No. US-2002-0199066-A1).
  • This coherency mechanism 122 maintains "copyback inforavation" 121 for each cache line.
  • FIG. 6 presents a flow chart illustrating how store-marking is performed during transactional execution in accordance with an embodiment of the present invention.
  • the system performs a store operation. If this store operation has been identified as a store operation that needs to be store-marked, the system first prefetches a corresponding cache line for exclusive use (step 602). Note that this prefetch operation will do nothing if the line is already located in cache and is already in an exclusive use state.
  • Ll data cache 115 is a write-through cache
  • the store operation propagates through Ll data cache 115 to L2 cache 120. The system then attempts to lock the cache line corresponding to the store operation in L2 data cache 115 (step 604).

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

La présente invention concerne un système qui élimine les verrous par l'exécution transactionnelle de sections critiques. Le système reçoit un programme qui comprend des sections critiques protégées par des verrous. Le système modifie le programme de sorte que les sections critiques soit exécutées au moyen de transactions sans l'aide de verrous. Le programme est modifié de sorte que: (1) pendant l'exécution transactionnelle d'une section critique, le programme détermine si un verrou associé à la section critique est maintenu par un autre processus et si c'est le cas, abandonne l'exécution transactionnelle; (2) si l'exécution transactionnelle s'achève sans rencontrer un accès de données interférant provenant d'un autre processus, le programme stocke les modifications effectuées pendant l'exécution transactionnelle et reprend éventuellement l'exécution non transactionnelle normale du programme après la section critique; (3) si un accès de données interférant provenant d'un autre processus est rencontré pendant l'exécution transactionnelle, le programme rejette les changements effectués pendant l'exécution transactionnelle et tente de procéder à la réexécution de la section critique.
PCT/US2006/028152 2005-08-01 2006-07-21 Elimination des verrous au moyen de l'execution transactionnelle de sections critiques WO2007015925A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008524994A JP2009508187A (ja) 2005-08-01 2006-07-21 クリティカルセクションをトランザクション的に実行することによるロックの回避
EP06787947A EP1913473A1 (fr) 2005-08-01 2006-07-21 Elimination des verrous au moyen de l'execution transactionnelle de sections critiques

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/195,093 US7398355B1 (en) 2003-02-13 2005-08-01 Avoiding locks by transactionally executing critical sections
US11/195,093 2005-08-01

Publications (1)

Publication Number Publication Date
WO2007015925A1 true WO2007015925A1 (fr) 2007-02-08

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PCT/US2006/028152 WO2007015925A1 (fr) 2005-08-01 2006-07-21 Elimination des verrous au moyen de l'execution transactionnelle de sections critiques

Country Status (3)

Country Link
EP (1) EP1913473A1 (fr)
JP (1) JP2009508187A (fr)
WO (1) WO2007015925A1 (fr)

Cited By (14)

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JP2012514254A (ja) * 2008-12-30 2012-06-21 インテル・コーポレーション トランザクショナルメモリシステム内でのハードウェア属性のメモリモデル
US9740521B2 (en) 2012-06-15 2017-08-22 International Business Machines Corporation Constrained transaction execution
US9740549B2 (en) 2012-06-15 2017-08-22 International Business Machines Corporation Facilitating transaction completion subsequent to repeated aborts of the transaction
US9766925B2 (en) 2012-06-15 2017-09-19 International Business Machines Corporation Transactional processing
US9772854B2 (en) 2012-06-15 2017-09-26 International Business Machines Corporation Selectively controlling instruction execution in transactional processing
CN107239415A (zh) * 2016-03-28 2017-10-10 华为技术有限公司 一种执行临界区操作的方法及装置
US9792125B2 (en) 2012-06-15 2017-10-17 International Business Machines Corporation Saving/restoring selected registers in transactional processing
US9851978B2 (en) 2012-06-15 2017-12-26 International Business Machines Corporation Restricted instructions in transactional execution
US9940138B2 (en) 2009-04-08 2018-04-10 Intel Corporation Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations
US9983883B2 (en) 2012-06-15 2018-05-29 International Business Machines Corporation Transaction abort instruction specifying a reason for abort
US10185588B2 (en) 2012-06-15 2019-01-22 International Business Machines Corporation Transaction begin/end instructions
US10223214B2 (en) 2012-06-15 2019-03-05 International Business Machines Corporation Randomized testing within transactional execution
US10430199B2 (en) 2012-06-15 2019-10-01 International Business Machines Corporation Program interruption filtering in transactional execution
US10599435B2 (en) 2012-06-15 2020-03-24 International Business Machines Corporation Nontransactional store instruction

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JP5088754B2 (ja) 2009-12-18 2012-12-05 インターナショナル・ビジネス・マシーンズ・コーポレーション システム、方法、プログラムおよびコード生成装置
US20120079245A1 (en) * 2010-09-25 2012-03-29 Cheng Wang Dynamic optimization for conditional commit
US20150277914A1 (en) * 2014-03-27 2015-10-01 John H. Kelm Lock elision with binary translation based processors

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US20040187123A1 (en) * 2003-02-13 2004-09-23 Marc Tremblay Selectively unmarking load-marked cache lines during transactional program execution

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US20040187123A1 (en) * 2003-02-13 2004-09-23 Marc Tremblay Selectively unmarking load-marked cache lines during transactional program execution

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Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012514254A (ja) * 2008-12-30 2012-06-21 インテル・コーポレーション トランザクショナルメモリシステム内でのハードウェア属性のメモリモデル
US9940138B2 (en) 2009-04-08 2018-04-10 Intel Corporation Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations
US9983883B2 (en) 2012-06-15 2018-05-29 International Business Machines Corporation Transaction abort instruction specifying a reason for abort
US9792125B2 (en) 2012-06-15 2017-10-17 International Business Machines Corporation Saving/restoring selected registers in transactional processing
US9996360B2 (en) 2012-06-15 2018-06-12 International Business Machines Corporation Transaction abort instruction specifying a reason for abort
US11080087B2 (en) 2012-06-15 2021-08-03 International Business Machines Corporation Transaction begin/end instructions
US10185588B2 (en) 2012-06-15 2019-01-22 International Business Machines Corporation Transaction begin/end instructions
US9851978B2 (en) 2012-06-15 2017-12-26 International Business Machines Corporation Restricted instructions in transactional execution
US9858082B2 (en) 2012-06-15 2018-01-02 International Business Machines Corporation Restricted instructions in transactional execution
US10223214B2 (en) 2012-06-15 2019-03-05 International Business Machines Corporation Randomized testing within transactional execution
US9983915B2 (en) 2012-06-15 2018-05-29 International Business Machines Corporation Facilitating transaction completion subsequent to repeated aborts of the transaction
US9983881B2 (en) 2012-06-15 2018-05-29 International Business Machines Corporation Selectively controlling instruction execution in transactional processing
US9740521B2 (en) 2012-06-15 2017-08-22 International Business Machines Corporation Constrained transaction execution
US9983882B2 (en) 2012-06-15 2018-05-29 International Business Machines Corporation Selectively controlling instruction execution in transactional processing
US9772854B2 (en) 2012-06-15 2017-09-26 International Business Machines Corporation Selectively controlling instruction execution in transactional processing
US9766925B2 (en) 2012-06-15 2017-09-19 International Business Machines Corporation Transactional processing
US9740549B2 (en) 2012-06-15 2017-08-22 International Business Machines Corporation Facilitating transaction completion subsequent to repeated aborts of the transaction
US10353759B2 (en) 2012-06-15 2019-07-16 International Business Machines Corporation Facilitating transaction completion subsequent to repeated aborts of the transaction
US10430199B2 (en) 2012-06-15 2019-10-01 International Business Machines Corporation Program interruption filtering in transactional execution
US10437602B2 (en) 2012-06-15 2019-10-08 International Business Machines Corporation Program interruption filtering in transactional execution
US10558465B2 (en) 2012-06-15 2020-02-11 International Business Machines Corporation Restricted instructions in transactional execution
US10719415B2 (en) 2012-06-15 2020-07-21 International Business Machines Corporation Randomized testing within transactional execution
US10599435B2 (en) 2012-06-15 2020-03-24 International Business Machines Corporation Nontransactional store instruction
US10606597B2 (en) 2012-06-15 2020-03-31 International Business Machines Corporation Nontransactional store instruction
US10684863B2 (en) 2012-06-15 2020-06-16 International Business Machines Corporation Restricted instructions in transactional execution
CN107239415B (zh) * 2016-03-28 2020-02-14 华为技术有限公司 一种执行临界区操作的方法及装置
CN107239415A (zh) * 2016-03-28 2017-10-10 华为技术有限公司 一种执行临界区操作的方法及装置

Also Published As

Publication number Publication date
JP2009508187A (ja) 2009-02-26
EP1913473A1 (fr) 2008-04-23

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