WO2007008314A2

WO2007008314A2 - Rf receiver, wireless communication terminal and method of operation

Info

Publication number: WO2007008314A2
Application number: PCT/US2006/021970
Authority: WO
Inventors: Ben Ayun Moshe; Ovadia Grossman; Mark Rozental; Yaniv Salem
Original assignee: Motorola, Inc.
Priority date: 2005-07-06
Filing date: 2006-06-06
Publication date: 2007-01-18
Also published as: GB0513759D0; WO2007008314A3; AU2006269678A1; GB2428146B; GB2428146A; AU2006269678B2

Abstract

An RF receiver (100) including an RF amplifier (105) for amplifying a received input RF signal, a mixer (107) for converting an RF signal produced as an output by the RF amplifier to a baseband signal, a baseband receiver channel (115) for processing the baseband signal, the baseband receiver channel including a baseband amplifier (127), an AGC (automatic gain control) loop (130) coupled from the baseband receiver channel to the RF amplifier to provide automatic gain control of the RF amplifier, an off-channel detector (163) operable to detect activation of the AGC loop by an unwanted received off-channel signal and a control loop (145) coupled from the detector to the baseband amplifier (127) to apply a control signal to the baseband amplifier to reduce a gain of the baseband amplifier when the off-channel detector detects an unwanted received off-channel signal. Also described is a wireless communication terminal and a method of operation in the receiver.

Description

TITLE: RF RECEIVER, WIRELESS COMMUNICATION TERMINAL AND METHOD OF OPERATION

FIELD OF THE INVENTION

The present invention relates to an RF (radio frequency) receiver, a wireless communication terminal and a method of operation. In particular, the invention relates to a multi-mode RF receiver for use in a wireless communication terminal, such as for use in mobile communications, for receiving RF signals of at least two different types sharing a common spectrum.

BACKGROUND OF THE INVENTION

Mobile wireless communication systems, for example cellular telephony or private mobile radio communication systems, typically provide for radio telecommunication links to be arranged between a plurality of user or subscriber terminals, often termed 'mobile stations', MSs, via a system infrastructure including fixed installations including one or more base transceiver stations (BTSs). Mobile communication systems typically operate according to a set of industry standards or protocols. An example of such standards is the TETRA (TErrestrial Trunked Radio) standards which have been defined by the European Telecommunications Standards Institute (ETSI). A system which operates according to TETRA standards is known as a TETRA system. TETRA systems are primarily designed for use by professional radio users such as the emergency services. TETRA systems use TDMA (time divided multiple access) operating protocols in which communications are synchronised to be in a continuous timing structure which consists of time slots, frames and multiframes. Four slots make up a frame and eighteen frames make up a multiframe (one second). Communications may be on different channel types according to the type of signalling to be sent. For example, control signals for system synchronisation and control are sent on a control channel. Signals to communicate user speech and data are sent respectively on a voice channel and a data channel.

TETRA systems operating according to the existing standards are used primarily for voice communication and provide limited slow data communication. A new, second generation of TETRA standards is being developed. This is aimed at use in providing high speed data communication, for example for fast accessing of police databases, and for transfer of picture, image and video data and the like. The existing generation of TETRA standards is referred to as 'TETRA 1' standards and the new standards are referred to as 'TETRA 2' standards and in one form are known as 'TEDS' ('TETRA Enhanced Data Services') standards. TETRA 1 provides a uniform spacing between RF channels of 25 kHz. TETRA 2 (TEDS) provides channel spacings of 25 KHz, 50 KHz, 100 KHz and 150 kHz depending on required data rate. A TETRA 1 system and a TETRA 2 system may share a common spectrum. For example there may be a TETRA 1 channel having a channel width of 25 kHz channel and a channel centre frequency at 380.100 MHz and there may be a TETRA 2

(TEDS) channel having a channel width of 100 kHz and a channel centre frequency at 380.1625 MHz.

It has been proposed that a single dual mode receiver may be used to receive both TETRA 1 signals and TETRA 2 signals. However, there are significant differences between TETRA 1 signals and TETRA 2 signals. A TETRA 1 signal has a π/4 DQPSK (differential quadrature phase shift keying) modulation with a peak to average ratio of 3.3 dB. In contrast, a TETRA 2 (TEDS) signal has a 4/16/64 QAM (quadrature amplitude modulation) with a peak to average ratio of 12 dB. The peak to average ratio of 12 dB may be reduced to about 6 dB by operation of a suitable 'peak reduction' algorithm, e.g. applied in a transmitter of a base transceiver station.

The differences between TETRA 1 and TETRA 2 signals in the design of a receiver to receive both signal types give rise to problems, particularly relating to rejection of off-channel signals which might activate an AGC (automatic gain control) loop included in the receiver. In particular, receivers have to meet an 'ACR' or 'Adjacent Channel Rejection' specification. This specification defines the maximum RF level of an unwanted interfering signal in a channel adjacent to that of a wanted signal that can be applied at the receiver whilst still allowing the receiver to receive its wanted signal at 3 dB above sensitivity level. Meeting the ACR specification is made more difficult because of the greater channel widths and greater peak to average ratios of TETRA 2 signals.

SUMMARY OF THE INVENTION

According to the present invention in a first aspect there is provided a receiver as defined in claim 1 of the accompanying claims. According to the present invention in a second aspect there is provided a wireless communication terminal as defined in claim 30 of the accompanying claims.

According to the present invention in a third aspect there is provided a method as defined in claim 32 of the accompanying claims.

Further features of the present invention are as defined in the accompanying dependent claims and are disclosed in the embodiments of the invention to be described.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block schematic circuit diagram of a receiver embodying the present invention.

FIG. 2 is a block schematic diagram of part of a digital signal processor used in the receiver of FIG. 1.

FIG. 3 is a flowchart of an algorithm or procedure embodying the present invention, the algorithm or procedure being operated by a processor of the digital signal processor part of FIG. 2. DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The present inventors have appreciated that where a receiver is designed for use in a system such as a TETRA system wherein there are signals in the same spectrum of different signal types, e.g. TETRA 1 and TETRA 2, problems arise particularly in the use of an AGC (automatic gain control) loop to maintain a level, e.g. a RMS (root mean square) level, of a received signal to be a selected difference, referred to herein as an 'AGC threshold', below a saturation level of a device such as a sigma delta converter used in a baseband receiver channel of the receiver. These signal types may beneficially be distinguished by their different PARs

(peak to average ratios). The AGC threshold may be set a small incremental difference above the expected or measured PAR. This pre-determined incremental difference is desirably in the range 0.1 dB to 2dB. Thus, for a TETRA 1 signal with a PAR of 3.3 dB, the AGC threshold may be suitably set 0.2 dB above the PAR to 3.5 dB. For a TETRA 2 signal with a PAR of 12 dB, the AGC threshold may be suitably set 1 dB above the expected or measured PAR, e.g. at 13 dB. However, the inventors have appreciated that if a TETRA 1 signal is the wanted on-channel signal and the receiver is receiving interference from an unwanted off-channel TETRA 2 signal, the TETRA 2 signal may activate the AGC loop and may drive the device to be protected by the AGC loop, e.g. a sigma delta converter, into an undesirable saturation.

However, setting the AGC threshold to that suitable for a TETRA 2 signal, say 13 dB, results in a substantial reduction in the AGC free dynamic range of the receiver, e.g. by an amount equal to the difference between 13 dB and 3.5 dB, i.e. by 9.5 dB, and a result is that the ACR specification referred to earlier is unlikely to be met in this condition. If a TETRA 2 signal with peak reduction, e.g. peak to average ratio of 6 dB, is a wanted signal, use of an AGC threshold of 13 dB as selected for a TETRA 2 signal with an unreduced peak to average ratio will degrade the AGC free dynamic range by about 6 dB. Again, this may result in the ACR specification not being met. These problems are addressed in the embodiments of the invention now to be described. FIG. 1 is a block schematic diagram of a receiver 100 embodying the invention. The receiver 100 is a dual mode receiver which operates to receive an input RF signal which has been transmitted in accordance with either (a) TETRA 1 standards, i.e. is a 'TETRA 1' signal; or (b) TETRA 2 (TEDS) standards, i.e. is a 'TETRA 2' signal. An input RF signal is first applied to a step attenuator 103 and then to a low noise RF amplifier 105. An amplified RF signal provided as an output by the low noise RF amplifier 105 is applied to a mixer 107 and to a mixer 109. A reference RF signal equal to a carrier signal of the input RF signal is generated by a local oscillator 111 and is applied to the mixer 107. The reference RF signal generated by the local oscillator 111 is also applied to a phase shifter 113 which shifts the phase of the reference signal by ninety degrees, and the output of the phase shifter 113 is applied to the mixer 109. The mixer 107 downconverts the input RF signal to produce an in-phase (T) baseband component of a modulation signal carried by the input RF signal. The in-phase baseband component is produced as an output signal by the mixer 107 and is a first baseband signal processed in a first baseband receiver channel, namely an I-channel 115. A quadrature phase ('Q') baseband component of the modulation signal carried by the input RF signal is produced as an output signal by the mixer 109 and is processed as a second baseband signal in a second baseband receiver channel, namely a Q-channel 117. The in-phase baseband component produced by the mixer 107 is applied in turn in the I-channel 115 to a post mixer amplifier 119 having a low noise figure, a filter 121 which is a one pole differential baseband filter, a baseband amplifier 123, a low pass filter 125 which is a two pole baseband filter, a baseband amplifier 127 and a ΣΔ (sigma delta) ADC (analogue to digital converter) 128. Similarly, the quadrature phase baseband component produced by the mixer 109 is applied in turn in the Q- channel 117 to a post mixer amplifier 129 having a low noise figure, a filter 131 which is a one pole differential filter, a baseband amplifier 133, a low pass filter 135 which is a two pole baseband filter, a baseband amplifier 137 and a ΣΔ ADC 138. Output signals from the ΣΔ ADC 128 and the ΣΔ ADC 138 are applied to a DSP (digital signal processor) 140 which performs additional known selectivity, demodulation and other modem related processing operations, as well as some additional functions as described later, and finally provides an output signal which may be delivered via a suitable transducer, e.g. a high speed data output terminal (not shown), to a user.

An AGC loop 130 extends from the ΣΔ ADC 128 and the ΣΔ ADC 138 to the low noise RF amplifier 105. The AGC loop 130 includes an RMS estimator 139, a digital AGC controller 141, an AGC DAC (digital to analogue converter) 143 and a lineariser 144. Output signals from the ΣΔ DAC 128 and the ΣΔ DAC 138 are applied to the RMS estimator 139. A digital output signal from the RMS estimator 139 is applied to the digital AGC controller 141 which in turn provides a digital output signal to the AGC DAC 143. The AGC DAC 143 produces an analogue output signal which is applied to the lineariser 145 which linearises the response of the low noise RF amplifier 105 in a known way. An output analogue signal produced by the lineariser 145 is applied as an analogue control signal to the low noise RF amplifier 105 to adjustably control the gain of the low noise amplifier 105. Thus, as the analogue control signal applied to the low noise RF amplifier 105 is continuously varied in a manner determined by the digital AGC controller 141, the gain of the low noise RF amplifier 105 is continuously adjusted to a desired value in response.

The digital AGC controller 141 produces, in addition to the digital signal passed to the AGC DAC 143, a first further output signal which is applied to control an attenuation level of the step attenuator 103. The step attenuator 103 may for example provide two levels of attenuation, e.g. 0 dB and 20 dB, which may be selected in design or use of the receiver 100. The digital AGC controller 141 receives, in addition to the input signal from the RMS estimator 139, a further input signal from the DSP 140 via a connection 148. A control loop 145 is formed from the DSP 140 to the baseband amplifiers 127 and 137 to provide control signals needed to change a gain of the amplifiers 127 and 137 in a manner described later with reference to FIG. 3.

A control loop 146 is also formed from the DSP 140 to the filters 121, 125, 131 and 135 to provide control signals needed to change a bandwidth of the filters 121, 125, 131 and 135 according to the bandwidth of the TETRA channel of the signal being received, i.e. 25 kHz, 50 kHz, 100 kHz or 150 kHz as appropriate. In use of the receiver 100, the in-phase (T) baseband component of the modulation signal carried by the received input RF signal is passed from the mixer 107 via the I-channel 115 to the ΣΔ ADC 128. It undergoes amplification by each of the amplifiers 119, 123 and 127 and filtering by the filter 121 and by the low pass filter 125 in a known manner. The filters 121 and 125 provide in combination some analogue selectivity before the ΣΔ DAC 128. The bandwidth of these filters is selected by the DSP 140 and set by control signals applied via the loop 146 according to the RF channel spacing and modulation of the expected (wanted) channel. The filters 121 and 125 have five selectable bandwidths, one for a TETRA 1 signal and four for TETRA 2 signals of different bandwidths. Similarly, the quadrature phase CQ') baseband component of the modulation signal carried by the received input RF signal is passed from the mixer 109 via the Q-channel 117 to the ΣΔ ADC 138. It undergoes amplification by each of the amplifiers 129, 133 and 137 and filtering by the filter 131 and by the low pass filter 135 in a known manner. The filters 131 and 135 provide some analogue bandwidth selectivity in the same manner as the filters 121 and 125 under control of signals from the DSP 140 sent via the control loop 146. The ΣΔ ADC 128 which operates in a known manner quantises the incoming analogue in-phase baseband component, which it receives from the baseband amplifier 127, to form incremental samples. The ΣΔ ADC 128 measures the value of each consecutive incremental sample and provides a digital output signal representing the T component in which the value of each successive incremental sample is indicated. The digital output signal provided by the ΣΔ ADC 128 is, as noted earlier, applied as an input signal to the RMS estimator 139.

The ΣΔ ADC 138 which operates in the same manner as the ΣΔ ADC 128 produces an output digital signal representing the Q component which is applied as another input to the RMS estimator 139.

It will be apparent to those skilled in the art that other known forms of analogue to digital converter may be employed instead of the ΣΔ ADCs 128 and 138. The RMS estimator 139 is a digital processor which calculates the squares respectively of each consecutive incremental sample of the I component and the Q component from the input signals it receives. The RMS estimator 139 also sums the values of the squares obtained for each sample in a given block of N samples, where N is a pre-determined block size containing a given number of samples, e.g. from one to one hundred samples, and then divides the result by N. This gives for the block of N samples an estimate of the mean square value. Finally, the RMS estimator 139 calculates the square root of the mean square value obtained for the block of N samples giving a root mean square ('RMS') value. This is an estimate of the current RMS signal level of the modulation signal carried by the input RF signal and which has been extracted as a complex baseband signal.

A signal representing a digital value of the calculated RMS signal level for each consecutive block of samples is passed to the digital AGC controller 141. The digital AGC controller 141 when activated sets the value of an output signal for use in AGC of the gain of the low noise RF amplifier 105 based on (i) the received current RMS value from the RMS estimator 139 and (ii) a value of AGC threshold selected by the DSP 140 in a manner to be described later with reference to FIGS. 2 and 3; this value is provided in an output signal from the DSP 140 via the connection 148. The digital AGC controller 141 thus produces an output digital signal which is converted by the digital AGC controller 141 into an analogue signal by the AGC DAC 143 and is applied as an analogue control signal to the low noise RF amplifier 105 via the ■ lineariser 144. The analogue control signal controllably adjusts the gain of the low noise RF amplifier 105 in the manner described earlier to a value which will maintain the RMS signal level of the complex baseband signal to a desired difference of X dB, the 'AGC threshold', below a saturation level of each of the ΣΔ ADC 128 and the ΣΔ ADC 138. The purpose of this AGC using the current estimated RMS value is as follows. If the received I component and Q component signals applied to the ΣΔ ADC 128 and ΣΔ ADC 138 are not maintained below a saturation level the ΣΔ ADC 128 and ΣΔ ADC 138 will become clipped (saturated). In this undesirable situation, the received baseband signal will become distorted and there is a long time of recovery from this condition.

Dynamically varying values of the parameter referred to herein as the AGC threshold X are used by the digital AGC controller 141 to set an appropriate level of the signal produced by the digital AGC controller and applied via the AGC DAC 143 and the lineariser 144 to controllably adjust the gain of the low noise RF amplifier 105. These different values of the AGC threshold X depend on various conditions which apply and are determined by the DSP 140 as described later.

FIG. 2 shows in more detail a part 150 of the DSP 140. The digital signal T provided as an output signal from the ΣΔ ADC 128 is applied through a rate conversion filter 151. The digital signal 'Q' provided as an output signal from the ΣΔ ADC 138 is applied through a rate conversion filter 155. The rate conversion filters 151, 155 reduce the signal processing rate in the DSP 140 in a known manner from a high rate employed in the ΣΔ ADC 128 and the ΣΔ ADC 138 to a lower rate employed in the DSP 140. An output signal provided by the rate conversion filter 151 is applied to a channel filter 153 which is a highly selective digital filter which filters out (by completing the filtering process begun in the analogue filters 121 and 125) as unwanted off-channel signals any signals other than that in the wanted channel to which the receiver 100 is currently tuned. This wanted channel is known from TETRA control signalling received by the receiver 100 and provided to the DSP 140. Likewise, the output signal provided by the rate conversion filter 155 is applied to a channel filter 157 similar to the filter 153. An RSSI estimator 158 samples the values of the signals I and Q before they are applied to the channel filters 153 and 157 to estimate a value of the RSSI (received signal strength indication) of the baseband signal prior to channel filtering. An RSSI estimator 159 samples the values of the signals I and Q after they have been applied to the channel filters 153 and 157 to estimate a value of the RSSI of the baseband signal after channel filtering. The RSSI estimators 158 and 159 calculate an estimate of the RSSI using the following relationship:

where 7,- and Qi are the values of individual samples of I and Q and where N is the number of samples of I and Q used for averaging in a sampling block; e.g. in an example a block consists of from 500 to 10000 samples.

A PAR estimator 161 also samples the values of the signals I and Q after they have been applied to the channel filters 153 and 157 to estimate a value of the PAR (peak to average ratio) of the demodulated signal after channel filtering. The PAR estimator 161 calculates an estimate of the peak to average ratio PAR using the following relationship:

where /_f- and Q₁ are again the values of individual samples of I and Q and where N is again the number of samples of I and Q used for averaging in a sampling block; e.g. in an example a block consists of from 500 to 10000 samples.

The current values of RSSI calculated by the RSSI estimators 157 and 159 and the current value of PAR estimated by the PAR estimator 161 are delivered in respective signals to an algorithm processor 163. The algorithm processor 163 is programmed to run an algorithm or procedure, to be described with reference to FIG. 3, which determines a suitable value of the AGC threshold X to be currently used. An output signal from the algorithm processor 163 indicating the selected value of X for each consecutive block of samples is delivered to the digital AGC controller 141 (FIG. 1) via the connection 148 for use in AGC of the gain of the low noise RF amplifier 105 in the manner described earlier.

The algorithm processor 163 also acts, during the algorithm it runs, as an off- channel detector to determine whether a signal which has activated the AGC loop 130 is a wanted on-channel signal or is an unwanted interfering off-channel signal. The algorithm processor 163 has an output connection to the control loop 145 described earlier with reference to FIG. 1 to produce an output control signal if an off-channel signal is detected in a manner to be described with reference to FIG. 3. The algorithm processor 162 also has an output to the connection 148 to provide an output signal indicating a current value of AGC threshold X to be employed by the digital AGC controller 141.

FIG. 3 is a flowchart illustrating an algorithm 300 or procedure operated by the algorithm processor 163 of FIG. 2. The algorithm 300 starts at a step 301. The algorithm 300 is initiated to run each time the receiver receives a signal and the AGC loop 130 has been activated. In a decision step 303 a determination is made as to whether the currently received signal is a TETRA 1 signal or a TETRA 2 (TEDS) signal. The determination is made by reference to information held by the DSP 140 describing the currently expected and wanted signal as known from received TETRA control channel signalling. The control channel signalling for example specifies the type of signal to be received, i.e. TETRA 1 or TETRA 2, the frequency on which a signal is to be received, e.g. 392.120 MHz for TETRA 1 or 390.550 MHz for TETRA 2, and the channel bandwidth of the received signal. If the determination in decision step 303 is that the signal is a TETRA 1 signal, a step 305 is next applied. In step 305 the AGC threshold X is set by the processor 163 to 3.5 dB (which is an example selected to be not greater than 4dB) of a small pre-determined incremental difference above the expected PAR for an on-channel TETRA 1 signal, namely 3.3 dB. After step 305, a step 307 is applied in which the PAR is measured by the PAR estimator 161 and the PAR value is obtained by the algorithm processor 163. In a decision step 309, a determination is made as to whether or not the value of the PAR measured in step 307 is greater than or equal to 3.5 dB. If the PAR is found not to be greater than or equal to 3.5 dB (a 'no' state) it means that the AGC loop 130 has correctly been activated by an on-channel TETRA 1 signal. Steps 307 and 309 are then cyclically repeated until a different condition is detected. If the PAR value is found in decision step 309 to be greater than or equal to 3.5 dB (a 'yes' state) it means that there is a received signal with a high PAR and this must be an off-channel TETRA 2 signal since an on channel signal can only be a TETRA 1 signal with a PAR not greater than 3.3 dB. In this condition, a step 311 is next applied. In step 311, the AGC threshold X is set by the algorithm processor 163 to 13 dB. This is approximately a pre- determined incremental difference of 1 dB (an example of a pre-determined incremental difference selected to be not greater than 2 dB) above the expected PAR for a TETRA 2 signal. This increase in AGC threshold activates greater attenuation by the low noise RF amplifier 105 and thereby requires an off-channel signal of greater strength to maintain activation of the AGC loop 120. In a step 313 applied at the same time as step 311, the algorithm processor 163 issues a signal indicating that a reduction of 6 dB is required to the gain of the amplifiers 127 and 137. This signal is applied as a digital control signal to the amplifiers 127 and 137 via the control loop 145 to reduce the gain of these amplifiers by the required 6 dB. Reducing the gain in this way requires a 6 dB higher off-channel signal level to maintain activation of the AGC loop 130. Thus, de-activation of the AGC loop 130 may be provided by a combination of steps 311 and 313.

It is to be noted that it is preferred to reduce the gain of the last gain stage of each of the I-channel 115 and the Q-channel 117 before the ΣΔ ADC 128 and the ΣΔ ADC 138 and the beginning of the AGC loop 130. This last gain stage is at the amplifiers 127 and 137. Reducing the gain at this last gain stage minimises any resulting degradation of receiver noise figure.

After a predetermined period following step 313, e.g. a number of slots of the TETRA signal timing structure, e.g. from 2 to 100 slots, the gain of each of the amplifiers 127 and 137 is returned to its previous level by an increase of 6dB so that each of the amplifiers 127 and 137 is ready for any further gain reduction needed elsewhere in the algorithm, either in the present cycle or in a future cycle.

Following step 313 in the algorithm 300, the PAR is re-measured in a step 315. Finally, the AGC threshold X is set in a step 317 to a value which is 1 dB above the measured PAR value.

It is to be noted that if an interfering off-channel TETRA 2 signal is present and the off-channel signal is strong enough the AGC loop 130 may remain activated even after applying the 6 dB gain reduction in the amplifiers 127 and 137 in step 313. If the off-channel signal is a TETRA 2 signal having a PAR of 12 dB then the AGC threshold X is set to 13 dB in step 317. Alternatively, if the off-channel signal is a reduced peak TETRA 2 signal having a PAR of 6 dB it is necessary in step 317 to set the AGC threshold X only to 7 dB. In this case an AGC threshold X of 13 dB is excessive.

If the determination in decision step 303 is that the wanted signal is a TETRA 2 signal, a step 319 is next applied. In step 319 the AGC threshold X is set by the processor 163 to 13 dB which is a small incremental difference above the expected PAR for an on-channel TETRA 2 signal, namely 12 dB. After step 319, a step 321 is applied in which the PAR is measured by the PAR estimator 161 and the measured value is obtained by the algorithm processor 163. Next, in a step 323, the AGC threshold X is set by the processor 163 to 1 dB above the measured PAR value. It is to be noted that if the TETRA 2 signal has a reduced PAR of 6 dB the AGC threshold X will be set to 7dB. In this case an AGC threshold of 13 dB is again excessive. Next, in a step 325, the RSSI values produced respectively by the RSSI estimator 157 and the RSSI estimator 159 before and after channel filtering are compared in the algorithm processor 163. If the difference value obtained from the comparison is greater than a pre-determined threshold difference, the signal being greater prior to channel filtering than after channel filtering, it indicates that the AGC loop 130 was activated by an off-channel interfering signal. Thus, by determining the difference value between the two RSSI signals, the algorithm processor 163 determines in a decision step 327 whether or not the AGC loop 130 was activated by an on-channel signal or an off- channel signal.

If the activation of the AGC loop 130 is found in decision step 327 not to be due to an off-channel signal (a 'no' state) it means that the AGC loop 130 has correctly been activated by a wanted on-channel TETRA 2 signal. Steps 325 and 327 are then cyclically repeated until a different condition is detected. If the AGC activation is found in decision step 327 to be due to an off-channel signal (a 'yes' state) a step 327 is applied in which the gain of amplifiers 127 and 137 is reduced by 6 dB in a similar manner to step 313. Reducing the gain in this way may cause deactivation of the AGC loop 130 since the activation level for an off-channel signal level is raised by 6dB.

After a predetermined period following step 329, e.g. a number of slots of the TETRA signal timing structure, e.g. from 2 to 100 slots, the gain of each of the amplifiers 127 and 137 is returned to its previous level by an increase of 6dB so that each of the amplifiers 127 and 137 is ready for any further reduction needed elsewhere in the algorithm, either in the present cycle or in a future cycle.

A cycle of the algorithm 300 is completed following completion of step 329 (or step 317 for a TETRA 1 signal). Further cycles may be applied periodically, e.g. after a pre-determined number of TETRA signal timing slots, e.g. from 2 to 100 slots. Alternatively, or in addition, one or more further cycles may be applied when a pre- defined trigger event occurs, e.g. when system reconfiguration occurs owing to handover of a mobile station containing the receiver to a new serving cell of a cellular communication system.

Although the above embodiments of the invention have been described in terms of application to a TETRA receiver, i.e. a receiver for use in a TETRA system, particularly for receiving TETRA 2 (TEDS) signals as well as TETRA 1 signals, in which there is a strong possibility of interference between adjacent received channels, application of the invention is not limited to TETRA receivers. The invention may be applied in receivers for use in other types of communication system in which similar interference problems arise, particularly where there are two or more types of signal sharing a common spectrum.

A receiver embodying the invention as described earlier may be used in any type of RF communication terminal operating in a suitable communication system, e.g. a TETRA or other mobile communication system. For example the receiver may be employed in a mobile station such as a portable device, e.g. radio or mobile telephone, or a device fitted in a mobile vehicle. Alternatively, the receiver may be used in a fixed communication station such as a base transceiver station or a control station or dispatcher console.

Claims

1. An RF receiver including an RF amplifier for amplifying a received RF signal, a mixer for converting an amplified RF signal produced as an output by the RF amplifier to a baseband signal, a baseband receiver channel for processing the baseband signal, the baseband receiver channel including a baseband amplifier, an AGC (automatic gain control) loop coupled from the baseband receiver channel to the RF amplifier to provide automatic gain control of the RF amplifier, an off-channel detector operable to detect activation of the AGC loop by an unwanted received off- channel signal and a control loop coupled from the detector to the baseband amplifier to apply a control signal to the baseband amplifier to reduce a gain of the baseband amplifier when the off-channel detector detects an unwanted received off-channel signal.

2. An RF receiver according to claim 1 operable in response to a gain reduction of the baseband amplifier to produce de-activation of the AGC loop.

3. An RF receiver according to claim 1 or claim 2 wherein the AGC loop includes means for estimating a level of a received baseband signal, and means for applying a control signal to the RF amplifier to control a gain of the RF amplifier to maintain an amplitude level of the received RF signal to be a selected threshold difference below a desired maximum value.

4. An RF receiver according to claim 3 wherein the means for estimating is operable to estimate a root mean square level of the received baseband signal.

5. An RF receiver according to claim 3 or claim 4 including in the baseband receiver channel an analogue to digital converter, wherein the maximum value of the level of the received baseband signal is a saturation level of the analogue to digital converter and wherein the AGC loop is coupled to the receiver channel at an output of the analogue to digital converter.

6. An RF receiver according to claim 5 wherein the analogue to digital converter comprises a sigma delta converter.

7. An RF receiver according to any one of the preceding claims including a first mixer for producing an in-phase (I) baseband component of the amplified RF signal produced as an output signal by the RF amplifier and a second mixer for producing a quadrature phase (Q) baseband component of the amplified RF signal produced as an output by the RF amplifier, an I-channel operable to process the in-phase baseband component and a Q-channel operable to process the quadrature phase baseband component, wherein each of the I-channel and the Q-channel includes a baseband amplifier and the control loop is coupled from the off-channel detector to the baseband amplifiers of the I-channel and the Q-channel to apply a control signal to reduce a gain of both of the baseband amplifiers when the off-channel detector detects an unwanted received off -channel signal.

8. An RF receiver according to claim 7 wherein each of the I-channel and the Q- channel includes a sigma delta analogue to digital converter and wherein the AGC loop includes an RMS estimator which is operable to receive output signals from each of the sigma delta analogue to digital converters and to estimate an RMS value of a received baseband signal by squaring samples of the signals received from the sigma delta analogue to digital converters, summing values obtained by squaring, averaging values obtained by summing for a block of samples and finding a square root of a value obtained by averaging.

9. An RF receiver according to any one of claims 3 to 8 including a processor operable to dynamically select a value of the selected threshold difference.

10. An RF receiver according to claim 9 including a PAR estimator for estimating a PAR (peak to average ratio) of a received baseband signal, the processor being operably coupled to the PAR estimator, and being operable to select, based on an estimated value of the PAR, a value of the selected threshold difference which is a pre-determined incremental difference greater than the estimated value of the PAR.

11. An RF receiver according to claim 10 wherein the processor is operable to 5 select a value of threshold difference which is not more than 2 dB greater than the estimated value of the PAR.

12. An RF receiver according to claim 10 or claim 11 including an I-channel including a first sigma delta analogue to digital converter to produce digital samples

10 of a baseband I-component signal received via the I-channel and a Q-channel including a second sigma delta analogue to digital converter to produce digital samples of a baseband Q-component signal received via the Q-channel, wherein the PAR estimator is operable to calculate a value of peak to average ratio PAR using the following relationship:

where /,^• and Qi are the values of individual samples of the I-component and Q- component signals and where N is a a number of samples of each of /,^• and Qi used in the PAR estimator for averaging in a sampling block and 'max' is a detected 20 maximum value.

13. An RF receiver according to any one of claims 9 to 12 wherein the processor also comprises the off-channel detector.

5 14. An RF receiver according to any one of the preceding claims wherein the off- channel detector is operable to detect that a PAR of a received signal is greater than expected for a wanted signal and is due to an unwanted signal, and in response, to issue a signal via the control loop by which a reduction in gain of the baseband amplifier or amplifiers is produced.

15. An RF receiver according to claim 14 wherein the wanted signal is a TETRA 1 signal and the signal having a greater than expected PAR is an unwanted off- channel TETRA 2 signal.

16. An RF receiver according to any one of the preceding claims wherein the off- channel detector includes a first RSSI (received signal strength indication) estimator for estimating an RSSI value of a received baseband signal prior to selective channel filtering, a second RSSI (received signal strength indication) estimator for estimating an RSSI value of the received baseband signal after selective channel filtering and a comparator for comparing signals representing RSSI values estimated by the first and second RSSI estimators to determine whether there is a substantial difference between the two values and, if there is a substantial difference, to issue a signal via the control loop by which a reduction in gain of the baseband amplifier or amplifiers is produced.

17. A receiver according to claim 16 wherein the off-channel detector is operable when the receiver is expected to receive a wanted on-channel TETRA 1 signal to determine if activation of the AGC loop has been caused by reception of an unwanted off-channel TETRA 2 signal.

18. An RF receiver according to any one of claims 9 to 17 wherein the AGC loop includes a digital AGC controller operable to receive an input signal from the processor indicating the threshold difference selected by the processor to be used in automatic gain control by the AGC loop and to receive a varying input signal from means for estimating a level of the received baseband signal and to use the input signals to provide a control signal for use in automatic control of the gain of the RF amplifier. '

19. An RF receiver according to claim 18 including a digital to analogue converter operably coupled to the digital AGC controller for converting the control signal provided by the digital AGC controller from digital to analogue form.

20. An RF receiver according to claim 19 including a lineariser coupled between the digital to analogue converter and the RF amplifier to linearise a response of the RF amplifier to gain control by the control signal in analogue form produced by the digital to analogue converter.

21. An RF receiver according to any one of claims 9 to 20 wherein the processor for selecting a value of the threshold difference is operable to select a first value of the threshold difference when a received RF signal is expected to be a first type of signal having a first value of peak to average ratio and to select a second value of the threshold difference when a received RF signal is expected to be a second type of signal having a second value of peak to average ratio.

22. An RF receiver according to claim 21 wherein the first type of signal is a TETRA 1 signal and the second type of signal is a TETRA 2 signal.

23. An RF receiver according to any one of claims 9 to 22 wherein the processor for selecting a value of the threshold difference is operable to run an algorithm to determine if an activation of the AGC loop is due to receipt of an on-channel or an off-channel signal.

24. An RF receiver according to claim 23 wherein the algorithm includes a first step in which the selected threshold difference is set according to an expected signal type and a later second step in which the selected threshold difference is set a predetermined incremental difference greater than a measured PAR value.

25. An RF receiver according to claim 23 or claim 24 wherein the processor is operable to run a first algorithm when receipt by the receiver of a signal of a first type is expected and to run a second algorithm when receipt by the receiver of a signal of a second type is expected.

26. An RF receiver according to any one of claims 22 to 25 which is operable to detect that an expected signal is a TETRA 1 signal and the processor in response to such a detection is operable to apply successively the following steps:

(i) to set the threshold difference to a value of not more than 4 dB; (ii) to obtain a PAR measurement value;

(iii) if the PAR measurement value is equal or greater than the threshold difference set in step (i) to set the threshold difference to a value of not more than 14 dB and to issue a signal to cause the gain of the baseband amplifier or amplifiers to be reduced; and then (iv) to obtain a PAR measurement value; and

(v) to set the threshold difference to the measured value of PAR plus Y dB, where Y is an incremental difference of not more than 2 dB.

27. An RF receiver according to any one of claims 22 to 26 which is operable to detect that an expected signal is a TETRA 2 signal and the processor in response to such a detection is operable to apply successively the following steps:

(i) to set the threshold difference to a value of not more than 14 dB;

(ii) to obtain a PAR measurement value;

(iii) to set the threshold difference to the measured value of PAR plus Y dB, where Y is an incremental difference not more than 2 dB;

(iv) to detect whether the RSSI value of a received signal before selective channel filtering is greater by at least a threshold difference greater than the RSSI value of the received signal after selective channel to determine if the AGC loop has been activated by an off-channel unwanted signal; (v) if in step (iv) it is detected that the AGC loop has been activated by an off-channel unwanted signal, to issue a signal to cause the gain of the baseband amplifier or amplifiers to be reduced.

28. A receiver according to any one of claims 1 to 27 wherein the control loop coupled from the detector to the baseband amplifier or amplifiers is operable a predetermined period after the gain of the amplifier or amplifiers is reduced to apply a further control signal to the baseband amplifier or amplifiers to cause the gain of the baseband amplifier or amplifiers to be increased.

29. A receiver according to any one of claims 23 to 28 wherein, during periods when the receiver is receiving a signal, the processor is operable to repeat the algorithm every time a pre-determined period has elapsed since a previous run of the algorithm and/or is operable to provide a run of the algorithm when a pre-defined trigger event occurs.

30. A wireless communication terminal including a receiver according to any one of claims 1 to 29.

31. A wireless communication terminal according to claim 30 operable in accordance with TETRA 1 and TETRA 2 standards.

32. A method operation in a receiver according to any one of claims 1 to 29 which includes receiving an input RF signal, amplifying the received input RF signal by an RF amplifier, applying the amplified RF signal produced as an output by the RF amplifier to a mixer to convert the amplified RF signal to a baseband signal, processing the baseband signal in a baseband receiver channel including a baseband amplifier, providing AGC (automatic gain control) of the RF amplifier by an AGC loop coupled from the baseband receiver channel, detecting by an off -channel detector activation of the AGC loop by an unwanted received off-channel signal and applying via a control loop coupled from the off -channel detector to the baseband amplifier a control signal to the baseband amplifier to reduce a gain of the baseband amplifier when the off-channel detector detects an unwanted received off -channel signal.

33. A receiver according to any one of claims 1 to 29 and substantially as described herein with reference to any one or more of the accompanying drawings.

34. A method according to claim 32 and substantially as described herein with reference to any one or more of the accompanying drawings.