WO2007006851A2

WO2007006851A2 - Method for improving the operation of a power control circuit and an advanced power control circuit

Info

Publication number: WO2007006851A2
Application number: PCT/FI2006/000253
Authority: WO
Inventors: Mikko KAIJÄRVI; Teemu HAAPAJÄRVI
Original assignee: Schneider Electric Industries Sas
Priority date: 2005-07-14
Filing date: 2006-07-14
Publication date: 2007-01-18
Also published as: FI20050751A0; FI117607B; WO2007006851A3; EP1911141A2

Abstract

The invention relates to a method for improving the operation of a power control circuit, particularly a dimmer. The power control circuit is realized as a phase controlled power circuit, comprising a control unit and a switching unit, meant to be connected in series with the load; the AC power supplied in the load is controlled by adjusting the phase angle of the supply voltage during each half-cycle. According to the invention, in the method there is defined (701) a first length (Tm) of the half- cycle, there is measured (702, 703) a second length (Tn) of the half-cycle, there is defined (704) a possible difference (ΔTn = Tm - Tn) between the first length (Tm)) and the second length (Tn) of the half-cycle, which is interpreted as an error of the second length of the half-cycle, and the defined error (ΔTn = Tm - Tn) is taken into account a correcting factor when defining the switching moment (tak) proper, corresponding to the phase angle, during the next half-cycle, so that the switching moment (ta) of the switching unit is shifted as a corrective measure for the magnitude of the defined difference (ΔT) and in a direction that compensates the error. The invention also relates to an advanced power control circuit applying the method.

Description

Method for improving the operation of a power control circuit and an advanced power control circuit

The invention relates to a method according to the preamble of claim 1 for improving the operation of a power control circuit, such as a dimmer.

The invention also relates to an advanced power control circuit according to the preamble of claim 8.

Generally AC power that is connected to load is adjusted by disconnecting the electric current passing through the load, so that the electric power obtained in the load is defined from the ratio of the connected and disconnected time of the load current and from the amplitude of the AC voltage changing along with the time. In most AC applications, load current is connected to be conducted in the load and respectively disconnected during the AC voltage half-cycle. This kind of device is called a phase controlled power circuit. Phase controlled power circuits can be used for adjusting for example light fixtures, motors and electric heating elements.

A phase controlled power circuit that connects the load current during an AC voltage zero point is most advantageously suited to adjusting a load that is typically capacitive, i.e. an RC load. In that case the charge current of the capacitance C, dependent on the voltage rate of change du/dt, remains low. In the specification below, this kind of control method is called reverse phase control. Said control method is also suited for controlling resistive loads. A device using reverse phase control, in which device the switching component is a FET, i.e. a field effect transistor, is disclosed in the international patent application WO 9322826. Another device using reverse phase control, wherein the employed switch components are transistors, is disclosed in the US patent publication US 4,528,494.

A phase controlled power circuit that disconnects the load current at the zero point of the current passing through the load is most advantageously suited to controlling typically inductive loads, i.e. RL loads. Current changes di/dt with a high rate of change result in a rugged overvoltage of the inductance L. In order to avoid this voltage peak, the load current is disconnected at the zero point of the current passing through the load. This kind of control method is called forward phase control, and a generally known triac control circuit that applies said control is disclosed, among others, in the US patent publication 6,175,195. A universal phase controlled power circuit, where depending on the load, i.e. RC or RL load, there is applied either reverse phase control or forward phase control, is disclosed in the earlier Finnish patent application 20040904 of the present applicant.

A problem with known phase controlled power circuits is that in addition to the AC voltage over the load, there also is created a direct voltage component, i.e. a DC component. This is harmful for example when the dimmer load circuit includes a toroidal transformer. Under the influence of the DC component, the transformer core begins to be saturated, and as a consequence, either the dimmer fuse or the transformer fuse blows, unless the DC component is removed.

When sinusoidal AC voltage is controlled in a phase controlled power circuit by switching the load current on and off during the AC voltage half-cycle, there is always also created a direct voltage component, i.e. a DC component. This is illustrated in Figures IA and IB, where for the sake of illustrative clarity it is assumed that the load current I_κ is switched on and off at the zero point of the mains voltage V_AC- Figure IA shows a first example where in between switching the load current I_K on pi and off pθ, there is an equal number of positive PA and negative PB half-cycles. Figure IB respectively shows a second example, where in between switching the load current I_K on and off, there is a different number of positive PA and negative PB half-cycles; in this case, two positive PA and one negative PB half- cycle. In the first example, a DC component is not created, whereas in the second example it is created owing to the imbalance of the half-cycles. As is known, in a phase controlled power circuit, the switching of the load current is not always carried out at the network zero point, but the switching point is adjusted within the half-cycle for feeding the desired AC power to the load. Even in this case, the summed area of the positive and negative half-cycles, i.e. the area of the half-cycle elements, should be zero in order to prevent the creation of a DC component.

Another problem with known phase controlled power circuits is that various interference from the electrical network as well as from network commands affect the supply voltage VA_C and the AC voltage and current over load, and hence also the power supplied to the load. In that case the supply voltage V_Ac includes, as summed in the basic frequency, harmonic waves, owing to the effect of which the value of the AC voltage fluctuates in rapid sequences inside the half-cycle PA, PB, as is illustrated in Figure 2. Network commands are digital or analog control signals transmitted through electric conductors to adjusting and/or controlling devices connected thereto. Said interference and/or network commands affect the supply voltage zero points t₀₁, t_02s t_O3, t_O4, and also the zero points of the load current passing through the load, altering their momentary locations and the lengths of the half- cycles PA, PB.

When reverse phase control is applied in a phase controlled power circuit, particularly in a dimmer using phase control, the closed time of the switching unit switches during each half-cycle is controlled directly, starting from the zero point of the supply voltage and/or load current, and by adjusting the recommended time, i.e. switching moment, proportional to the set phase angle. In that case the closed time of the switches, i.e. the time period the switches are conductive, is precisely known, and it is equal to said recommended time. In case the zero point is even slightly moved owing to interference or a network command signal, such as for instance for 50...100 μs, this may already be seen as a change in the dimmer luminosity, i.e. as flashing.

When forward phase control is applied in a phase controlled power circuit, particularly in a dimmer using phase control, the closed time of the switches of the switching unit is not precisely known for the duration of the half-cycle. The reason for this is that a dimmer or the like is controlled on the basis of the open time of the switching unit switches (i.e. the time period when the switches are not conductive), and consequently it is assumed that the closed time of the switching unit switches is the difference of the half-cycle and said open time. This is not, however, exactly the case, especially when the load of the phase controlled power circuit is an inductive load, such as for example a halogen lamp dimmer, and when external electric interference affect the phase controlled power circuit. An inductive load causes phase difference in between the voltage and the current, and electric interference may shift the zero points. These factors cause temporary asymmetry in the power supply, and hence in the DC component load. As a consequence, for example the halogen lamp transformer begins to be saturated and finally reaches saturation. Particularly with high control values (large phase angle), saturation takes place very rapidly. In that case the dimmer or the transformer may be broken, or at least the protecting fuse burns, unless the DC component is not eliminated.

Another drawback is that as a consequence from said interference and network commands, for example the power of the dimmer lamp may vary, which results in flashing or rapid changes in the lamplight, as was already maintained above. Often these phenomena also result in unpleasant noises, such as crackling and whirring noises. In the prior art there is know, from the European patent publication EP-1135007, a dimmer applying the phase angle control method. Said publication suggests that the real load current zero points should be replaced by virtual zero points that are based on the calculation of the zero point average. By means of this method, the operation of the dimmer can be stabilized, particularly for eliminating fluctuations in the AC voltage frequency, but also interference from network command devices.

A problem with the stabilizing method described in said publication is that asymmetric waveforms and/or waveforms resulting from temporary interference are not compensated. The dimmer is controlled on the basis of an average virtual zero point, in principle always symmetrically. Thus the interference does not directly affect the control or the luminosity. By applying mis dimmer control method, it is not possible to eliminate the creation of a DC component or the defects caused thereby.

The object of the present invention is to eliminate the drawbacks connected to phase controlled power circuits, particularly to prevent the creation of direct voltage, i.e. a DC component, and to eliminate network interference. Another object of the invention is to realize a new phase controlled power circuit, particularly a dimmer, that is suited for controlling the luminosity of many different types of light fixtures.

The method according to the invention for improving the operation of a power control circuit is characterized by what is set forth in claim 1. The advanced power control circuit according to the invention is characterized by what is set forth in claim 8. The dependent claims disclose preferred embodiments of the invention.

In a method according to the invention for improving the operation of a power control circuit, particularly a dimmer, said power control circuit is realized as a phase controlled power circuit provided with a control unit and a switching unit, meant to be connected in series with the load, and the AC power supplied in the load is controlled by adjusting the supply voltage phase angle during each half- cycle. In the method according to the invention:

- there is defined the first length of the half-cycle,

- there is measured the second length of the half-cycle,

- there is defined the possible difference of the first and second lengths, which is interpreted as an error of the second length of the half-cycle; and - the defined error is taken into account as a correcting factor of the switching moment when defining the switching moment proper, corresponding to the phase angle, during the next half-cycle, so that the switching moment of the switching unit is shifted, as a corrective measure, for the magnitude of the defined difference and in a direction that compensates the error.

An advanced power control circuit according to the invention, particularly a dimmer, comprises a switching unit and a control unit meant to be connected in series with the load, so that under the control of said control unit, the AC power supplied in the load by the switching unit is controlled by adjusting the phase angle during each half-cycle of the supply voltage. According to the invention, the advanced power control circuit also comprises a switching moment correction unit, provided with:

- means for defining the first length of the half-cycle;

- means for measuring the second length of the half-cycle; and

- means for calculating a possible difference between said half-cycle lengths, said difference being interpreted as an error of the second length of the half- cycle; and

- means for correcting the switching moment, by taking into account the calculated difference as a correcting factor of the switching moment when defining the switching moment proper, corresponding to the phase angle, during the next half-cycle, so that the switching moment of the switching unit is shifted as a corrective measure for the magnitude of the defined difference, and in a direction that compensates the error.

The invention is based on the measurement of the half-cycle length, i.e. the second length, on comparing it with the constant length of the half-cycle, i.e. with the first length, and on controlling the switching moment on the basis of the performed measurements and comparisons. The principle of the invention is to control the switching moment within the half-cycle, so that the creation of a DC component is rapidly and effectively prevented, and any cumulative effects cannot occur. Deviations caused in the half-cycle length by interference are measured, and the ensuing correction is realized during the next half-cycle by controlling the moment of switching the load current on or off, so that current is supplied in the load essentially for the same amount of time as during the previous cycle, in case the given recommended value remains the same.

In a preferred embodiment of the invention, the first length of a half-cycle is defined on the basis of the second lengths of the earlier measured half-cycles, by calculating an average for said half-cycle lengths and by setting said obtained average as the first length of the half-cycle. The advantage is that the first length of the half-cycle is defined by measurements, and it need not be separately given as a constant.

In a preferred embodiment of the invention, at least two successive load current zero points are registered, and there is defined the second length of the half-cycle, which second length is the time difference between two successive zero points.

It is an advantage of the invention that the different on-time sequences of the load current of the positive and negative half-cycles, caused by zero point errors, are eliminated rapidly after detection, so that any defective DC component cannot be created. The measurement of the second length of the half-cycle is based on registering real, successive zero points and on defining their time difference, which data is immediately utilized by comparing it with the first length of the half-cycle, which thus represents the constant value of the half-cycle. When a sufficiently large difference, i.e. deviation, is detected between them, it is fully compensated during the next half-cycle.

In a preferred embodiment of the invention, the difference is calculated for two successive half-cycles, and their sum is taken into account as an error value during the next half-cycle, when defining the switching moment proper. The history data of the errors/deviations of the half-cycles is then utilized in the compensation process. The purpose is to even out errors in two successive, directionally opposite half- cycles, so that during these half-cycles, current sequences of equal magnitudes are supplied in the load. This is carried out so that in addition to the first half-cycle, the switching moment also is corrected in the second half-cycle, and the error correction term of the second half-cycle is calculated as a sum of the errors of two successive, first and second, half-cycles, which term is then subtracted from or added to the evaluated switching moment, in which case the switching moment to be realized is shifted according to the obtained error sum, according to the signum thereof, and also for the magnitude of the error sum, i.e. the error value. Another advantage of the invention is that the elimination of zero point errors can be realized in a two-wire power control circuit, i.e. a power control circuit that is realized without a neutral wire.

Yet another advantage of the invention is that both the method and the advanced power control circuit applying the method are simple and easy to realize. They do not necessarily require additional components in the control unit of the phase controlled power circuit, which control unit is preferably realized with a microcontroller or a corresponding data processing unit, but all steps in the process can be realized by programming.

In the most advantageous embodiment of the invention, there also is utilized zero points filtering. An advantage of this arrangement is that extra trouble zero points located mutually near to each other can thus be eliminated, and they cannot disturb the operation of the power control circuit, and especially not the elimination of the DC component.

The invention and its further advantages are described in more detail below, with reference to the accompanying drawings, where

Figure IA illustrates a first example, where in between switching the load on and off, there are equally many positive and negative half-cycles;

Figure IB respectively illustrates a second example, where in between switching the load on and off, there are a different number of positive and negative half-cycles;

Figure 2 illustrates the supply voltage obtained from the AC power source, when interference is connected thereto;

Figure 3 is a block diagram illustrating an advanced power control circuit according to the invention;

Figure 4 illustrates a switching unit that can be applied in the advanced power control circuit,

Figure 5A illustrates the supply voltage obtained from the AC power source as a function of the phase angle and time;

Figure 5B illustrates the modes of the first and second switches of the switching unit; Figure 5C illustrates the load voltage as a function of the phase angle and time, when the load is resistive, and when reverse phase control is applied;

Figure 6 illustrates a troubled supply voltage and the load current obtained therefrom, when the load is an RC load, and when reverse phase control is applied;

Figure 7 illustrates a troubled supply voltage and the load current obtained therefrom, when the load is an RL load, and when forward phase control is applied;

Figure 8 is a flow diagram illustrating a method according to the invention for improving the operation of a power control circuit; and

Figure 9 is a block diagram illustrating the correction unit of an advanced power control circuit according to the invention.

Like numbers for like parts are used in the drawings.

Figures IA, IB and 2 were already dealt with in the introduction above.

An advanced power control circuit 1 according to the invention is illustrated as a block diagram in Figure 3. A power control circuit 1 and a load circuit K are connected in series. The AC power source AC, such as an AC distribution network, is connected over the power control circuit 1 and the load K. The power control circuit 1 comprises a switching unit 2 or a corresponding unit controlling the load current, and a control unit 3. By means of the switching unit 2 or other corresponding unit, the supply of the current I_K to the load K is started and/or interrupted during each half-cycle PA, PB of the supply voltage V_Ac obtained from the AC power source AC (cf. Figures 5A and 5C) at a given, predetermined phase angle φ_a. Said phase angle is defined in the control unit 3. The AC power fed in the load K is then controlled by adjusting the phase angle φ of the supply voltage V_AC and/or of the load current I_K. The recommended electric value ohje(φ_a) is fed in the control unit 3 with a suitable setting device that can be for example manually controlled, such as a dimmer adjusting knob. In addition, the power control circuit 1 comprises a switching moment correction unit 4, which most advantageously is arranged as part of the control unit 3, but which as an alternative can also be a separate unit that communicates with the control unit.

The power control circuit 1 also comprises a power source 5, through which at least the control unit 3 is supplied with suitable electric power, most advantageously DC power, for running it. The power source 5 is preferably realized as a DC power source that is arranged to receive the electric power over the switching unit 2 both in a case when the switching unit is conductive, i.e. in closed mode, and in a case when it is not conductive, i.e. in open mode. In that case the power control circuit 1 is realized as a so-called two-wire power control circuit, so that the power control circuit 1 can only be connected to the hot wire going to the load, and a separate neutral wire is not needed. As an alternative, the power control circuit 1 can also be realized so that its supply voltage is taken from the network wire, and the reference potential is taken from the network neutral wire, in between which wires also the power source of the power control circuit can be connected.

In the example illustrated in the drawings, Figure 4, the switching unit 2 comprises two switching elements connected in succession, such as a first and a second switch kl, k2, and in parallel with these, there are also arranged, likewise connected in succession, reverse coupled diodes, i.e. a first and a second diode dl, d2. In this switching unit example, the diodes dl, d2 are also connected together at the anodes and in between the switches kl, k2. The diodes dl, d2 are forward coupled, away from the mutual connecting point. Said connecting point is advantageously used also as the virtual earth of the control unit 3. The switching unit 2 can be realized for instance by using two MOSFET transistors serving as the switches kl, k2 and diodes, so-called body diodes dl, d2 provided in connection thereto.

By means of the control unit 3, the switches kl, k2 of the switching unit 2 are switched in turns to an electrically conductive mode, i.e. to a closed mode and respectively to a non-conductive mode, i.e. open mode, during the half-cycle PA, PB of the AC voltage V_Ac serving as the supply voltage.

The switching unit 2 can be arranged to be conductive in either direction, i.e. direction a or direction b, i.e. either from the AC source AC towards the load K or from the load K towards the AC source AC, depending on which of the switches kl, k2 is switched to conductive mode, and which is switched to non-conductive mode. The switching unit 2 is only conductive in one direction at a time, i.e. a or b. Moreover, the switching unit 2 is functionally realized so that it commutes at the zero points of the load current I_κ. In that case the switching unit 2 stops being conductive or starts to be conductive a the zero point of the load current I_κ, depending on the basic arrangement of the phase angle control, i.e. according to whether the applied control method is forward phase control of reverse phase control. The phase angle φ_a, at which, depending on the applied control method, the current supply to the load is respectively either stopped or started, is defined in the control unit 3 for instance on the basis of a recommendation from an external control signal ohje(φ_a), i.e. in principle according to how large a proportion of the maximum power should be fed in the load K.

It is pointed out that in the specification above, we have disclosed only one preferred embodiment of the switching unit 2. The switches of the above described switching unit 2, i.e. the first switch kl and the second switch k2, as well as the diodes, i.e. the first diode dl and the second diode d2, can also be arranged in another fashion, for example the first switch kl and the second diode d2 in succession, and respectively the second switch k2 and the first diode dl in succession, in parallel branches of the switching unit. In this configuration, the operation of the switching unit 2 would remain similar to the operation of the previous configuration.

The operation of the power source 1 is illustrated in Figures 5A, 5B, 5C, 6 and 7. The voltage of a sinusoidal AC power source AC, i.e. the supply voltage V_AC? as a function of the phase angle φ and also as a function of time t is schematically illustrated in Figure 5 A. The length of one cycle is P, i.e. 360 degrees, and respectively the positive half-cycle is PA and the negative half-cycle is PB, which both constitute 180 degrees. The cycle length P in time units t depends on the AC power source frequency, which generally is either 50 or 60 Hz, when dealing with a universal AC distribution network. The cycle length P is 20 ms, when the frequency is 50 Hz, which thus corresponds to the phase angle 360 degrees. During the half- cycle, the phase angle φ_a (switching unit 2 to conductive mode or to non-conductive mode) is adjusted between 0 — 180 degrees, which at a corresponding switching moment t_a is set within the time period 0 - 10 ms, which maximum value is the half-cycle length T.

The modes of the first switch kl and respectively the second switch k2 are illustrated in Figure 5B, where mode 0 means that the switch is open, i.e. non- conductive, and mode 1 means that the switch is closed, i.e. conductive. The switches kl, k2 are controlled in turns, so that in the exemplary case of Figure 5B₅ the first switch kl is conductive during the positive half-cycle PA of the AC voltage VA_C after reaching the phase angle φ_a and the corresponding switching moment t_a, and respectively the second switch k2 is conductive during the negative half-cycle PB after reaching the phase angle φ_a and the corresponding switching moment t_a. The phase angle at which the supply of the current I_κ in the load K is started in this example is during the positive half-cycle φ_a and during the negative half-cycle φi+180 degrees, when observing the whole cycle length P. Consequently, when defined from the starting moment of the half-cycle PA, PB i.e. from the zero point, the phase angle φ_a and the switching moment t_a are always the same and follow the given recommended value ohje(φ_a).

The curve shapes of the load current I_κ of the power control circuit 1 are illustrated in Figure 5C. In this case, the load K is resistive, such as a filament lamp, the luminosity of which is controlled by adjusting the AC power supplied therein, and by realizing reverse phase control. Thus there is no phase difference between the load voltage V_κ and the current I_κ, but they follow each other with the same phase angle; the load voltage V_K ⁼ I_R ^' Rκ_> when the switching unit 2 of the power control circuit is in conductive mode, and the resistance of the load K is R_K-

During the first positive half-cycle PA of the supply voltage V_Ac_> at the phase angle φ_a (or at a corresponding switching moment t_a, which thus represents the time delay with respect to the zero point t_On, where n = 1, 2, 3...) defined from the first load current zero point t_Oi (Figure 5C), the first switching element kl is switched to closed mode simultaneously as the second switching element k2 is switched to open mode (Figure 5B). Now the load current I_κ is arranged to pass via the first switch kl and the forward coupled second diode d2, until the direction of the supply voltage V_AC and at the same time of the load current I_κ is changed at the second zero point to₂- Now the direction of the load current I_κ is changed to opposite with respect to the second diode d2, and this prevents the current from being supplied to the load K. During the second negative half-cycle PB of the AC voltage V_Ac_> at the phase angle φ_a (and respectively at the switching moment t_a) defined from the second zero point to₂, the second switching element k2 is switched to closed mode simultaneously as the first switching element kl is switched to open mode. Now the load current IK is arranged to pass through the second switching element k2 and the forward coupled first diode dl, until the direction of the load current is again changed at the next zero point t_O3 of the current. With respect to the changing of the load current I_κ, said zero point to₃ corresponds to the first zero point to_ls where the direction of the load current I_κ is changed to opposite with respect to the first diode dl. Thus the first diode dl prevents the passage of the current to the load, until during the third half- cycle, which corresponds to the first positive half-cycle PA, the above described steps are repeated. At a phase angle φ_a (or at a switching moment t_a), defined from the current zero point t₀₁, fø, the load current I_κ passes through the load K, as far as the next current zero point t_O2, t₀₃. With a resistive load K, the load current I_κ conforms, with the same phase angle, to the load voltage V_κ, as was already maintained above. The load voltage VR conforms to the AC voltage V_Ac of the AC source AC, when the switching unit 2 is in conductive mode, and allows the current I_κ to pass through.

When interference occurs in the supply voltage VA_C? it affects the load voltage VR and the current I_κ. The momentary locations of the load current zero points t₀₁, to₂,to₃, to₄ ... in successive half-cycles PA, PB may vary and affect the electric power supplied in the load K. The zero points can occur either before or after the regular zero point t₀₁₁, t₀₂i, falling at 0 and 180 degrees, of the ideal load current I (illustrated by dotted lines), as is illustrated in Figures 6 and 7.

The method according to the invention is applied for eliminating the effects of interference. An advanced power control circuit according to the invention is provided with a switching moment correction unit 4 utilizing a corresponding method.

A few embodiments of the method according to the invention are illustrated step by step in Figure 8. Here we also refer to Figures 6 and 7.

In the first step 701 of the method according to the invention, there is defined the length of the half-cycle PA, PB of the supply voltage V_AC? i-e- the first length T_m of the half-cycle. It is in general practical to define the half-cycle lengths in time units. The first length of the half-cycle is either known, or it can be measured. In principle, the first length of the half-cycle is a constant value depending on the frequency, which can be given for the power source control unit 3 and for the correction unit 4. The first length T_m of the half-cycle is recorded for example in the memory 6 of a correction unit 4, such as a first memory unit 61.

In the second step 702, the zero point t_On (n = 1, 2, 3, 4,...= positive integral) of the load current I_κ is registered. During this step, there are registered at least two successive load current zero points t_O(n-1), to_n. After one zero point is registered, step 702a, it is checked whether the previous zero point was registered, and if it is not, the next zero point is registered, step 702b. As an alternative, if the previous zero already was registered, we proceed to the third step. In practice, successive zero points t_On (n = 1, 2, 3, ...) are registered continuously, when the power control circuit 1 is in operation.

In general, the power control circuit detects the load current zero points, by means of which the operation of the control circuit is synchronized. Hence, in a method according to the invention, as well as in an advanced power control circuit applying said method, this existing data is advantageously utilized. In the third step 703, on the basis of the last registered zero point to_n (such as t₀] in Figures 6 and 7) and the previous zero point t_O(n-i₎ (too), there is calculated the time difference between these zero points. Said time difference is the length of the latest completed half-cycle, i.e. the second length T_n = t_On - t_O(n-i₎ (Ti) of the half-cycle.

In the fourth step 704, there is calculated the difference between the first length T_m of the half-cycle and the second length T_n of the half-cycle, i.e. ΔT_n = T_n, - T_n (such as for example ΔTi = T_m — T₁ in Figures 6 and 7), and it is recorded with its signum in a suitable memory 6, such as a second memory unit 62.

In the fifth step 705, there is formed the absolute value (i.e. value without signum) of the difference ΔT_n (ΔTi), and it is compared with a suitable reference value that is theoretically zero but in practice a generally small positive number p approaching zero. The number p is for example 0.1% of the half-cycle length, which is defined in suitable units, preferably in units of time. When the frequency of the employed AC voltage is 50 Hz, the first length T_m of the half-cycle is 20 ms, and respectively, according to the example given above, p = 0.02 ms. If the absolute value of the difference ΔT_n (AT₁) is other than zero, i.e. in practice larger or equal to said small number, the obtained result, i.e. the difference ΔT_n (AT₁), is interpreted to signify an error in the second length T_n (T₁) of the half-cycle. Basically it is interpreted to signify an error in the location of the last registered zero point t_On (t_Oi). In addition, the signum +/- of the difference ΔT_n (ΔTi) indicates the direction of the error. If the first length T_m of a half-cycle is larger than the second length T_n, the difference and the direction of the error are positive, and respectively, if the first length T_n, is smaller than the second length T_n, the difference and the direction of the error are negative. As a logical and advantageous starting-point for the above described comparison, there is the constant value of the half-cycle, i.e. the first length T_m, in relation to which the second length T_n (T₁) is evaluated.

As an alternative, also the second length T_n (T₁) of the half-cycle can be chosen as the starting point, with which the first length T_m is compared, in which case the direction of the defined error is naturally changed. Now, if the second length T_n of the half-cycle is larger than the first length T_m, the difference and the direction of the error are negative, and respectively, if the second length T_n is smaller than the first length T_m, the difference and the direction of the error are positive.

When an error is detected in said second length T_n (Ti) of the half-cycle PB, the required correction is calculated for the next switching moment t_a in the sixth step 706. The switching moment t_a is always defined starting from the completed and detected load current zero point. The switching moment t_a of the switch kl, k2 in the switching unit 2 is shifted, within the half-cycle PA, as a corrective measure for the magnitude of the error, i.e. the absolute value of difference ΔT_n (AT₁), and in this embodiment, in the direction indicated by its signum (for example the arrow at the marked difference AT₁ in Figures 6 and 7). Thus a positive signum (+) of the difference ΔT_n means shifting forwards in time, and respectively a negative signum (-) means shifting backwards in time with respect to the original switching moment t_a. Consequently, the corrected switching moment is t_ak = t_a + ΔT_n.

In the seventh step 707, the switching moment t_a is replaced by the new corrected switching moment t_ak, which is realized in the control unit 3 when controlling the switching unit 2. Thus the error caused by interference in one half-cycle PB is immediately compensated in the next half-cycle PA. The operation can be continued in the fashion described above in each following half-cycle for correcting the switching moments t_a.

In another embodiment of the method according to the invention (Figure 6), the obtained difference, i.e. error value ΔT_n (such as AT₁), is recorded in the memory 6, advantageously a second memory unit 62, apart from the above described switching moment correction step (steps 704, 705, 706 and 707), also as the first error value of the second length T_n (T₁) of the half-cycle in the recording step 710. When a (possible) error ΔT_n+1 (ΔT₂) in the second length T_n+1 (T₂) of the next half-cycle (PA) is detected by following the above described process steps 702 - 705, it is recorded as the second error value of the second length T_n+1 (T₂) in the memory 6, preferably in the second memory unit 62, likewise in the recording step 710. The required correction is calculated for the switching moment t_a of the next half-cycle (PB). Now there are taken into account the errors of the previous half-cycles, i.e. the first error value ΔT_n (AT₁) and the second error value AT_n+1 (AT₂), by summing the errors, i.e. by forming an error sum ΔT_S = AT_n + ΔT_n+1 (ΔT_S = AT₁ + AT₂) in the error value summing step 711. The switching moment t_a of the switch kl, k2 in the switching unit 2 within the half-cycle PA is shifted, as a corrective measure, for the magnitude of the absolute value of the error, i.e. the absolute value of the error sum ΔT_S, and in the direction indicated by its signum. Hence the corrected switching moment is t_ak = t_a + ΔT_S, which is calculated in said sixth step 706. In the described example of Figure 6, the first error AT₁ has a positive signum, and the second error ΔT₂ has a negative signum, in which case the real calculated error sum ΔT_S is the difference of the errors, and in this case its signum t_a is negative, because the absolute value of the second error is larger than that of the first. In the seventh step 707, connected to another embodiment of the method according to the invention, the next switching moment t_a in the half-cycle PB is replaced by a new corrected switching moment t_ak, which is realized in the control unit 3 when controlling the switching unit 2. Thus the error caused by interference in successive half-cycles is compensated so that in said half-cycles PA, PB, the supply cycles of the load current I_K to the load K are essentially identical in length, and a DC component cannot be created.

In the above described preferred embodiment of the invention, in the power control circuit there was used history data of a detected half-cycle error, i.e. history data of the previous half-cycle error, particularly for compensating the errors of two successive half-cycles. This embodiment of the invention that utilizes history data can be particularly applied in a power control circuit using reverse phase control, when the load is an RC load, i.e. generally a capacitive and/or resistive load, as is illustrated in Figure 6.

In an embodiment of the invention, described above, a possible half-cycle error ΔT_n is compensated immediately when it is detected, in the next half-cycle. This embodiment of the invention is particularly applied in a power control circuit using forward phase control, when the load is an RL load. In this case, it is not recommendable to use the embodiment that utilizes history data, because there is the danger that the control is at the maximum adjustment (t_a = 0) driven to the end of the adjustment area, and that the adjustment range is ended (i.e. that the switching moment can only be adjusted in the opposite direction) and finally there is the threat of a possible saturation of the transformer.

A method according to the invention, where the error ΔT_n is compensated immediately, is also illustrated step by step in Figure 8, and as the curve shape of the controlled load current in Figure 7. The process steps 701 - 707 are realized as was already explained above. Error data from the previous half-cycle is not recorded in the memory, but calculated error data ΔT_n, such as AT₁, is utilized immediately in the next half-cycle, when defining the corrected switching moment t_ak. Thus the corrected switching moment is t_ak = t_a + AT_n. When the error at the half-cycle PB is corrected, by shifting the switching moment t_ak = t_a + AT₁ of the next half-cycle PA, there is measured the possible error AT₂ of the current half- cycle, and it is respectively corrected during the next half-cycle PB by shifting the switching moment t_ak = t_a + AT₂. The same procedure is continued in the successive half-cycles PA, PB,.... In the first step 701, there is defined the first length T_m of the half-cycle PA, PB, as was maintained above. In a preferred embodiment of the invention, instead of giving a constant value, the first length T_m of the half-cycle can advantageously be defined on the basis of the earlier defined second lengths T_n of the half-cycles by calculating the average T_kes of these half-cycle lengths. This is illustrated by dotted lines as an extra step 708 in Figure 8. The number n = kes of the half-cycles can be for example within the range 2 - 1000, in which case T_m = T_kes = Σ T_n /kes. As an alternative, there can be defined a certain time period, and the half-cycles occurred during said period are taken into account when calculating the average of the half- cycle lengths. This time period can be for example within the range 20 ms - 10 seconds.

In a method according to the invention, several zero points of the supply voltage, and respectively of the load current, occurring at short intervals and in succession, for instance the zero points to₂, fø ; W, t₀₄ in Figure 2, may turn out to be a problem. Owing to various occurrences of interference, it may be possible that even in the middle of a half-cycle, there are observed erroneous zero points, at least in the control unit input. In order to avoid this problem, in the most advantageous embodiment of the invention, there is applied zero point filtering.

In zero point filtering, the essential thing is that after a detected zero point is accepted, a new zero point is not accepted before a given, predetermined time has passed. Filtering is realized so that a first detected zero point t_On, such as t₀₂, is interpreted as the zero point proper, after which the registering of zero points is interrupted for a predetermined time period T_tauko, and after this time period has passed, the next zero point data t_On+i, such as t_O3, is accepted. Said time period T_tauko forms a large part of the first half-cycle, preferably a proportion within the range 70

- 95%, or most advantageously 90%, of the length of the first half-cycle T_m. When proceeding in this fashion, among several zero points that occur in succession and timewise close to each other, only the first is taken into account, whereas the rest are filtered away. The next zero point data is received at the end of the current half- cycle, i.e. when it most probably occurs. Filtering is realized as an extra step 709,

Figure 8, preferably immediately after step 702; 702a, where the load current zero points are detected.

The advanced power control circuit 1 according to the invention includes a switching moment correction unit 4, where the method according to the invention is utilized. A switching moment correction unit 4 is schematically illustrated in Figure 9, which shall next be referred to. The correction unit 4 is used for realizing the steps according to the method of the invention.

The correction unit 4 comprises the following means: means for defining the first length T_m of the half-cycle, i.e. the assumed constant length; means 7 for measuring the second length T_n of the half-cycle; means 8 for calculating the possible difference ΔT_n = T_m - T_n between said half-cycle lengths T_m, T_n, which difference can be interpreted as an error of the second length of the half-cycle; and means 11 for correcting the switching moment t_a, by taking into account the calculated difference ΔT_n as a correcting factor for the switching moment t_a when defining the switching moment t_ak proper corresponding to the phase angle during the next half- cycle, so that the switching moment t_a of the switching unit is shifted as a corrective measure for the magnitude of the defined difference ΔT_n and in a direction that compensates the error.

The advanced power control circuit according to the invention advantageously comprises means -12 for defining the first length T_m of the half-cycle that are realized so that on the basis of the lengths of the earlier defined second lengths T_n of the half-cycle, there can be calculated the average T_kes of these lengths, which average is then set as the first length T_m. of the half-cycle. As an alternative, the first length of the half-cycle is fed by suitable data input means in the correction unit 4.

In a preferred embodiment of the invention, the switching moment correction unit 4 comprises a memory 6, including at least one memory unit 61; a measurement unit 7 for measuring the second length T_n of the half-cycle; a first calculation unit 8 and a correction value defining unit 11. At least the first length T_m of the half-cycle, i.e. the constant value of the half-cycle, must be recorded in the memory 6, such as the first memory unit 61. A possible difference ΔT_n = T_m - T_n between the first length T_m and the second length T_n of the half-cycle is calculated in the first calculation unit 8. This difference is interpreted as an error of the second length T_n of the half- cycle. The interpreted error of the length T_n of the second half-cycle and the corresponding error value are submitted to the correcting value defining unit 11. In this unit, there is defined a new corrected switching moment t_ak by shifting the next switching moment t_a for the magnitude of the difference ΔT_n, and in this embodiment to the direction indicated by its signum. The corrected switching moment is submitted to the control unit 3 for controlling the switching unit 2 during the next half-cycle. In a preferred embodiment of the invention, the measurement unit 7 comprises a registering unit 71 and a time measurement unit 72.

The first length T_m of the half-cycle must be recorded, for example in connection with the implementation of the power control circuit, in the memory 6, such as the first memory unit 61, according to the process step 701. In this memory 6, there can also be recorded other data, such as various interim data that are needed in the switching moment correction unit 4. Successive zero points to_n of the load current I_κ are registered in the registering unit 71. There are needed at least two pieces of zero point data, in order to be able to proceed in the definitions according to the process step 702. It is advantageous to take the zero point data from the zero point detector to the switching moment correction unit 4. The zero point detector forms part of a regular power control circuit.

The time difference between two successive zero points t_On, to_(n-i₎ is measured in the time measurement unit 72 according to the process step 703. This time difference corresponds to the second length T_n = to_n - t_O(n-i₎ of the half-cycle. In a preferred embodiment, the time measurement unit 72 can be formed of two clocks, i.e. a first and a second clock 721, 722, that are respectively started and stopped simultaneously at detected zero points. Thus the clocks measure and register the timewise second length T_n, T_n+1 of successive half-cycles, and said length value can be read from each clock immediately after it is stopped. The half-cycle lengths T_n, T_n+i read in turn from clocks 721, 722 can be recorded for instance in the memory unit 61 to wait for the next process step.

The difference ΔT_n = T_m - T_n of the first length T_n of the half-cycle and the second length T_m of the half-cycle is calculated in the first calculation unit 8 according to the process step 704. The calculation result ΔT_n can be recorded in the memory 6, for example in the above mentioned first memory unit 61.

In a preferred embodiment of the invention, the switching moment correction unit 4 also comprises a reference unit 10 for comparing the magnitude of the absolute value of the difference ΔT_n = T_m - T_n with a predetermined small positive number p approaching zero according to the process step 705. This number p is defined in advance and recorded in a suitable memory unit, such as said first memory unit 61. The magnitude of the number p, as well as the practical arrangement of the comparison, has been discussed above, in connection with the description of the method according to the invention. If it is detected in the reference unit 10 that the absolute value of he difference ΔT_π is smaller than said small number p, the first and second lengths of the half-cycle are interpreted to be equally large. In that case any corrective measures are not started, but the registering of zero points t_On is continued in the registering unit 71, and accordingly also other described monitoring, calculation and comparison procedures in the units of the correction unit 4 are continued.

If, on the other hand, in the reference unit 10 it is detected that the absolute value of the difference ΔT_n is larger or as large as said small number p, it is interpreted as an error of the second length T_n of the half-cycle, and respectively as an error value. The value of said difference ΔT_n = T_m - T_n is recorded, together with its signum + or -, in a suitable memory unit, such as the second memory unit 62, as a detected error value of the second length T_n of the half-cycle. At the same time, the detected error is announced to the control unit 3, and the error value is given to the correction value defining unit 11.

In a preferred embodiment of the invention, a new corrected switching moment t_ak is defined in the correction value defining unit 11, to which the value of the difference ΔT_n = T_m - T_n and hence the interpreted error value of the second length T_n of the half-cycle is submitted. In the correction value defining unit 11, the signum +/- of the difference ΔT_n is used for indicating the direction of the error with respect to the first length T_m of the half-cycle. From the control unit 3, there is given a notice of the next switching moment t_a to the correction value defining unit 11. A new corrected switching moment t^ is defined in the correction value defining unit 11 according to the process step 706 by shifting the next switching moment t^ for the magnitude of the difference ΔT_n and in the direction indicated by its signum +/-, in which case the new switching moment can thus be mathematically expressed in the form t^ = t_a + ΔT_n. The corrected switching moment %_& is fed in the control unit 3 for controlling the switching unit 2 according to the process step 707, and thus it replaces the switching moment value t_a based on the recommended value of said adjustment.

In another preferred embodiment of the invention, the switching moment correction unit 4 includes a second calculation unit 9 for calculating the correction for the switching moment t_a of the next half-cycle. Now the difference obtained as a result above, i.e. the error value ΔT_n (ΔT_h cf. Figure 6) is recorded as an interim data of the second length T_n (Ti) in the memory 6, preferably in the second memory unit 62, in the recording step 710. On the basis of this error value, the switching moment already has been corrected during the half-cycle (PA). When an error ΔT_n+i (ΔT₂), i.e. a second error, in the second length T_n+1 (T₂) of the half-cycle (PA) is detected, it is calculated in the first calculation unit 8 and likewise recorded in the memory, such as the second memory unit 62. The required correction is calculated for the switching moment t_a of the next half-cycle (PB) in the same fashion as in the case of the earlier error (sixth step 706) in the correction value defining unit 11. Now there are taken into account the errors of the previous half-cycles (PB, PA), i.e. the first error and the second error (AT₁, ΔT₂) by summing the errors, i.e. by forming an error sum ΔT_S = AT_n + AT_n+1 (ΔT_S = AT₁ + AT₂) in the error value summing step 711 in the second calculation unit 9, and by giving the error sum to the correction value defining unit 11 , where the corrected switching moment t_ak is calculated. The switching moment t_a of the switch kl, k2 in the switching unit 2 within the half- cycle PA is shifted as a corrective measure for the magnitude of the error, i.e. for the absolute value of the error sum ΔT_S, and in the direction indicated by its signum. Thus the corrected switching moment is t_ak = t_a + ΔT_S, which is calculated in the correction value defining unit 11.

A preferred embodiment of the switching moment correction unit 4 further comprises means for defining the first length T_m of the half-cycle. Said means are most advantageously realized by an average calculation unit 12, where on the basis of the earlier defined second lengths T_n = t_On - t_O(n-1) of the half-cycles, there is calculated an average T^_es of these timewise lengths of the half-cycle, which average is then set as the first length T_m of the half-cycle, according to the process step 708. Now the second length values of the half-cycles are fed in from the time measurement unit 72 into the average calculation unit 12, in which there are collected length values of n = kes numbers of half-cycles, the average T_kes = Σ T_n /kes of these is calculated. Thereafter said average T^₆₈ is set as the first length T_m of the half-cycle, and it is fed into the first memory unit 6.

The most advantageous embodiment of the switching moment correction unit 4 comprises a zero point filter 13. By means of said filter, the first detected zero point to_n (n = 1) is interpreted as the zero point proper, after which the registering of zero points is interrupted for a predetermined time period T_tauko, which forms part of the first length T_m of the half-cycle, and after said time period has passed, zero point data is again received and processed according to the procedure described above, as was explained above, in connection with the process step 709. Said time period

Ttauko forms the major part, advantageously for example 70 - 95% or preferably

90% of the first length T_m of the half-cycle. The invention is not restricted to the above described embodiment only, but many modifications are possible within the scope of the inventive idea defined in the appended claims.

Claims

1. A method for improving the operation of a power control circuit, particularly a dimmer, said power control circuit being realized as a phase controlled power circuit comprising a control unit and a switching unit, which is meant to be connected in series with the load, and where the AC power supplied in the load is controlled by adjusting the phase angle of the supply voltage (VA_C) during each half-cycle (PA, PB), characterized in that in the method:

- there is defined (701) a first length (T_1n) of the half-cycle;

- there is measured (702, 703) a second length (T_n) of the half-cycle;

- there is defined (704) a possible difference (ΔT_n = T_m - T_n) of the first length

(T_1n)) and the second length (T_n) of the half-cycle, which difference is interpreted as an error of the second length of the half-cycle; and

- the defined error (ΔT_n = T_m - T_n) is taken into account as a correcting factor of the switching moment (t_a), when defining the switching moment (t_ak) proper corresponding to the phase angle, during the next half-cycle so that the switching moment (t_a) of the switching unit is shifted as a corrective measure for the magnitude of the defined difference (ΔT) and in a direction that compensates the error.

2. A method according to claim 1 for improving the operation of a power control circuit, particularly a dimmer, characterized in that the first length (T_m) of the half- cycle is defined on the basis of the second lengths of the earlier defined half-cycles (T_n), by calculating an average (T_kes) of these half-cycle lengths, and by setting said average as the first length of the half-cycle.

3. A method according to claim 1 or 2 for improving the operation of a power control circuit, particularly a dimmer, characterized in that at least two successive zero points (t_0n5 where n = 1, 2, 3,...) of the load current (I_x) are registered (702), and that there is defined (703) a second length (T_n = t_On - to_(n-i₎)_s of the half-cycle, which second length is the time difference (T_n) between two successive zero points

4. A method according to any of the preceding claims for improving the operation of a power control circuit, particularly a dimmer, characterized in that in the method: - the absolute value of the defined error (ΔT_n) is compared (705) with a predetermined positive small number (p) approaching zero and

- if the absolute value of the difference (ΔT_n) is smaller than said small number, the lengths of the first and second half-cycle are interpreted to be equally large, whereafter the process proceeds to define the second length

(T_n) of the next half-cycle, and the above described steps are repeated,

- if the absolute value of the difference (ΔT_n) is larger or as large as the small number, it is interpreted as an error of the second length (T_n) of the second half-cycle and respectively as an error value,

- when an error in the second length of the second half-cycle (T_n) is detected, the signum (+/-) of the defined difference (ΔT_n) is used for indicating the direction of the difference with respect to the first length of the first half-cycle (T_m), after which

- the next switching moment (t_a) of the switching unit is shifted as a corrective measure for the magnitude of the defined difference (ΔT_n), and in the direction (706, 707) indicated by its signum.

5. A method according to any of the preceding claims for improving the operation of a power control circuit, particularly a dimmer, characterized in that the difference is calculated for two successive half-cycles (AT₁ , ΔT₂), and their sum (ΔT_S) is taken into account as an error value during the next half-cycle when defining the switching moment (t_ak) proper.

6. A method according to any of the preceding claims for improving the operation of a power control circuit, particularly a dimmer, characterized in that the process includes filtering of the zero points, so that the first detected zero point (t_On) is interpreted as the zero point proper, after which the registering of zero points is interrupted for a predetermined time period (T_tauko) of the first length (T_m) of the half-cycle, and after said time period has passed, the next zero point data is accepted.

7. A method according to claim 6 for improving the operation of a power control circuit, particularly a dimmer, characterized in that said time period (T_tauk0) forms a large part, advantageously within the range 70 - 95% or preferably 90% of the first length (T_1n) of the half-cycle.

8. An advanced power control circuit, particularly a dimmer, comprising a switching unit (2) and a control unit (3), which is meant to be connected in series with the load (K), under the control of which control unit, by means of said switching unit, the AC power supplied in the load is controlled by adjusting the phase angle during each half-cycle (PA, PB) of the supply voltage, characterized in that the power control circuit comprises a switching moment correction unit (4), provided with:

- means for defining a first length (T_m) of the half-cycle;

- means for measuring a second length (T_n) of the half-cycle, and

- means for calculating a possible difference (ΔT_n = T_m - T_n) in said half-cycle lengths (T_n,, T_n), which difference is interpreted as an error of the second length of the half-cycle; and

- means for correcting the switching moment (t_a) by taking into account the calculated difference (AT_n) as a correcting factor of the switching moment (t_a) when defining the switching moment (t_ak) proper, corresponding to the phase angle, during the next half-cycle, so that the switching moment (t_a) of the switching unit is shifted as a corrective measure for the magnitude of the defined difference (AT_n) and in a direction that compensates the error.

9. An advanced power control circuit, particularly a dimmer, according to claim 8, characterized in that the switching moment correction unit (4) comprises means for defining a first length (T_m) of the half-cycle, and is realized on the basis of the earlier defined second lengths (T_n) of the half-cycle, there is calculated an average (T_kes) of these lengths, which average is then set as the first length (T_m) of the half- cycle.

10. An advanced power control circuit, particularly a dimmer, according to claim 8 or 9, characterized in that the switching moment correction unit (4) also comprises:

- a first memory unit (61), where at least the first length (T_n) of the half-cycle shall be recorded;

- a measurement unit (7) for measuring the second length (T_n) of the half-cycle;

- a first calculation unit (8) for calculating the difference (AT_n = T_n, - T_n) between the first length (T_m) of the half-cycle and the second length (T_n) of the half-cycle, said difference being interpreted as an error of the second length of the half-cycle; and

- a correction value defining unit (11), in which the interpreted error of the second length (T_n) of the half-cycle and the corresponding error value are fed, where a new corrected switching moment (t_k) is defined by shifting the next switching moment (t_a) for the magnitude of the difference (ΔT_n) and in the direction indicated by its signum (+/-), and which corrected switching moment is given to the control unit (3) for controlling the switching unit (2) during the next half-cycle.

11. An advanced power control circuit, particularly a dimmer, according to any of the preceding claims 8 - 10, characterized in that the measurement unit (7) includes:

- a registering unit (71) for registering the zero points (t_On) of the load current (I_L), and

- a time measurement unit (72) for measuring the time difference between two successive zero points (to_n, t_O(n-1)), said time difference being considered to correspond to the second length (T_n = t_On - to_(n-1)) of the half-cycle.

12. An advanced power control circuit, particularly a dimmer, according to any of the preceding claims 8 - 11, characterized in that the switching moment correction unit (4) also includes a reference unit (10) for comparing the magnitude of the absolute value of the difference (ΔT_n = T_m - T_n) with a predetermined small positive number (p) approaching zero, so that

- if the absolute value of the difference (ΔT_n) is smaller than said small number (p), the first and second lengths of the half-cycle are interpreted as equally large, and

- if the absolute value of the difference (AT_n) is larger or equally large as said small number, it is interpreted as an error of the second length (T_n) of the half-cycle and respectively an error value.

13. An advanced power control circuit, particularly a dimmer, according to any of the preceding claims 8 - 12, characterized in that the switching moment correction unit (4) also includes a second calculation unit (9) for calculating the correction for the next switching moment (t_a) of the half-cycle, in which calculation unit there are fed the errors (AT₁, AT₂) of the second lengths of said successive half-cycles and summed up for creating an error sum (ΔT_S = ΔTi+ΔT₂), which error sum is interpreted as the total error of the second length of the successive half-cycles, said total error being given as an error value to the correction value defining unit (11), where a new corrected switching moment (t_ak) is defined by shifting the next switching moment (t_a) for the magnitude of the error sum (ΔT_S), and in a direction indicated by its signum (+/-), said corrected switching moment being given to the control unit (3) for controlling the switching unit (2) during the next half-cycle.

14. An advanced power control circuit, particularly a dimmer, according to any of the preceding claims 8 - 13, characterized in that the switching moment correction unit (4) includes a zero point filter (13), by which the first detected zero point (t_On) is interpreted as the zero point proper, after which the registering of zero points is interrupted for a predetermined time period (T_taUko) of the first length (T_m) of the half-cycle, and after said period has passed, the next zero point data is accepted.

15. An advanced power control circuit according to claim 14, characterized in that said time period (T_tauk0) forms a large part, such as advantageously 70 - 95% or preferably 90%, of the first length (T_m) of the half-cycle.