WO2006137197A1 - Semiconductor integrated circuit device and regulator using the same - Google Patents

Semiconductor integrated circuit device and regulator using the same Download PDF

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Publication number
WO2006137197A1
WO2006137197A1 PCT/JP2006/304984 JP2006304984W WO2006137197A1 WO 2006137197 A1 WO2006137197 A1 WO 2006137197A1 JP 2006304984 W JP2006304984 W JP 2006304984W WO 2006137197 A1 WO2006137197 A1 WO 2006137197A1
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Prior art keywords
concentration
type
region
low
power transistor
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Application number
PCT/JP2006/304984
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French (fr)
Japanese (ja)
Inventor
Yoshiyuki Hojo
Hirotaka Nakabayashi
Original Assignee
Rohm Co., Ltd
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Publication date
Application filed by Rohm Co., Ltd filed Critical Rohm Co., Ltd
Priority to CN2006800126376A priority Critical patent/CN101160654B/en
Priority to US11/913,805 priority patent/US7872459B2/en
Publication of WO2006137197A1 publication Critical patent/WO2006137197A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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    • G—PHYSICS
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    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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Definitions

  • the present invention relates to a semiconductor integrated circuit device provided with a power transistor and a regulator using the same.
  • a semiconductor integrated circuit device (so-called power IC) provided with a power transistor may be required to pass a relatively large current through the power transistor according to its specifications.
  • one end of the power transistor is connected in parallel to a plurality of pads, and each pad is wire bonded to a common frame (external terminal).
  • a configuration in which current is shared through a plurality of bonding wires has been adopted.
  • Patent document 1 JP-A-9-266226
  • the conventional semiconductor integrated circuit device shown in FIG. 5 can reduce the resistance of the bonding wire that electrically connects the pad and the frame, thereby increasing the allowable current flow rate of the device. Is possible.
  • the conventional semiconductor integrated circuit device has a problem that it is difficult to detect disconnection of the bonding wires connected in parallel.
  • an object of the present invention is to provide a semiconductor integrated circuit device capable of easily detecting a disconnection of bonding wires connected in parallel and a regulator using the semiconductor integrated circuit device.
  • a semiconductor integrated circuit device includes ⁇ power transistors that are controlled to be opened and closed by the same control signal, and ⁇ pieces of transistors connected to one end of the power transistor.
  • a semiconductor chip comprising: a first pad; ⁇ second pads connected to each other end of the power transistor; and a control signal generating means for generating the control signal; And a second frame in which the second pads are commonly connected via bonding wires, respectively (first configuration).
  • the power transistor may be configured as a bipolar transistor (second configuration).
  • the power transistor includes a low-concentration ⁇ -type well region formed on a low-concentration ⁇ -type substrate; and the low-concentration ⁇ -type well region.
  • a high-concentration ⁇ -type buried region carried below, and a high-concentration ⁇ -type formed so as to be in contact with the high-concentration ⁇ -type buried region from the upper surface to the lower surface of the low-concentration ⁇ -type well region
  • a sinker region formed in the high-concentration ⁇ -type sinker region and connected to an output terminal of the control signal generating means as a base of the power transistor; formed in the low-concentration ⁇ -type well region;
  • As an emitter of the power transistor A first high-concentration p-type region connected to the first pad; and formed in the low-concentration n-type well region so as to sandwich the high-concentration p-type emitter region, and connected to the second pad as a collector of the power transistor
  • the power transistor includes a low-concentration n-type well region formed on a low-concentration p-type substrate; and the low-concentration n-type well region.
  • the power transistor may be a field effect transistor (fifth configuration).
  • the power transistor includes: a first low-concentration n-type well region formed on a low-concentration P-type substrate; and a first low-concentration n-type well region. A high concentration n-type buried region carried below; a second low concentration n-type well region formed in the first low concentration n-type well region; and a second low concentration n-type well region.
  • second low Configuration of the structure is the p-channel type field effect transistor formed in (6; formed in degrees n-type Ueru region, the high concentration n-type back gate region as a back gate of the power transistor is connected to the first pad )
  • the power transistor is formed on a low-concentration p-type substrate, and is connected to a first pad as a drain of the power transistor.
  • a high-concentration n-type source region formed on the low-concentration p-type substrate and connected to a second pad as a source of the power transistor; and the high-concentration n-type drain region and the high-concentration n- type source region
  • a gate region formed between and connected to the output terminal of the driver circuit as a gate of the power transistor; formed on the low concentration P-type substrate and connected to a second pad as a back gate of the power transistor;
  • the regulator according to the present invention is connected between the semiconductor integrated circuit device having any one of the first to seventh configurations, the first frame to which the input voltage is applied, and the ground terminal.
  • the control signal generation means generates the control signal so that the feedback voltage matches a predetermined reference voltage (eighth configuration).
  • the semiconductor integrated circuit device according to the present invention and the regulator using the semiconductor integrated circuit device can easily detect disconnection of the bonding wires connected in parallel.
  • FIG. 1 is a circuit diagram showing an embodiment of a series regulator using a semiconductor integrated circuit device according to the present invention.
  • FIG. 2 is a longitudinal sectional view of a semiconductor chip CHIP1.
  • FIG. 3 is a diagram for explaining the proper use of power transistor elements.
  • FIG. 4 is another longitudinal sectional view of the semiconductor chip CHIP1.
  • FIG. 5 is a schematic configuration diagram showing a conventional example of a semiconductor integrated circuit device. Explanation of symbols
  • T11, T12 1st pad (Each Plitter, ⁇ 2)
  • Rl resistance (feedback voltage generator)
  • FIG. 1 is a circuit diagram showing an embodiment of a series regulator using a semiconductor integrated circuit device according to the present invention.
  • the series regulator of the present embodiment includes a semiconductor integrated circuit device IC 1, smoothing capacitors Cl and C 2, and resistors R 1 and R 2.
  • the semiconductor integrated circuit device IC1 is formed by packaging a semiconductor chip CHIP1 and first to third frames (external terminals) FR1 to FR3.
  • the first frame FR 1 to which the input voltage Vin is applied outside the semiconductor integrated circuit device IC 1 is grounded via a smoothing capacitor C 1.
  • the second frame FR2 from which the output voltage Vout is drawn is grounded via the smoothing capacitor C2, while a series connection circuit consisting of resistors Rl and R2 (feedback that generates a feedback voltage Vfb corresponding to the output voltage Vout). It is also grounded via the voltage generation circuit. Note that the connection node of the resistors Rl and R2 serving as the output terminal of the feedback voltage Vfb is connected to the frame T3 of the semiconductor integrated circuit device IC1.
  • the semiconductor chip CHIP1 includes pnp bipolar transistors Pl and P2, first pads Tl 1 and T12, second pads ⁇ 21 and ⁇ 22, third pad ⁇ 3, driver circuit DRV, and error amplification.
  • Unit ERR and DC voltage source E1 are integrated.
  • the emitters of the transistors Pl and P2 are connected to the first pads Tll and T12, respectively.
  • the first pads ⁇ 11 and ⁇ 12 are commonly connected to the first frame FR1 through bonding wires Wll and W12, respectively.
  • the collectors of the transistors Pl and P2 are connected to the second pads T21 and ⁇ 22, respectively.
  • the second nodes ⁇ 21 and ⁇ 22 are commonly connected to the second frame FR2 via bonding wires W21 and W22, respectively.
  • the bases of the transistors Pl and IV2 are both connected to the control signal output terminal of the driver circuit DRV.
  • the inverting input terminal (-) of the error amplifier ERR is connected to the third pad T3.
  • the third pad T3 is connected to the third frame FR3 via a bonding wire W3.
  • the non-inverting input terminal (+) of the error amplifier ERR is connected to the positive terminal of the DC voltage source E1 (such as a bandgap power supply circuit), and the target value of the output voltage Vout is set to the non-inverting input terminal (+). Reference voltage Vref for setting is applied.
  • the negative terminal of the DC voltage source E1 is grounded .
  • the output terminal of the error amplifier ERR is connected to the error voltage signal input terminal of the driver circuit DRV.
  • the semiconductor chip CHIP1 includes various protection circuits (an overcurrent protection circuit that prevents IC destruction due to output short-circuiting, etc., an overvoltage protection circuit that prevents surge destruction of the power supply, or Temperature protection circuits that prevent thermal destruction due to overload conditions, etc.) are also incorporated, but these protection circuits are not directly related to the present invention, so illustration and detailed description thereof are omitted. .
  • the error amplifier ERR amplifies the difference between the feedback voltage Vfb and the reference voltage Vref and outputs it to the driver circuit DRV.
  • the driver circuit DRV controls opening and closing of the transistors Pl and P2 so that the error voltage signal becomes small. More specifically, the driver circuit DRV generates a control signal for the transistors Pl and P2 to increase the output voltage Vout when the feedback voltage Vfb is lower than the reference voltage Vref, and conversely, the feedback voltage Vfb is the reference voltage. If the Vre beam is high, the control signals for the transistors Pl and P2 are generated so as to lower the output voltage Vout. By such an operation, a desired output voltage Vout can be generated from the input voltage Vin.
  • the transistors Pl and P2 are provided in the parallel IJ, and the gap between the first frame FR1 and the second frame FR2 is provided.
  • Two independent current paths (wire Wl 1—first pad Tl 1 -transistor P1—second pad T21—first path consisting of wire W21 and wire W12—first pad T12—transistor P2—second pad T22 -The configuration connected by the second path consisting of the wire W22, that is, the configuration sharing the current through the first and second paths described above.
  • the resistance of the bonding wire that electrically connects the pad and the frame can be reduced, so that the allowable current amount of the device is increased. It becomes possible.
  • the element size of the transistors Pl and P2 is half that of the power transistor that should be originally provided (twice the on-resistance), so that the chip size is not increased.
  • the path resistance value when the wire is broken rises twice as much as when the wire is not broken. Therefore, if the configuration of the present embodiment is adopted, it is easy to break the wire even if either the emitter side or the collector side of the bonding wires connected in parallel can be disconnected, and the allowable current amount of the device can be increased. Can be detected.
  • FIG. 2 is a longitudinal sectional view of the semiconductor chip CHIP1.
  • the transistors Pl, P2 are low-concentration n-type [n-] well regions 3a formed on the low-concentration P-type [P-] substrate 1. 3b; isolation region for isolating transistors PI and P2 (high-concentration p-type [p +] region) 4; and low-concentration n-type [n—] well regions 3a and 3b High-concentration n-type [n +] loading regions 2a and 2b; low-concentration n-type [n-] well regions 3a and 3b from the top to the bottom n-type [n +] embedding region 2a, High-concentration n-type [n +] sinker regions 5a and 5b formed in contact with 2b; high-concentration n-type [n +] sinker regions 5a and 5b, and driver circuit DRV as the base of transistors Pl and P2 N-type [n ++] base regions 6a and 6b connected to
  • semiconductor chip 1 having the above structure is formed through first to sixth processes described below.
  • n-type impurity diffusion is performed on the surface layer of the low-concentration p-type [p_] substrate 1, and high-concentration n-type [n +] loading regions 2a, 2b (so-called no- A buried layer) is formed.
  • the high concentration n-type [n +] loading regions 2a and 2b are Formed to lower the resistance of time.
  • a low-concentration n-type [n-] silicon single crystal layer is epitaxially grown on the low-concentration p-type [p-] substrate 1 in the gas phase.
  • n-type impurities are in contact with the high-concentration n-type [n +] buried regions 2a and 2b from the upper surface to the lower surface of the low-concentration n-type [n_] tool regions 3a and 3b. Diffusion is performed to form high-concentration n-type [n +] sinker regions 5a and 5b.
  • the high-concentration n-type [n +] sinker regions 5a and 5b are formed to reduce the resistance when the base is pulled out.
  • p-type impurity diffusion is performed in the low-concentration n-type [n-] well regions 3a and 3b, and the high-concentration P-type [P +] emitter regions 7a and 7b (transistors Pl and P2 Equivalent to the emitter).
  • the first high-concentration P-type [P +] collector regions 8a and 8b and the second high-concentration p-type [p +] Collector regions 9a and 9b are formed.
  • the transistors Pl and P2 have the above structure, so that the element isolation is completely performed, but the parallel transistor pairing characteristics without greatly changing the layout area can be arranged well. it can. Also, since the elements are completely separated, the same power transistor can be used for 1 element / 2 elements (see Fig. 3).
  • the series regulator using the semiconductor integrated circuit device according to the present invention has been described as an example.
  • the configuration and application target of the present invention are limited to this.
  • semiconductor integrated circuit devices that handle large currents (for example, amplifiers) And a comparator or a power transistor alone).
  • the configuration of the present invention can be variously modified within the scope of the present invention in addition to the above-described embodiment.
  • the number of power transistors in parallel may be three or more, npn bipolar transistors (see Fig. 4 (a)), p-channel or n-channel field effect transistors (Fig. 4). (b) or see Fig. 4 (c)).
  • the power transistor includes a low-concentration n-type well region formed on a low-concentration p-type substrate; A high-concentration n-type sinker formed so as to be in contact with the high-concentration n-type embedded region from the upper surface to the lower surface of the low-concentration n-type well region; Formed in the high-concentration n-type sinker region and connected to the first pad as a collector of the power transistor; and formed in the low-concentration n-type drain region.
  • the power transistor includes a first low-concentration n-type well region formed on a low-concentration p-type substrate; and a lower portion of the first low-concentration n-type well region.
  • a high concentration n-type buried region encased in; a second low concentration n-type well region formed in the first low-concentration n-type well region; and a second low-concentration n-type well region.
  • the power transistor is formed on a low-concentration p-type substrate, and is connected to a first pad as a drain of the power transistor.
  • a high-concentration n-type source region formed on the low-concentration p-type substrate and connected to a second pad as a source of the power transistor; and the high-concentration n-type drain region and the high-concentration n-type source region A gate region formed between and connected to the output terminal of the driver circuit as a gate of the power transistor; formed on the low-concentration p-type substrate and connected to a second pad as a back gate of the power transistor A high-concentration p-type back gate region, and an n-channel field effect transistor formed by; At that time, each element may be isolated in a low-concentration n-type element isolation region.
  • the present invention is a technique useful for improving the reliability of a semiconductor integrated circuit device handling a large current and a regulator using the same.

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Abstract

A semiconductor integrated circuit device (IC1) comprises a semiconductor chip (CHIP1), a first frame lead (FR1), and a second frame lead (FR2). The semiconductor chip (CHIP1) includes common-base transistors (P1, P2), pads (T11, T12) connected to the respective emitters of the common-base transistors (P1, P2), pads (T21, T22) connected to the respective collectors of the common-base transistors (P1, P2), and a means (DRV, ERR, E1) for generating a base signal. The pads (T11, T12) are connected through the respective bonding wires (W11, W12) to the first frame lead (FR1). The pads (T21, T22) are connected through the respective bonding wires (W21, W22) to the second frame lead (FR2). This structure can easily detect breaking of the bonding wires connected in parallel.

Description

明 細 書  Specification
半導体集積回路装置及びこれを用いたレギユレータ  Semiconductor integrated circuit device and regulator using the same
技術分野  Technical field
[0001] 本発明は、パワートランジスタを備えた半導体集積回路装置及びこれを用いたレギ ユレータに関するものである。  The present invention relates to a semiconductor integrated circuit device provided with a power transistor and a regulator using the same.
背景技術  Background art
[0002] 従来より、パワートランジスタを備えた半導体集積回路装置 (いわゆる、パワー IC) には、その仕様に応じて、前記パワートランジスタに比較的大きな電流を流すことが 要求される場合がある。このような場合、従来の半導体集積回路装置では、図 5に示 す通り、パワートランジスタの一端を複数のパッドに並列接続し、各パッドを共通のフ レーム（外部端子）に各々ワイヤボンディングする構成、言い換えれば、複数のボン デイングワイヤを介して電流を分担する構成が採用されていた。  Conventionally, a semiconductor integrated circuit device (so-called power IC) provided with a power transistor may be required to pass a relatively large current through the power transistor according to its specifications. In such a case, in the conventional semiconductor integrated circuit device, as shown in FIG. 5, one end of the power transistor is connected in parallel to a plurality of pads, and each pad is wire bonded to a common frame (external terminal). In other words, a configuration in which current is shared through a plurality of bonding wires has been adopted.
[0003] なお、本願発明に関連する従来技術としては、多数のユニットセルを並列配置した 大電流用半導体デバイスにおいて、この半導体デバイスの少なくとも一方の主電極 領域が、少なくとも 2以上の独立したボンディングパッド領域に分割されたチップ構造 とし、このボンディングパッドに、それぞれ独立したボンディングワイヤの一端を接続し 、このボンディングワイヤの他端を共通の外部端子に接続する半導体装置が開示' 提案されている (例えば、特許文献 1を参照）。  [0003] It should be noted that, as a related art related to the present invention, in a large current semiconductor device in which a large number of unit cells are arranged in parallel, at least one main electrode region of the semiconductor device has at least two independent bonding pads. A semiconductor device having a chip structure divided into regions, one end of each independent bonding wire connected to each bonding pad, and the other end of the bonding wire connected to a common external terminal has been disclosed (for example, proposed) , See Patent Document 1).
特許文献 1 :特開平 9一 266226号公報  Patent document 1: JP-A-9-266226
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0004] 確かに、図 5に示す従来の半導体集積回路装置であれば、パッドとフレームとを電 気的に接続するボンディングワイヤの抵抗を減らすことができるので、装置の許容電 流量を高めることが可能である。 [0004] It is true that the conventional semiconductor integrated circuit device shown in FIG. 5 can reduce the resistance of the bonding wire that electrically connects the pad and the frame, thereby increasing the allowable current flow rate of the device. Is possible.
[0005] し力、しながら、上記従来の半導体集積回路装置には、並列接続されたボンディング ワイヤの断線を検出することが困難である、という課題があった。 However, the conventional semiconductor integrated circuit device has a problem that it is difficult to detect disconnection of the bonding wires connected in parallel.
[0006] 上記の課題について、図 5の場合を例に挙げて具体的に説明する。ワイヤ 1本の抵 抗値を 0· 10[ Ω ]とした場合、チップ'フレーム間における並列ワイヤの合成抵抗値 は、いずれのワイヤも断線していなければ 0· 05[ Ω ]となり、いずれ力 1本のワイヤが 断線していれば 0. 10[ Ω ]となる。すなわち、ワイヤの断線/非断線に応じた抵抗値 の変動分は 0. 05[ Ω ]と微少であり、ワイヤの断線検出に際しては、当該微少な抵抗 値変動分を正確に検出する必要があった。しかし、パワートランジスタのオン抵抗値 には、 ± 30%程度の製造誤差 (例えば、設計上のオン抵抗値 0. 5 [ Ω ]に対して、土 0. 15[ Ω ])が存在し、ワイヤの断線 Ζ非断線に応じた抵抗値変動分が当該誤差範 囲に含まれてしまうため、その断線検出は非常に困難であった。 [0006] The above problem will be specifically described by taking the case of FIG. 5 as an example. 1 piece of wire If the resistance value is 0 · 10 [Ω], the combined resistance value of the parallel wires between the chip and the frame is 0 · 05 [Ω] if no wires are disconnected, and each wire has one force. If it is disconnected, it becomes 0.10 [Ω]. In other words, the amount of change in resistance corresponding to wire breakage / non-breakage is as small as 0.05 [Ω]. When wire breakage is detected, it is necessary to accurately detect the minute resistance value change. It was. However, there is a manufacturing error of about ± 30% in the on-resistance value of the power transistor (for example, 0.15 [Ω] on earth compared to 0.5 [Ω] on the design on-resistance value). Disconnection Ζ Resistance fluctuations corresponding to non-disconnection are included in the error range, so it was very difficult to detect disconnection.
[0007] 本発明は、上記の問題点に鑑み、並列接続されたボンディングワイヤの断線を容 易に検出することが可能な半導体集積回路装置及びこれを用いたレギユレ一タを提 供することを目的とする。 In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit device capable of easily detecting a disconnection of bonding wires connected in parallel and a regulator using the semiconductor integrated circuit device. And
課題を解決するための手段  Means for solving the problem
[0008] 上記目的を達成するために、本発明に係る半導体集積回路装置は、同一の制御 信号によって開閉制御される η個のパワートランジスタと、前記パワートランジスタの各 一端に接続される η個の第 1パッドと、前記パワートランジスタの各他端に接続される η個の第 2パッドと、前記制御信号を生成する制御信号生成手段と、を備えた半導体 チップと；第 1パッドが各々ボンディングワイヤを介して共通接続される第 1フレームと； 第 2パッドが各々ボンディングワイヤを介して共通接続される第 2フレームと；を有して 成る構成 (第 1の構成）としている。  In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes η power transistors that are controlled to be opened and closed by the same control signal, and η pieces of transistors connected to one end of the power transistor. A semiconductor chip comprising: a first pad; η second pads connected to each other end of the power transistor; and a control signal generating means for generating the control signal; And a second frame in which the second pads are commonly connected via bonding wires, respectively (first configuration).
[0009] なお、上記第 1の構成から成る半導体集積回路装置において、前記パワートランジ スタは、ノ イポーラトランジスタである構成（第 2の構成）にするとよい。  [0009] Note that in the semiconductor integrated circuit device having the first configuration, the power transistor may be configured as a bipolar transistor (second configuration).
[0010] また、上記第 2の構成から成る半導体集積回路装置において、前記パワートランジ スタは、低濃度 ρ型基板に形成された低濃度 η型ゥエル領域と；前記低濃度 η型ゥェ ノレ領域の下方に坦め込まれた高濃度 η型埋込領域と；前記低濃度 η型ゥエル領域の 上面から下面に至るまで前記高濃度 η型埋込領域と接するように形成された高濃度 η 型シンカー領域と；前記高濃度 η型シンカー領域に形成され、前記パワートランジスタ のベースとして前記制御信号生成手段の出力端に接続される高々濃度 η型ベース 領域と；前記低濃度 η型ゥエル領域に形成され、前記パワートランジスタのェミッタとし て第 1パッドに接続される第 1高濃度 p型領域と;前記高濃度 p型ェミッタ領域を挟む ように前記低濃度 n型ゥエル領域に形成され、前記パワートランジスタのコレクタとして 第 2パッドに接続される第 1、第 2高濃度 p型コレクタ領域と；で形成される pnp型バイ ポーラトランジスタである構成（第 3の構成）にするとよい。 [0010] In the semiconductor integrated circuit device having the second configuration, the power transistor includes a low-concentration η-type well region formed on a low-concentration ρ-type substrate; and the low-concentration η-type well region. A high-concentration η-type buried region carried below, and a high-concentration η-type formed so as to be in contact with the high-concentration η-type buried region from the upper surface to the lower surface of the low-concentration η-type well region A sinker region; formed in the high-concentration η-type sinker region and connected to an output terminal of the control signal generating means as a base of the power transistor; formed in the low-concentration η-type well region; As an emitter of the power transistor A first high-concentration p-type region connected to the first pad; and formed in the low-concentration n-type well region so as to sandwich the high-concentration p-type emitter region, and connected to the second pad as a collector of the power transistor The first and second high-concentration p-type collector regions, and the pnp bipolar transistor formed by (a third configuration) may be used.
[0011] また、上記第 2の構成から成る半導体集積回路装置において、前記パワートランジ スタは、低濃度 p型基板に形成された低濃度 n型ゥエル領域と；前記低濃度 n型ゥェ ノレ領域の下方に坦め込まれた高濃度 n型埋込領域と；前記低濃度 n型ゥエル領域の 上面から下面に至るまで前記高濃度 n型埋込領域と接するように形成された高濃度 n 型シンカー領域と；前記高濃度 n型シンカー領域に形成され、前記パワートランジスタ のコレクタとして第 1パッドに接続される接続される高々濃度 n型コレクタ領域と；前記 低濃度 n型ゥエル領域に形成される低濃度 p型ゥエル領域と；前記低濃度 p型ゥエル 領域に形成され、前記パワートランジスタのベースとして前記ドライバ回路の出力端 に接続される高濃度 P型ベース領域と；前記低濃度 p型ゥエル領域に形成され、前記 パワートランジスタのェミッタとして第 2パッドに接続される高濃度 n型ェミッタ領域と； で形成される npn型バイポーラトランジスタである構成（第 4の構成）にしてもよい。 [0011] In the semiconductor integrated circuit device having the second configuration, the power transistor includes a low-concentration n-type well region formed on a low-concentration p-type substrate; and the low-concentration n-type well region. A high-concentration n-type buried region carried below the high-concentration n-type region; and a high-concentration n-type formed so as to contact the high-concentration n-type buried region from the upper surface to the lower surface of the low-concentration n-type well region a sinker region; formed on the low concentration n-type Ueru region; formed on the heavily doped n-type sinker region, at most a concentration n-type collector region is connected is connected to the first pad as a collector of said power transistor A low-concentration p-type well region; a high-concentration P-type base region formed in the low-concentration p-type well region and connected to an output terminal of the driver circuit as a base of the power transistor; A high-concentration n-type emitter region formed in the region and connected to the second pad as an emitter of the power transistor may be configured as an npn-type bipolar transistor (fourth configuration).
[0012] 或いは、上記第 1の構成から成る半導体集積回路装置において、前記パワートラン ジスタは、電界効果トランジスタである構成（第 5の構成）にしてもよい。  [0012] Alternatively, in the semiconductor integrated circuit device having the first configuration, the power transistor may be a field effect transistor (fifth configuration).
[0013] なお、第 5の構成から成る半導体集積回路装置において、前記パワートランジスタ は、低濃度 P型基板に形成された第 1低濃度 n型ゥエル領域と；第 1低濃度 n型ゥエル 領域の下方に坦め込まれた高濃度 n型埋込領域と；第 1低濃度 n型ゥエル領域に形 成された第 2低濃度 n型ゥエル領域と；第 2低濃度 n型ゥエル領域に形成され、前記パ ワートランジスタのソースとして第 1パッドに接続される高濃度 p型ソース領域と；第 2低 濃度 n型ゥヱル領域に形成され、前記パワートランジスタのドレインとして第 2パッドに 接続される高濃度 p型ドレイン領域と；前記高濃度 p型ソース領域と前記高濃度 p型ド レイン領域との間に跨って形成され、前記パワートランジスタのゲートとして前記ドライ バ回路の出力端に接続されるゲート領域と；第 2低濃度 n型ゥエル領域に形成され、 前記パワートランジスタのバックゲートとして第 1パッドに接続される高濃度 n型バック ゲート領域と；で形成される pチャネル型電界効果トランジスタである構成（第 6の構成 )にするとよレ、。 In the semiconductor integrated circuit device having the fifth configuration, the power transistor includes: a first low-concentration n-type well region formed on a low-concentration P-type substrate; and a first low-concentration n-type well region. A high concentration n-type buried region carried below; a second low concentration n-type well region formed in the first low concentration n-type well region; and a second low concentration n-type well region. A high concentration p-type source region connected to the first pad as the source of the power transistor; and a high concentration connected to the second pad as the drain of the power transistor formed in the second low concentration n-type wall region a p-type drain region; a gate region formed between the high-concentration p-type source region and the high-concentration p-type drain region and connected to the output terminal of the driver circuit as a gate of the power transistor And second low Configuration of the structure is the p-channel type field effect transistor formed in (6; formed in degrees n-type Ueru region, the high concentration n-type back gate region as a back gate of the power transistor is connected to the first pad )
[0014] また、第 5の構成から成る半導体集積回路装置において、前記パワートランジスタ は、低濃度 p型基板に形成され、前記パワートランジスタのドレインとして第 1パッドに 接続される高濃度 n型ドレイン領域と;前記低濃度 p型基板に形成され、前記パワート ランジスタのソースとして第 2パッドに接続される高濃度 n型ソース領域と；前記高濃度 n型ドレイン領域と前記高濃度 n型ソース領域との間に跨って形成され、前記パワート ランジスタのゲートとして前記ドライバ回路の出力端に接続されるゲート領域と；前記 低濃度 P型基板に形成され、前記パワートランジスタのバックゲートとして第 2パッドに 接続される高濃度 p型バックゲート領域と；で形成される nチャネル型電界効果トラン ジスタである構成（第 7の構成）にしてもよい。 [0014] In the semiconductor integrated circuit device having the fifth structure, the power transistor is formed on a low-concentration p-type substrate, and is connected to a first pad as a drain of the power transistor. A high-concentration n-type source region formed on the low-concentration p-type substrate and connected to a second pad as a source of the power transistor; and the high-concentration n-type drain region and the high-concentration n- type source region A gate region formed between and connected to the output terminal of the driver circuit as a gate of the power transistor; formed on the low concentration P-type substrate and connected to a second pad as a back gate of the power transistor; A high-concentration p-type back gate region and an n-channel field effect transistor (seventh configuration) formed by
[0015] また、本発明に係るレギユレータは、上記第 1〜第 7いずれかの構成から成る半導 体集積回路装置と、入力電圧が印加される第 1フレームと接地端との間に接続される 入力平滑コンデンサと、出力電圧が引き出される第 2フレームと接地端との間に接続 される出力平滑コンデンサと、前記出力電圧に応じた帰還電圧を生成する帰還電圧 生成手段と、を有して成り、前記制御信号生成手段にて、前記帰還電圧が所定の基 準電圧と一致するように、前記制御信号の生成を行う構成 (第 8の構成）とされている [0015] Further, the regulator according to the present invention is connected between the semiconductor integrated circuit device having any one of the first to seventh configurations, the first frame to which the input voltage is applied, and the ground terminal. An input smoothing capacitor, an output smoothing capacitor connected between the second frame from which the output voltage is drawn and the ground terminal, and feedback voltage generating means for generating a feedback voltage corresponding to the output voltage. And the control signal generation means generates the control signal so that the feedback voltage matches a predetermined reference voltage (eighth configuration).
発明の効果 The invention's effect
[0016] 上記したように、本発明に係る半導体集積回路装置及びこれを用いたレギユレータ であれば、並列接続されたボンディングワイヤの断線を容易に検出することが可能と なる。  As described above, the semiconductor integrated circuit device according to the present invention and the regulator using the semiconductor integrated circuit device can easily detect disconnection of the bonding wires connected in parallel.
図面の簡単な説明  Brief Description of Drawings
[0017] [図 1]は、本発明に係る半導体集積回路装置を用いたシリーズレギユレータの一実施 形態を示す回路図である。  [0017] FIG. 1 is a circuit diagram showing an embodiment of a series regulator using a semiconductor integrated circuit device according to the present invention.
[図 2]は、半導体チップ CHIP1の縦断面図である。  FIG. 2 is a longitudinal sectional view of a semiconductor chip CHIP1.
[図 3]は、パワートランジスタ素子の使い分けを説明するための図である。  FIG. 3 is a diagram for explaining the proper use of power transistor elements.
[図 4]は、半導体チップ CHIP1の別の縦断面図である。  FIG. 4 is another longitudinal sectional view of the semiconductor chip CHIP1.
[図 5]は、半導体集積回路装置の一従来例を示す概略構成図である。 符号の説明 FIG. 5 is a schematic configuration diagram showing a conventional example of a semiconductor integrated circuit device. Explanation of symbols
IC1 半導体集積回路装置  IC1 Semiconductor integrated circuit device
CHIP1 半導体チップ  CHIP1 semiconductor chip
P1 第 1パワートランジスタ  P1 1st power transistor
P2 第 2パワートランジスタ  P2 Second power transistor
DRV ドライバ回路  DRV driver circuit
T11、T12 第 1パッド（Pl、 Ρ2のェミッタ毎）  T11, T12 1st pad (Each Plitter, ェ 2)
Τ21、 Τ22 第 2パッド（Pl、 Ρ2のコレクタ毎）  Τ21, Τ22 2nd pad (for each collector of Pl, Ρ2)
Τ3 第 3パッド  Τ3 3rd pad
Wl l、 W12 第 1ボンディングワイヤ（Pl、 P2のェミッタ毎） Wl l, W12 1st bonding wire (Each Pl, P2 emitter)
W21、 W22 第 2ボンディングワイヤ（PI、 P2のコレクタ毎)W21, W22 Second bonding wire (for each collector of PI, P2)
W3 第 3ボンディングワイヤ W3 3rd bonding wire
FR1 第 1フレーム（Pl、 P2のェミッタに共通）  FR1 1st frame (common to Pl and P2 emitters)
FR2 第 2フレーム（Pl、 P2のコレクタに共通）  FR2 second frame (common to Pl and P2 collectors)
FR3 第 3フレーム  FR3 3rd frame
ERR 誤差増幅器  ERR error amplifier
E1 直流電圧源  E1 DC voltage source
C1 平滑コンデンサ（入力側）  C1 Smoothing capacitor (input side)
C2 平滑コンデンサ（出力側）  C2 smoothing capacitor (output side)
Rl、 R2 抵抗（帰還電圧生成部）  Rl, R2 resistance (feedback voltage generator)
1 低濃度 P型基板 [P— ]  1 Low-concentration P-type substrate [P-]
2a、 2b 高濃度 n型坦込領域 [n+ ]  2a, 2b High-concentration n-type loading region [n +]
3 低濃度 n型ゥエル領域 [n - ]  3 Low-concentration n-type well region [n-]
4 素子分離領域 [p + ]  4 Element isolation region [p +]
5a、 5b 高濃度 n型シンカー領域 [n + ]  5a, 5b High concentration n-type sinker region [n +]
6a, 6b ベース領域 [n+ +]  6a, 6b Base region [n ++]
7a、 7b ェミッタ領域 [p + ]  7a, 7b Emitter region [p +]
8a, 8b 第 1コレクタ領域 [p + ] 9a、 9b 第 2コレクタ領域 [p + ] 8a, 8b First collector region [p +] 9a, 9b Second collector region [p +]
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0019] 図 1は、本発明に係る半導体集積回路装置を用いたシリーズレギユレータの一実施 形態を示す回路図である。  FIG. 1 is a circuit diagram showing an embodiment of a series regulator using a semiconductor integrated circuit device according to the present invention.
[0020] 本図に示すように、本実施形態のシリーズレギユレータは、半導体集積回路装置 IC 1と、平滑コンデンサ Cl、 C2と、抵抗 Rl、 R2と、を有して成る。上記の半導体集積回 路装置 IC1は、半導体チップ CHIP1と、第 1〜第 3フレーム（外部端子） FR1〜FR3 と、をパッケージングして成る。  As shown in the figure, the series regulator of the present embodiment includes a semiconductor integrated circuit device IC 1, smoothing capacitors Cl and C 2, and resistors R 1 and R 2. The semiconductor integrated circuit device IC1 is formed by packaging a semiconductor chip CHIP1 and first to third frames (external terminals) FR1 to FR3.
[0021] 半導体集積回路装置 IC1の外部にて、入力電圧 Vinが印加される第 1フレーム FR 1は、平滑コンデンサ C1を介して接地されている。また、出力電圧 Voutが引き出され る第 2フレーム FR2は、平滑コンデンサ C2を介して接地される一方、抵抗 Rl、 R2か ら成る直列接続回路（出力電圧 Voutに応じた帰還電圧 Vfbを生成する帰還電圧生 成回路）を介しても接地されている。なお、帰還電圧 Vfbの出力端となる抵抗 Rl、 R2 の接続ノードは、半導体集積回路装置 IC1のフレーム T3に接続されている。  The first frame FR 1 to which the input voltage Vin is applied outside the semiconductor integrated circuit device IC 1 is grounded via a smoothing capacitor C 1. The second frame FR2 from which the output voltage Vout is drawn is grounded via the smoothing capacitor C2, while a series connection circuit consisting of resistors Rl and R2 (feedback that generates a feedback voltage Vfb corresponding to the output voltage Vout). It is also grounded via the voltage generation circuit. Note that the connection node of the resistors Rl and R2 serving as the output terminal of the feedback voltage Vfb is connected to the frame T3 of the semiconductor integrated circuit device IC1.
[0022] 一方、半導体チップ CHIP1は、 pnp型バイポーラトランジスタ Pl、 P2と、第 1パッド Tl l、 T12と、第 2パッド Τ21、 Τ22と、第 3パッド Τ3と、ドライバ回路 DRVと、誤差増 幅器 ERRと、直流電圧源 E1と、を集積化して成る。  On the other hand, the semiconductor chip CHIP1 includes pnp bipolar transistors Pl and P2, first pads Tl 1 and T12, second pads Τ21 and Τ22, third pad Τ3, driver circuit DRV, and error amplification. Unit ERR and DC voltage source E1 are integrated.
[0023] トランジスタ Pl、 P2のェミッタは、それぞれ、第 1パッド Tl l、 T12に接続されている 。第 1パッド Τ11、Τ12は、各々ボンディングワイヤ Wl l、 W12を介して、第 1フレー ム FR1に共通接続されている。トランジスタ Pl、 P2のコレクタは、それぞれ、第 2パッ ド T21、 Τ22に接続されている。第 2ノ ッド Τ21、 Τ22は、各々ボンディングワイヤ W2 1、 W22を介して、第 2フレーム FR2に共通接続されている。トランジスタ Pl、 Ρ2のべ ースは、いずれもドライバ回路 DRVの制御信号出力端に接続されている。誤差増幅 器 ERRの反転入力端（―）は、第 3パッド T3に接続されている。第 3パッド T3は、ボン デイングワイヤ W3を介して、第 3フレーム FR3に接続されている。誤差増幅器 ERR の非反転入力端（+ )は、直流電圧源 E1 (バンドギャップ電源回路など）の正極端に 接続されており、該非反転入力端（+ )には、出力電圧 Voutの目標値を設定するた めの参照電圧 Vrefが印加されている。直流電圧源 E1の負極端は、接地されている 。誤差増幅器 ERRの出力端は、ドライバ回路 DRVの誤差電圧信号入力端に接続さ れている。 [0023] The emitters of the transistors Pl and P2 are connected to the first pads Tll and T12, respectively. The first pads Τ11 and Τ12 are commonly connected to the first frame FR1 through bonding wires Wll and W12, respectively. The collectors of the transistors Pl and P2 are connected to the second pads T21 and Τ22, respectively. The second nodes Τ21 and Τ22 are commonly connected to the second frame FR2 via bonding wires W21 and W22, respectively. The bases of the transistors Pl and IV2 are both connected to the control signal output terminal of the driver circuit DRV. The inverting input terminal (-) of the error amplifier ERR is connected to the third pad T3. The third pad T3 is connected to the third frame FR3 via a bonding wire W3. The non-inverting input terminal (+) of the error amplifier ERR is connected to the positive terminal of the DC voltage source E1 (such as a bandgap power supply circuit), and the target value of the output voltage Vout is set to the non-inverting input terminal (+). Reference voltage Vref for setting is applied. The negative terminal of the DC voltage source E1 is grounded . The output terminal of the error amplifier ERR is connected to the error voltage signal input terminal of the driver circuit DRV.
[0024] なお、半導体チップ CHIP1には、上記した回路構成要素のほか、各種保護回路（ 出力短絡等による IC破壊を防止する過電流保護回路、電源のサージ破壊を防ぐ過 電圧保護回路、或いは、過負荷状態等による熱破壊を防ぐ温度保護回路など)も組 み込まれているが、これらの保護回路は、いずれも本発明と直接関係がないため、そ の図示並びに詳細な説明は省略する。  [0024] In addition to the circuit components described above, the semiconductor chip CHIP1 includes various protection circuits (an overcurrent protection circuit that prevents IC destruction due to output short-circuiting, etc., an overvoltage protection circuit that prevents surge destruction of the power supply, or Temperature protection circuits that prevent thermal destruction due to overload conditions, etc.) are also incorporated, but these protection circuits are not directly related to the present invention, so illustration and detailed description thereof are omitted. .
[0025] 上記構成から成るシリーズレギユレータの基本動作について説明する。半導体チッ プ CHIP1において、誤差増幅器 ERRは、帰還電圧 Vfbと参照電圧 Vrefとの差分を 増幅してドライバ回路 DRVに出力する。ドライバ回路 DRVは、誤差電圧信号が小さ くなるように、トランジスタ Pl、 P2の開閉制御を行う。より具体的に述べると、ドライバ 回路 DRVは、帰還電圧 Vfbが参照電圧 Vrefより低ければ、出力電圧 Voutを高める ようにトランジスタ Pl、 P2の制御信号を生成し、逆に、帰還電圧 Vfbが参照電圧 Vre はりも高ければ、出力電圧 Voutを下げるようにトランジスタ Pl、 P2の制御信号を生 成する。このような動作により、入力電圧 Vinから所望の出力電圧 Voutを生成するこ とが可能となる。  [0025] The basic operation of the series regulator configured as described above will be described. In the semiconductor chip CHIP1, the error amplifier ERR amplifies the difference between the feedback voltage Vfb and the reference voltage Vref and outputs it to the driver circuit DRV. The driver circuit DRV controls opening and closing of the transistors Pl and P2 so that the error voltage signal becomes small. More specifically, the driver circuit DRV generates a control signal for the transistors Pl and P2 to increase the output voltage Vout when the feedback voltage Vfb is lower than the reference voltage Vref, and conversely, the feedback voltage Vfb is the reference voltage. If the Vre beam is high, the control signals for the transistors Pl and P2 are generated so as to lower the output voltage Vout. By such an operation, a desired output voltage Vout can be generated from the input voltage Vin.
[0026] ここで、本実施形態の半導体集積回路装置 IC1は、図 1からも分かるように、トラン ジスタ Pl、 P2を並歹 IJに設け、第 1フレーム FR1と第 2フレーム FR2との間を 2系統の 独立した電流経路（ワイヤ Wl 1—第 1パッド Tl 1 -トランジスタ P1—第 2パッド T21— ワイヤ W21から成る第 1経路と、ワイヤ W12—第 1パッド T12—トランジスタ P2—第 2 パッド T22—ワイヤ W22から成る第 2経路）で接続した構成、すなわち、上記の第 1、 第 2経路を介して電流を分担する構成とされてレ、る。  Here, as can be seen from FIG. 1, in the semiconductor integrated circuit device IC1 of the present embodiment, the transistors Pl and P2 are provided in the parallel IJ, and the gap between the first frame FR1 and the second frame FR2 is provided. Two independent current paths (wire Wl 1—first pad Tl 1 -transistor P1—second pad T21—first path consisting of wire W21 and wire W12—first pad T12—transistor P2—second pad T22 -The configuration connected by the second path consisting of the wire W22, that is, the configuration sharing the current through the first and second paths described above.
[0027] このような構成とすることにより、図 3に示した従来構成と同様、パッドとフレームとを 電気的に接続するボンディングワイヤの抵抗を減らすことができるので、装置の許容 電流量を高めることが可能となる。なお、トランジスタ Pl、 P2の素子サイズは、いずれ も本来設けるべきパワートランジスタの半分 (オン抵抗 2倍）で足りるため、チップサイ ズの拡大を招くことはない。  By adopting such a configuration, as in the conventional configuration shown in FIG. 3, the resistance of the bonding wire that electrically connects the pad and the frame can be reduced, so that the allowable current amount of the device is increased. It becomes possible. Note that the element size of the transistors Pl and P2 is half that of the power transistor that should be originally provided (twice the on-resistance), so that the chip size is not increased.
[0028] また、ワイヤ 1本の抵抗値を Ra = 0. 10 [ Ω ]、トランジスタ Pl、 Ρ2のオン抵抗を Rb = 1. 0 ± 0. 3 [ Ω ]とした場合、第 1、第 2フレーム間の合成抵抗値は、いずれのワイ ャも断 f泉してレヽなければ、 0· 45〜0· 75 (= (Ra X 2 + Rb) /2) [ Ω ]となり、レヽずれ 力 1本のワイヤが断線していれば、 0. 9〜： 1. 5 (=Ra X 2 +Rb) [ Q ]となる。すなわ ち、ワイヤ断線時の経路抵抗値は、非断線時の 2倍に上昇する。従って、本実施形 態の構成を採用すれば、装置の許容電流量を高め得るだけでなぐ並列接続された ボンディングワイヤのうち、ェミッタ側或いはコレクタ側のいずれが断線した場合でも、 その断線を容易に検出することが可能となる。 [0028] The resistance value of one wire is Ra = 0.10 [Ω], and the on-resistance of transistors Pl and Ρ2 is Rb. = 1. 0 ± 0. 3 [Ω], the combined resistance value between the first and second frames will be 0 · 45 to 0 · 75 ( = (Ra X 2 + Rb) / 2) [Ω], and if the wire displacement force is one wire is broken, 0.9 ~: 1.5 (= Ra X 2 + Rb) [Q] Become. In other words, the path resistance value when the wire is broken rises twice as much as when the wire is not broken. Therefore, if the configuration of the present embodiment is adopted, it is easy to break the wire even if either the emitter side or the collector side of the bonding wires connected in parallel can be disconnected, and the allowable current amount of the device can be increased. Can be detected.
[0029] 次に、半導体チップ 1 (特にトランジスタ Pl、 P2周辺）の構造について、図 2を参照 しながら詳細に説明する。図 2は、半導体チップ CHIP1の縦断面図である。  [0029] Next, the structure of the semiconductor chip 1 (especially around the transistors Pl and P2) will be described in detail with reference to FIG. FIG. 2 is a longitudinal sectional view of the semiconductor chip CHIP1.
[0030] 本図に示す通り、本実施形態の半導体チップ 1において、トランジスタ Pl、 P2は、 低濃度 P型 [P— ]基板 1に形成された低濃度 n型 [n - ]ゥエル領域 3a、 3bと；トランジ スタ PI、 P2を分離するための素子分離領域 (高濃度 p型 [p + ]領域) 4と；低濃度 n型 [n—]ゥエル領域 3a、 3bの下方に坦め込まれた高濃度 n型 [n + ]坦込領域 2a、 2bと ；低濃度 n型 [n—]ゥエル領域 3a、 3bの上面から下面に至るまで高濃度 n型 [n + ]埋 込領域 2a、 2bと接するように形成された高濃度 n型 [n + ]シンカー領域 5a、 5bと；高 濃度 n型 [n + ]シンカー領域 5a、 5bに形成され、トランジスタ Pl、 P2のベースとして ドライバ回路 DRVの出力端に接続される高々濃度 n型 [n+ +]ベース領域 6a、 6bと ；低濃度 n型 [n— ]ゥエル領域 3a、 3bに形成され、トランジスタお、 P2のェミッタとし て第 1パッド Tl l、 T12に接続される高濃度 ρ型 [ρ + ]ェミッタ領域 7a、 7bと；高濃度 p型 [p + ]ェミッタ領域 7a、 7bを挟みこむように、低濃度 n型 [n— ]ゥエル領域 3a、 3b に形成され、トランジスタ Pl、 P2のコレクタとして、第 2パッド T21、 Τ22に接続される 第 1高濃度 Ρ型 [Ρ + ]コレクタ領域 8a、 8b、及び、第 2高濃度 p型 [p + ]コレクタ領域 9 a、 9bと；で形成されている。  [0030] As shown in this figure, in the semiconductor chip 1 of the present embodiment, the transistors Pl, P2 are low-concentration n-type [n-] well regions 3a formed on the low-concentration P-type [P-] substrate 1. 3b; isolation region for isolating transistors PI and P2 (high-concentration p-type [p +] region) 4; and low-concentration n-type [n—] well regions 3a and 3b High-concentration n-type [n +] loading regions 2a and 2b; low-concentration n-type [n-] well regions 3a and 3b from the top to the bottom n-type [n +] embedding region 2a, High-concentration n-type [n +] sinker regions 5a and 5b formed in contact with 2b; high-concentration n-type [n +] sinker regions 5a and 5b, and driver circuit DRV as the base of transistors Pl and P2 N-type [n ++] base regions 6a and 6b connected to the output terminals of the transistors; and low-concentration n-type [n-] well regions 3a and 3b, which are used as transistors and P2 emitters. The high-concentration ρ-type [ρ +] emitter regions 7a and 7b connected to the first pads Tl l and T12; and the high-concentration p-type [p +] emitter regions 7a and 7b are sandwiched between the low-concentration n-type [n —] First high-concentration n-type [] +] collector regions 8a, 8b, and second high formed in the well regions 3a, 3b and connected to the second pads T21, Τ22 as collectors of the transistors Pl, P2. Concentration p-type [p +] collector regions 9 a and 9 b;
[0031] なお、上記構造から成る半導体チップ 1は、以下に述べる第 1〜第 6のプロセスを経 て形成される。  Note that the semiconductor chip 1 having the above structure is formed through first to sixth processes described below.
[0032] まず、第 1のプロセスでは、低濃度 p型 [p_]基板 1の表層に、 n型不純物拡散が行 われ、高濃度 n型 [n + ]坦込領域 2a、 2b (いわゆる、ノ リアードレイャ [barried layer] )が形成される。なお、当該高濃度 n型 [n + ]坦込領域 2a、 2bは、ベース引出 時の抵抗を下げるために形成される。 [0032] First, in the first process, n-type impurity diffusion is performed on the surface layer of the low-concentration p-type [p_] substrate 1, and high-concentration n-type [n +] loading regions 2a, 2b (so-called no- A buried layer) is formed. The high concentration n-type [n +] loading regions 2a and 2b are Formed to lower the resistance of time.
[0033] 第 2のプロセスでは、低濃度 p型 [p— ]基板 1上に、気相中で低濃度 n型 [n—]のシ リコン単結晶層がェピタキシャル成長される。  [0033] In the second process, a low-concentration n-type [n-] silicon single crystal layer is epitaxially grown on the low-concentration p-type [p-] substrate 1 in the gas phase.
[0034] 第 3のプロセスでは、トランジスタ Pl、 P2を分離するために、素子分離領域 4として[0034] In the third process, as the element isolation region 4 in order to isolate the transistors Pl and P2,
、高濃度 P型 [P + ]の不純物拡散（アイソレーション拡散）が行われる。当該プロセス により、先述したェピタキシャル成長層は、低濃度 n型 [n_]ゥヱル領域 3a、 3bに分 離される。 High-concentration P-type [P +] impurity diffusion (isolation diffusion) is performed. By this process, the above-mentioned epitaxial growth layer is separated into low-concentration n-type [n_] tool regions 3a and 3b.
[0035] 第 4のプロセスでは、低濃度 n型 [n_]ゥヱル領域 3a、 3bの上面から下面に至るま で、高濃度 n型 [n+ ]埋込領域 2a、 2bと接するように n型不純物拡散が行われ、高濃 度 n型 [n + ]シンカー領域 5a、 5bが形成される。なお、該高濃度 n型 [n+ ]シンカー 領域 5a、 5bは、ベース引出時の抵抗を下げるために形成される。  [0035] In the fourth process, n-type impurities are in contact with the high-concentration n-type [n +] buried regions 2a and 2b from the upper surface to the lower surface of the low-concentration n-type [n_] tool regions 3a and 3b. Diffusion is performed to form high-concentration n-type [n +] sinker regions 5a and 5b. The high-concentration n-type [n +] sinker regions 5a and 5b are formed to reduce the resistance when the base is pulled out.
[0036] 第 5のプロセスでは、高濃度 n型 [n+ ]シンカー領域 5a、 5bにさらなる n型不純物拡 散が行われ、高々濃度 n型 [n+ + ]ベース領域 6a、 6b (トランジスタ Pl、 P2のベース に相当）が形成される。  [0036] In the fifth process, further n-type impurity diffusion is performed in the high-concentration n-type [n +] sinker regions 5a and 5b, and at most the n-type [n + +] base regions 6a and 6b (transistors Pl and P2 Is equivalent to the base of).
[0037] 第 6のプロセスでは、低濃度 n型 [n—]ゥエル領域 3a、 3bに p型不純物拡散が行わ れ、高濃度 P型 [P + ]ェミッタ領域 7a、 7b (トランジスタ Pl、 P2のェミッタに相当）が形 成される。また、同プロセスでは、高濃度 p型 [p + ]ェミッタ領域 7a、 7bを挟むように、 第 1高濃度 P型 [P + ]コレクタ領域 8a、 8b、及び、第 2高濃度 p型 [p + ]コレクタ領域 9 a、 9b (いずれも、トランジスタ Pl、 P2のコレクタに相当）が形成される。  [0037] In the sixth process, p-type impurity diffusion is performed in the low-concentration n-type [n-] well regions 3a and 3b, and the high-concentration P-type [P +] emitter regions 7a and 7b (transistors Pl and P2 Equivalent to the emitter). In the same process, the first high-concentration P-type [P +] collector regions 8a and 8b and the second high-concentration p-type [p +] Collector regions 9a and 9b (both corresponding to the collectors of the transistors Pl and P2) are formed.
[0038] 以降のプロセスでは、シリコン絶縁膜の形成、コンタクトホールの形成、アルミ配線 の形成、並びに、保護膜の形成が順次行われる。  In the subsequent processes, formation of a silicon insulating film, formation of a contact hole, formation of an aluminum wiring, and formation of a protective film are sequentially performed.
[0039] 以上のように、トランジスタ Pl、 P2を上記構造とすることにより、完全に素子分離を 行っているものの、レイアウト面積を大きく変更することなぐ並列トランジスタのペア 性も良好に配置することができる。また、完全に素子分離しているため、同じパワート ランジスタで、 1素子 /2素子の使い分けを行うことが可能となる（図 3を参照）。  [0039] As described above, the transistors Pl and P2 have the above structure, so that the element isolation is completely performed, but the parallel transistor pairing characteristics without greatly changing the layout area can be arranged well. it can. Also, since the elements are completely separated, the same power transistor can be used for 1 element / 2 elements (see Fig. 3).
[0040] なお、上記の実施形態では、本発明に係る半導体集積回路装置を用いたシリーズ レギユレータを例に挙げて説明を行ったが、本発明の構成及び適用対象はこれに限 定されるものではなぐ大電流を取り扱う半導体集積回路装置全般 (例えば、アンプ やコンパレータ、或いは、パワートランジスタ単体）に広く適用することが可能である。 In the above embodiment, the series regulator using the semiconductor integrated circuit device according to the present invention has been described as an example. However, the configuration and application target of the present invention are limited to this. In general, semiconductor integrated circuit devices that handle large currents (for example, amplifiers) And a comparator or a power transistor alone).
[0041] また、本発明の構成は、上記実施形態のほか、発明の主旨を逸脱しない範囲で種 々の変更を加えることが可能である。例えば、パワートランジスタの並列個数を 3個以 上としても構わなレ、し、パワートランジスタとして npn型バイポーラトランジスタ（図 4 (a) を参照）や、 pチャネル或いは nチャネルの電界効果トランジスタ（図 4 (b)或いは図 4 ( c)を参照）を用いても構わなレ、。  [0041] The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above-described embodiment. For example, the number of power transistors in parallel may be three or more, npn bipolar transistors (see Fig. 4 (a)), p-channel or n-channel field effect transistors (Fig. 4). (b) or see Fig. 4 (c)).
[0042] より具体的に述べると、前記パワートランジスタは、図 4 (a)に示すように、低濃度 p 型基板に形成された低濃度 n型ゥエル領域と；前記低濃度 n型ゥエル領域の下方に 坦め込まれた高濃度 n型坦込領域と；前記低濃度 n型ゥエル領域の上面から下面に 至るまで前記高濃度 n型埋込領域と接するように形成された高濃度 n型シンカー領域 と；前記高濃度 n型シンカー領域に形成され、前記パワートランジスタのコレクタとして 第 1パッドに接続される接続される高々濃度 n型コレクタ領域と；前記低濃度 n型ゥェ ノレ領域に形成される低濃度 p型ゥエル領域と；前記低濃度 p型ゥエル領域に形成され 、前記パワートランジスタのベースとして前記ドライバ回路の出力端に接続される高 濃度 P型ベース領域と；前記低濃度 p型ゥエル領域に形成され、前記パワートランジス タのェミッタとして第 2パッドに接続される高濃度 n型ェミッタ領域と；で形成される npn 型バイポーラトランジスタとしてもよい。その際、各素子は、低濃度 p型素子分離領域 で分離すればよい。  More specifically, as shown in FIG. 4 (a), the power transistor includes a low-concentration n-type well region formed on a low-concentration p-type substrate; A high-concentration n-type sinker formed so as to be in contact with the high-concentration n-type embedded region from the upper surface to the lower surface of the low-concentration n-type well region; Formed in the high-concentration n-type sinker region and connected to the first pad as a collector of the power transistor; and formed in the low-concentration n-type drain region. A low-concentration p-type well region; a high-concentration P-type base region formed in the low-concentration p-type well region and connected to an output terminal of the driver circuit as a base of the power transistor; Formed in the region , A high concentration n-type Emitta region is connected to a second pad as Emitta of the power transistor capacitor; may be npn-type bipolar transistor formed by. At that time, each element may be separated by a low-concentration p-type element isolation region.
[0043] 或いは、前記パワートランジスタは、図 4 (b)に示すように、低濃度 p型基板に形成さ れた第 1低濃度 n型ゥエル領域と；第 1低濃度 n型ゥエル領域の下方に坦め込まれた 高濃度 n型埋込領域と；第 1低濃度 n型ゥエル領域に形成された第 2低濃度 n型ゥェ ノレ領域と；第 2低濃度 n型ゥエル領域に形成され、前記パワートランジスタのソースとし て第 1パッドに接続される高濃度 p型ソース領域と；第 2低濃度 n型ゥエル領域に形成 され、前記パワートランジスタのドレインとして第 2パッドに接続される高濃度 p型ドレイ ン領域と;前記高濃度 p型ソース領域と前記高濃度 p型ドレイン領域との間に跨って 形成され、前記パワートランジスタのゲートとして前記ドライバ回路の出力端に接続さ れるゲート領域と；第 2低濃度 n型ゥエル領域に形成され、前記パワートランジスタの バックゲートとして第 1パッドに接続される高濃度 n型バックゲート領域と；で形成され る Pチャネル型電界効果トランジスタとしてもよい。その際、各素子は、高濃度 p型素 子分離領域で分離すればょレ、。 [0043] Alternatively, as shown in FIG. 4 (b), the power transistor includes a first low-concentration n-type well region formed on a low-concentration p-type substrate; and a lower portion of the first low-concentration n-type well region. A high concentration n-type buried region encased in; a second low concentration n-type well region formed in the first low-concentration n-type well region; and a second low-concentration n-type well region. A high concentration p-type source region connected to the first pad as the source of the power transistor; and a high concentration connected to the second pad as the drain of the power transistor and formed in the second low concentration n-type well region a p-type drain region; a gate region formed between the high-concentration p-type source region and the high-concentration p-type drain region and connected to the output terminal of the driver circuit as a gate of the power transistor; ; Formed in the second low-concentration n-type well region Is a high-concentration n-type back gate region is connected to the first pad as a back gate of said power transistor; formed by P-channel field effect transistors may be used. At that time, each element should be separated in the high-concentration p-type element separation region.
[0044] 或いは、前記パワートランジスタは、図 4 (c)に示すように、低濃度 p型基板に形成さ れ、前記パワートランジスタのドレインとして第 1パッドに接続される高濃度 n型ドレイ ン領域と；前記低濃度 p型基板に形成され、前記パワートランジスタのソースとして第 2パッドに接続される高濃度 n型ソース領域と；前記高濃度 n型ドレイン領域と前記高 濃度 n型ソース領域との間に跨って形成され、前記パワートランジスタのゲートとして 前記ドライバ回路の出力端に接続されるゲート領域と;前記低濃度 p型基板に形成さ れ、前記パワートランジスタのバックゲートとして第 2パッドに接続される高濃度 p型バ ックゲート領域と；で形成される nチャネル型電界効果トランジスタとしてもよレ、。その 際、各素子は、低濃度 n型素子分離領域で分離すればよい。  Alternatively, as shown in FIG. 4 (c), the power transistor is formed on a low-concentration p-type substrate, and is connected to a first pad as a drain of the power transistor. A high-concentration n-type source region formed on the low-concentration p-type substrate and connected to a second pad as a source of the power transistor; and the high-concentration n-type drain region and the high-concentration n-type source region A gate region formed between and connected to the output terminal of the driver circuit as a gate of the power transistor; formed on the low-concentration p-type substrate and connected to a second pad as a back gate of the power transistor A high-concentration p-type back gate region, and an n-channel field effect transistor formed by; At that time, each element may be isolated in a low-concentration n-type element isolation region.
産業上の利用可能性  Industrial applicability
[0045] 本発明は、大電流を取り扱う半導体集積回路装置及びこれを用いたレギユレータの 信頼性向上を図る上で有用な技術である。 The present invention is a technique useful for improving the reliability of a semiconductor integrated circuit device handling a large current and a regulator using the same.

Claims

請求の範囲 The scope of the claims
[1] 同一の制御信号によって開閉制御される n個のパワートランジスタと、前記パワート ランジスタの各一端に接続される n個の第 1パッドと、前記パワートランジスタの各他 端に接続される n個の第 2パッドと、前記制御信号を生成する制御信号生成手段と、 を備えた半導体チップと；第 1パッドが各々ボンディングワイヤを介して共通接続され る第 1フレームと；第 2パッドが各々ボンディングワイヤを介して共通接続される第 2フ レームと；を有して成る半導体集積回路装置。  [1] n power transistors controlled to be opened and closed by the same control signal, n first pads connected to each one end of the power transistor, and n connected to each other end of the power transistor A second chip, a control signal generating means for generating the control signal, a semiconductor chip comprising: a first frame in which the first pads are commonly connected via bonding wires; And a second frame connected in common via a wire.
[2] 前記パワートランジスタは、バイポーラトランジスタであることを特徴とする請求項 1に 記載の半導体集積回路装置。  2. The semiconductor integrated circuit device according to claim 1, wherein the power transistor is a bipolar transistor.
[3] 前記パワートランジスタは、低濃度 p型基板に形成された低濃度 n型ゥエル領域と； 前記低濃度 n型ゥエル領域の下方に埋め込まれた高濃度 n型埋込領域と；前記低濃 度 n型ゥエル領域の上面から下面に至るまで前記高濃度 n型埋込領域と接するように 形成された高濃度 n型シンカー領域と；前記高濃度 n型シンカー領域に形成され、前 記パワートランジスタのベースとして前記制御信号生成手段の出力端に接続される 高々濃度 n型ベース領域と；前記低濃度 n型ゥエル領域に形成され、前記パワートラ ンジスタのェミッタとして第 1パッドに接続される高濃度 p型ェミッタ領域と；前記高濃 度 p型ェミッタ領域を挟むように前記低濃度 n型ゥエル領域に形成され、前記パワート ランジスタのコレクタとして第 2パッドに接続される第 1、第 2高濃度 p型コレクタ領域と ；で形成される pnp型バイポーラトランジスタであることを特徴とする請求項 2に記載の 半導体集積回路装置。  [3] The power transistor includes: a low-concentration n-type well region formed on a low-concentration p-type substrate; a high-concentration n-type buried region buried below the low-concentration n-type well region; A high-concentration n-type sinker region formed in contact with the high-concentration n-type buried region from the upper surface to the lower surface of the n-type well region; and the power transistor formed in the high-concentration n-type sinker region A high-concentration n-type base region connected to the output terminal of the control signal generating means as a base of the control signal; a high-concentration p formed in the low-concentration n-type well region and connected to the first pad as an emitter of the power transistor A first emitter and a second emitter connected to a second pad as a collector of the power transistor, formed in the low-concentration n-well region so as to sandwich the high-concentration p-type emitter region. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is a pnp bipolar transistor formed by: a concentration p-type collector region;
[4] 前記パワートランジスタは、低濃度 p型基板に形成された低濃度 n型ゥエル領域と； 前記低濃度 n型ゥエル領域の下方に埋め込まれた高濃度 n型埋込領域と；前記低濃 度 n型ゥエル領域の上面から下面に至るまで前記高濃度 n型埋込領域と接するように 形成された高濃度 n型シンカー領域と；前記高濃度 n型シンカー領域に形成され、前 記パワートランジスタのコレクタとして第 1パッドに接続される接続される高々濃度 n型 コレクタ領域と；前記低濃度 n型ゥエル領域に形成される低濃度 p型ゥエル領域と；前 記低濃度 p型ゥエル領域に形成され、前記パワートランジスタのベースとして前記ドラ ィバ回路の出力端に接続される高濃度 p型ベース領域と；前記低濃度 p型ゥエル領域 に形成され、前記パワートランジスタのェミッタとして第 2パッドに接続される高濃度 n 型ェミッタ領域と；で形成される npn型バイポーラトランジスタであることを特徴とする 請求項 2に記載の半導体集積回路装置。 [4] The power transistor includes: a low-concentration n-type well region formed on a low-concentration p-type substrate; a high-concentration n-type buried region buried below the low-concentration n-type well region; A high-concentration n-type sinker region formed in contact with the high-concentration n-type buried region from the upper surface to the lower surface of the n-type well region; and the power transistor formed in the high-concentration n-type sinker region A high-concentration n-type collector region connected to the first pad as a collector of the low-concentration p-type well region formed in the low-concentration n-type well region; and formed in the low-concentration p-type well region. A high-concentration p-type base region connected to an output terminal of the driver circuit as a base of the power transistor; and the low-concentration p-type well region 3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is an npn-type bipolar transistor formed by: a high-concentration n-type emitter region connected to a second pad as an emitter of the power transistor. .
[5] 前記パワートランジスタは、電界効果トランジスタであることを特徴とする請求項 1に 記載の半導体集積回路装置。  5. The semiconductor integrated circuit device according to claim 1, wherein the power transistor is a field effect transistor.
[6] 前記パワートランジスタは、低濃度 p型基板に形成された第 1低濃度 n型ゥエル領域 と；第 1低濃度 n型ゥエル領域の下方に坦め込まれた高濃度 n型坦込領域と；第 1低 濃度 n型ゥエル領域に形成された第 2低濃度 n型ゥエル領域と；第 2低濃度 n型ゥエル 領域に形成され、前記パワートランジスタのソースとして第 1パッドに接続される高濃 度 p型ソース領域と；第 2低濃度 n型ゥエル領域に形成され、前記パワートランジスタ のドレインとして第 2パッドに接続される高濃度 p型ドレイン領域と；前記高濃度 p型ソ ース領域と前記高濃度 p型ドレイン領域との間に跨って形成され、前記パワートランジ スタのゲートとして前記ドライバ回路の出力端に接続されるゲート領域と；第 2低濃度 n型ゥエル領域に形成され、前記パワートランジスタのバックゲートとして第 1パッドに 接続される高濃度 n型バックゲート領域と；で形成される pチャネル型電界効果トラン ジスタであることを特徴とする請求項 5に記載の半導体集積回路装置。  [6] The power transistor includes a first low-concentration n-type well region formed on a low-concentration p-type substrate; and a high-concentration n-type loading region carried below the first low-concentration n-type well region A second low-concentration n-type well region formed in the first low-concentration n-type well region; and a second high-concentration region formed in the second low-concentration n-type well region and connected to the first pad as the source of the power transistor. A high-concentration p-type source region; a high-concentration p-type source region formed in a second low-concentration n-type well region and connected to a second pad as a drain of the power transistor; And a gate region connected to the output terminal of the driver circuit as a gate of the power transistor; formed in a second low concentration n-type well region; The power transistor bar 6. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is a p-channel field effect transistor formed by: a high-concentration n-type back gate region connected to the first pad as a back gate.
[7] 前記パワートランジスタは、低濃度 p型基板に形成され、前記パワートランジスタのド レインとして第 1パッドに接続される高濃度 n型ドレイン領域と；前記低濃度 p型基板に 形成され、前記パワートランジスタのソースとして第 2パッドに接続される高濃度 n型ソ ース領域と；前記高濃度 n型ドレイン領域と前記高濃度 n型ソース領域との間に跨つ て形成され、前記パワートランジスタのゲートとして前記ドライバ回路の出力端に接続 されるゲート領域と；前記低濃度 p型基板に形成され、前記パワートランジスタのバッ クゲートとして第 2パッドに接続される高濃度 p型バックゲート領域と；で形成される n チャネル型電界効果トランジスタであることを特徴とする請求項 5に記載の半導体集 積回路装置。  [7] The power transistor is formed on a low-concentration p-type substrate, and is formed on the low-concentration p-type substrate; a high-concentration n-type drain region connected to a first pad as a drain of the power transistor; A high concentration n-type source region connected to a second pad as a source of the power transistor; formed between the high concentration n-type drain region and the high concentration n-type source region; A gate region connected to an output terminal of the driver circuit as a gate of the driver; a high concentration p-type back gate region formed on the low-concentration p-type substrate and connected to a second pad as a back gate of the power transistor; 6. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is an n-channel field effect transistor formed by:
[8] 請求項 1〜請求項 7のいずれかに記載の半導体集積回路装置と、入力電圧が印加 される第 1フレームと接地端との間に接続される入力平滑コンデンサと、出力電圧が 引き出される第 2フレームと接地端との間に接続される出力平滑コンデンサと、前記 出力電圧に応じた帰還電圧を生成する帰還電圧生成手段と、を有して成り、前記制 御信号生成手段にて、前記帰還電圧が所定の基準電圧と一致するように、前記制御 信号の生成を行うことを特徴とするレギユレータ。 [8] The semiconductor integrated circuit device according to any one of claims 1 to 7, an input smoothing capacitor connected between the first frame to which the input voltage is applied and the ground terminal, and an output voltage is extracted. An output smoothing capacitor connected between the second frame and the ground terminal, Feedback voltage generating means for generating a feedback voltage corresponding to the output voltage, and the control signal generating means generates the control signal so that the feedback voltage matches a predetermined reference voltage. Regulator characterized by performing.
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