WO2006132560A1

WO2006132560A1 - Dynamic sequential functional device

Info

Publication number: WO2006132560A1
Application number: PCT/RU2005/000309
Authority: WO
Inventors: Victor Nikolaevich Mourachev
Original assignee: Victor Nikolaevich Mourachev
Priority date: 2005-06-06
Filing date: 2005-06-06
Publication date: 2006-12-14

Abstract

The invention relates to micro-nano electronic engineering and can be used for designing dynamic storage devices, two-dimensional control matrixes for liquid crystal screen-displays, high-speed and high-accuracy scanners, two-dimensional sensors, delay lines etc. The inventive device is characterised in that it uses a chain of in-series connected active functionally-integrated pixels capable to control electrical devices which are technology-compatible therewith. Each pixel chain is embodied in the form of an elementary electrical circuit consisting of a MOS transistor and resistors. The main advantages of the device are the following: processability, low cost and a high operational reliability, due to the fact that the failure of one or several elements-pixels thereof does not cause the failure of the entire device, a low energy consumption as far as the energy of a power source is consumed by one pixel and the device is provided with three electrical outputs, only.

Description

Dynamic Serial Functional Device

The invention relates to micro-nanoelectronics and can be used, in particular, when creating storage devices, two-dimensional control matrices for liquid crystal displays, high-speed scanners, sensors, delay lines, etc.

Analogs are known, i.e. dynamic sequential functional DEVICE α V. _I M, AI *** J ₎ WAYS AFTER AFFECTIVELY PSrCrviSLTN KNψ SMROSOCHNY CHARGE ON a chain of pixel elements constituting them [1 - 3], for example, device DFTU consisting of consecutively [bipolar, 3 bipolar. Fig. 1) or MOS transistors [2, 3] (see Fig. 2), which in the literature have received the name "fire chains". DPFU based on series-connected MOS structures, called “charge-coupled devices” (CCD), are widely used in optical image receivers. [3] (see FIG. 3)

However, these DPFU devices have a serious disadvantage in that they are not able to enhance the transferred information charge, which ultimately leads to its weakening or complete attenuation. In addition, the pixels of these devices are not capable of controlling the technology

SUBSTITUTE SHEET (RULE 26) compatible with other electronic devices - transistors, resistors, LEDs, etc.

The second drawback of these DFTUs is the need to clock a chain of serially connected pixels to ensure the movement of the information charge from pixel to pixel, which requires the use of two to three clock buses, which greatly complicates the design and construction of the DFTU device.

These drawbacks are partially deprived of the closest in terms of the technological nature of the DPFU described in the Russian patent [4] and PCT patent application [5], taken as a prototype. This DPFU (see Fig. 4) contains a chain of series-connected pixels, including the input and output buses (terminals), a common bus and a power bus, while the output bus (terminal) of each pixel \ except for the last \ is connected to the input bus (terminal) pixels following it. Each pixel of the chain contains a bipolar transistor, and its collector is connected to the output bus and through the resistor to the power bus, the emitter is connected to the common bus, and the base is connected through another resistor to the common bus and through the capacitor to the input bus, and the storage time of information is determined by the recombination time minority charge carriers in which:

^L nac ¹ O ^w I _c ,

where t us is the saturation time, τ ₀ is the lifetime of minority carriers, Iк and 16 are the collector and base currents, respectively, h21e is the base current gain.

This DPFU device is also not without drawbacks, which are due to its low speed due to the use of the “low” saturation of the bipolar transistor, the relative complexity of the manufacturing technology of bipolar transistor structures, as well as their relatively large sizes, which does not allow to achieve the maximum level of integration of the DPFU .

The technical effect of the invention is to increase the speed, manufacturability and integration of DPFU.

SUBSTITUTE SHEET (RULE 26) These effects are achieved in that each pixel of the chain contains a \ non-bipolar \ MOS transistor, capacitor, first resistance, second resistance and third resistance, and the gate of the MOS transistor is connected through the capacitor to the input bus (terminal) and through the first input resistance to the common bus , its drain is connected through the second load resistance to the power bus, its gate region through the third additional resistance is connected to the common bus, and the source is also connected to the common bus.

At the same time, the storage time of the information charge, determined by the turn-off delay time of the MOS transistor (tset), which should increase the constant of the recharge time (τп) of the capacitor (C) through the \ first \ input resistance is Rl tset> C * Rl, and the product of the capacitor capacitance C by the value of the input voltage Uin should exceed the value of the product of the gate capacitance - the gate region (Szp) times the value of the threshold voltage of the MOS transistor (Ut)

Uvx * C> Ut * Czp

In order to ensure synchronization (which is important for some applications), the first - input impedance pixels of an FFTU can be connected to an additional synchronization bus.

In order to ensure greater manufacturability, the capacitor and the first input and / or third additional pixel resistances can be made on the basis of diodes, moreover, the anode of the diode replacing the capacitor is connected to the gate of the MOS transistor, and the cathode is connected to the input bus (terminal), the anode of the diode replacing the first the input resistance is connected to the common bus, and the cathode to the gate of the MOS transistor, the anode of the diode replacing the third - additional resistance is connected to the gate region, and its cathode to the common bus.

In order to ensure greater reliability, the gate region of the MOS transistor is connected to the base of an additional bipolar transistor, the collector of which is connected to the drain region, and the emitter to the source region of the MOS transistor.

In order to simplify the design of the DPSA circuit, the gate region may not be connected to the topic, i.e. to be “floating”, i.e. In this case, the third additional resistance is infinity.

SUBSTITUTE SHEET (RULE 26) Description of electrical circuits

In FIG. 1 shows an electrical circuit of a fireproof type DFU selected as an analogue of the invention, containing pixels, output buses (2) of which are connected in series with input buses (1) of subsequent pixels, bipolar transistor electrodes -3 are connected respectively: emitters to input buses I ₅ collectors to the output buses 2, the base through the corresponding capacitors (4) are connected to the collectors and the odd (5) and even buses (6), respectively.

In FIG. Figure 2 shows a similar electrical circuit selected as an analogue of a DPFU of the “fire” type on MOS transistors. The designations in the diagram are identical.

In fig. Figure 3 shows the construction of another analogue device called "CCD" device containing sequentially arranged MOS structures

(3).

CCD devices also have clock buses (5, 6, 7), however, the input bus-terminal is only on the first pixel, and the output bus is on the last.

consistently connected pixels, each of which contains an input (1) and output- (2) bus (terminal), a common bus- (3), a power bus - (4), a capacitor- (5), the first resistor Rl- (6) , the second resistor R2 is (7), the bipolar transistor is (8).

In FIG. 5 shows an electrical circuit of a DPFU corresponding to the first claim. The electrical circuit contains a chain of series-connected pixels, each of which has an input (1) and output (2) bus (terminal), common blush (3) and power blink (4), capacitor (5), the first is the input resistance (6) the second is the load resistance (7), the third is the additional resistance (8), the MOS transistor (9). In this case, in the circuit, the gate of the MOS transistor (9) is connected to the input terminal (1) through a capacitor (5) and connected to a common bus (3) through the first-input resistance Rl (6), its drain is connected to the output bus (2) and through the load resistance R2 (7) is connected to the power bus (4), the gate region of the MOS transistor (9) through the third additional resistance

(о) ιi ОССОСДИНСНα To the General ϊlшris (3).

Figure 6 shows the electrical circuit of the DPFU corresponding P2 claims. The electrical circuit contains a chain of series-connected pixels, each of which has an input (1) and output (2) bus (terminal), a common

SUBSTITUTE SHEET (RULE 26) the bus (3) and the power bus (4), the capacitor (5), the first resistance (6), the second resistance (7) the third resistance (8), the MOS transistor (9) of the gates of which is connected through the first resistance R 1 (6) R 'additional clock pin (10), where the drain is connected to the output bus (2) and is connected to the power bus (4) through the resistor R2 (7), the gate region of the MOS transistor (9) is connected to the common bus through the third resistance (8) ( 3).

Figure 7 shows the electrical circuit of the DPFU corresponding to the PP of the claims. The electrical circuit contains a chain of series-connected pixels, each of which has an input (I) and output (2) bus (terminal), a common bus (3) and a power bus (4), a capacitor (5), the first resistance (6), and the second resistance (7) is the third resistance (8), the MOS transistor (9), while in the circuit the gate of the MOS transistor (9) is connected to the anode of the diode (11), the cathode of which is connected to the input bus (1) and to the anode of the diode (12) the cathode of which is connected to a common bus (3), its drain is connected to an output bus (2) and is connected to a power bus (4) through resistance R2 (7), I region of the MOS transistor (9) is connected to the common bus through the third resistance.

In FIG. S shows an electrical circuit of a DPFU corresponding to P4 of the claims. The electrical circuit contains a chain of series-connected pixels, each of which has an input (1) and output (2) bus (terminal), a common bus (3) and a power bus (4), a capacitor (5), the first resistance (6), and the second resistance (7) third resistance (8), MOS transistor (9) and bipolar transistor (13). In this case, in the circuit, the gate of the MOS transistor (9) is connected through a condenser - 5 to the input cable (1) and through the first resistance to the common bus-3 its source is connected to the common bus -3 its drain is connected to the output bus (2) and through the resistance R2 (7) is connected to the power bus (4), the gate region of the MOS transistor (9) is connected to the base of the bipolar transistor (13), the collector of which is connected to the output bus (2), and the emitter to the common bus (3).

Figure 9 shows the electrical circuit of the DPFU corresponding to paragraph Pl of the claims. The electric circuit comprises a chain of series-connected pixels, each of koto ⁿ yx has vxodn ^v u O ^ and vyxodn ^v w ^ 2 ^ bus (terminals), a common bus (3) and the power bus (4), a condenser (5), the first resistance (6), the second resistance (7) the third resistance (8), the MOS transistor (9 whose gate is connected through the capacitor to the input bus-1 and through the first resistance is connected to the common bus-3 input bus (П and. Its drain is connected to the output tire (2)

SUBSTITUTE SHEET (RULE 26) and through resistance R2 (7) it is connected to the power bus (4), the gate region of the MOS transistor (9) is not connected to anything (that is, it has a “floating” potential).

DPFU device (see figure 5) works as follows:

When a “longoro” negative input pulse (Uin) arrives at the input terminal (1), as shown in FIG. 10a, it is differentiated due to the RC chain formed by the capacitor C (5) and the resistance Rl (6). As a result, at the gate of the MOS transistor (9) two “short” pulses are formed, negative and positive, respectively (see Fig. I Ob). In this case, a positive pulse opens the MOS transistor (9), which is in this state up to this point. However, the open state of the transistor (t _TCI) can significantly exceed the duration of a positive "kopotkogo" impylca (t m _and _{n, +)} and the duration of the input pulse _(P Tim), i.e. in real transistors, there is always a delay in the turn-off time of the transistor (tЗa _Д ) with respect to the time when the input signal expires (see Fig. Yuv). This phenomenon in MOS transistors is usually extremely undesirable and is due to well-known physical effects, which have received the names in the literature: - “kink-effect”, “bodi” effect, parasitic transistor effect. In the proposed electric circuit of the FFTU, these parasitic effects are used to memorize the fact of applying a pulse to the input pixels by a value of time (t-back). In this case, the DPFU is used as a dynamic random access memory device, (t _ass ) is essentially the storage time of the information order R pixel — memory cell

Obviously, the arrival of the output signal (U _off ) from the drain of the MOS transistor of the first pixels to the input of the next pixel of the DFTU, for which it will be an input signal, will lead to a similar process. Thus, the pulse applied to the first memory cell will be sequentially distributed throughout the pixel chain, due to the sequential opening of the MOS pixel transistors (see Fig. South). Receipt of the input DPFU several divided by time input pulses lcov ^v n ⁿ ivodit to their serial pepem ^p u and ^p iiyu ho ⁿ ^MF m tirshmtlv signals ma - pixel charges along the chain, as in ((traveling ctpoke "illuminated advertising.

It should be noted that the DPFU device \ as well as the CCD device \ is a functional device, since the technical result is achieved through the simultaneous use of the original circuit and specific ((parasite »

SUBSTITUTE SHEET (RULE 26) effects inherent in the MOS structure, which cannot be adequately described by circuitry.

It is important to note that the slave is ^“ axis,” and the pixel of the DPFU, yours is possible when the above relations are fulfilled tad> C * Rl

, which determines the condition of acceptable differentiation of the input pulse and the condition

U _in * OV _t * C _n , which determines the necessary condition for sufficient opening of the MOS transistor. In this case, usually the f _zAD correlates with the lifetime of non-main charge carriers in the sub-gate region.

The operation of DPFU in asynchronous mode is modeled using the well-known computer program "SPACE". B as an example in FIG. Figure 11 shows the time dependences of the output voltages for a chain of 8 ^mi pixels, at the input of which a single pulse is applied.

For some applications of DPFU, it is important that it synchronously work with other electronic devices (for example, in flat-circuit television image scanning schemes), and to provide a synchronization mode, it is sufficient to supply synchronizing pulses to only one clock bus (10), as shown in FIG. 6. Modeled, using SPACE program, the timing diagram of the operation of the DPFU in asynchronous mode is shown in Fig. 12.

The operation of the DPFU chain is possible in the case of replacing the capacitor C (5) and / or the resistor R 1 (6) and diodes (1 1) and (12), respectively (see Fig. 7) R in this case, the barrier capacitance of the diode (11) acts as a capacitor, and the presence of the reverse current of the diode (Ϊ2) ensures the presence of the necessary zero potential at the gate of the MOS transistor. Such a replacement of the capacitor and resistors Rl and / or RЗ provides greater manufacturability of manufacturing DPFU and its smaller size, i.e. great integration. It should be noted that any element can be used as resistor R2 (7) - 2 ^ pole (LED, inductance, etc.).

In case of use

a koto ⁿ yx aforementioned "papazitnye" effects are weaker, possibly using a combination of the pixels in the MOS and bipolar transistors as shown in FIG. 8. In this case, the dependence of the DPFU operability on the magnitude and variation of the capacitance and resistance values of the resistors of the circuit u and also on

SUBSTITUTE SHEET (RULE 26) electrophysical parameters of MOS and bipolar transistors. This circumstance provides increased reliability of the circuit.

Cx ^'Em DPFU iSLGOJT Jy Goscha MOS transistor ^"C kfiLZvanZScheiw iϊODZa Gvϋrnυi region (see FIG. 8) is different from previous schemes lower speed because it is most strongly expressed" papazitnye "effects. However, it has the best integration, because there is no resistance in the gate region (RЗ) and contact with it. Such a DFU can be easily implemented on the basis of the “silicon on isolator” technology - KHI, \ see Fig. 14 \. Such a scheme can be used in the case when speed is not a determining parameter.

Practical use

The experimental devices (mock-ups) of the DPFU were made on the basis of standard K'MOS VLSI technologies with monosilicon and ϊt dielectric substrates. Topologies and designs of such devices \ with a minimum topological norm Lt ~ 1.5 microns. \ are shown in FIG. 13 and FIG. 14. The values of the resistors \ made on polysilicon n ^~ - type \ were respectively Ri = 10 Mom, R2 = 100 Kom, the capacitance of the capacitor C = 10 ^"13 F, the length and width of the gate of the MOS transistor, respectively, was LK = 1.5 μm, Wk = 10 μm, the gate system capacitance Сзп = 10 ^"14 F, the drain capacitance - the source Cc = Cu ~ 5 * 10 ^{" 14} F. The mesa size is

Lz I jJJf IV i Jr JJbI i jjαn_> nv_. iujjα

kΛjо iαоjiяjiti vv_ »υ ι ot 11/1 i_ιiw - miuvi and r» ivi -

10 μm, the thickness of the gate oxide δ ~ 300A. The threshold voltage (Ut) of the MOS transistors was Ut ~ 1.0 V, the supply voltage of the circuit was + Uc = 5 V. The fabricated model of the DPFU device showed its stable performance with a wide change in the parameters of the circuit elements in the range of ± 200% and the supply voltage from + Uc = 2.5V to 10V.

In conclusion, it should also be noted the important advantages of DPFU, which CONSTITUTE WITH ^' лсдуТшцέм ^' .

- extremely low energy consumption when it is used as a scanning device, since in this case the energy consumption occurs in only one pixel (see Fig. 15).

- exceptionally high reliability of work, a high percentage of annual output \ and the associated low cost \ is realized in the case of the organization of work of DFU in

SUBSTITUTE SHEET (RULE 26) the principle of “double helix” (see Fig. 16), since in this case a failure of one or many pixels does not lead to a failure of the entire device.

- DJTI m'ϋnTazh of the crystal (ϊϊ Дα) DPFU GreyububGсG Dsshsiyi vSёfυ Two-Sin output case.

SUBSTITUTE SHEET (RULE 26) Information sources

1. Sangster F. L. J. The The Great Vrigate Delau Lipe. A Shift Registeg for For Apaligue Sigpals, Philips Tesh. Revéw, 31, 97-1 10 (1970)

2. Krause G. Apalog Srehsherketle: Fipe Neuartige Sshtulpg Jum Srehshep apd Verzoegerp vop Sigpalep. Elstroopis Lettt, 3, 544-546 (1967)

3. Сarllo H. Sevuyp apd Mishail F. Totsset Scharge Trapsfer Devices Asademis Res. Ips. New York, Sap Frapsisso, Lopd 1975 pplθ-15.

K. Seken, M. Thompset. Charge transfer devices. Because of the world. 1978 pg. 12-14

4. V. Murashev. “Dynamic memory cell” patent for the invention of Russia jNs2147772 priority from 11.06.1997.

5. Murashev V. H., Saito T. ((Sequential dynamic functional device)). Patent Application N ° PCT / RU 02/00457 of July 21, 2003

6. Siliop-op-IPsulogo Teshologu: Materials for VLSL 2-nd Ediop bu Dzheap-Rieper Solipge. Experience catholigue de louvaj, belgium. Kluwer Assademis Publishers Vostop / Dordresht / Lopdop TK7871 35 C 758, 1997. 651.38.152-dc21 97-35777cip. PP-126, 134, 163.

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SUBSTITUTE SHEET (RULE 26)

Claims

Claim

Pl Dynamic serial functional device containing a chain of series-connected pixels, including a common bus, a power bus, input and output buses (terminals), and the output bus (terminal) of each pixel connected to the input

subsequent to the xi pixels, each pixel contains a transistor, a capacitor, the first input resistance, the second load resistance, characterized in that in order to improve performance, manufacturability and integration, the pixel transistor is a MOS transistor, while the gate of the MOS transistor is connected through the capacitor to the input bus (terminal) and through the first - input resistance to the common bus, its drain is connected through the second - load resistance to the power bus, its gate region through the third - additional with trrotinlenie connected to a common bus, and the source is also connected to a common bus.

In this case, the turn-on delay time of the MOS transistor (tset) exceeds the constant of the capacitor recharge time (C) through the first input resistance (Rl), i.e. back> C * Rl

, and the product of the value of the capacitance of the capacitor (C) multiplied by the value of the input voltage (Uin) is greater than the product of the value of the capacitance formed by the gate and the substrate of the MOS transistor (Szp) by the value of the threshold voltage of the MOS transistor

Uvx * C> Ut * Rl

eleven

SUBSTITUTE SHEET (RULE 26) P2 Dynamic sequential functional device, according to Pl, characterized in that in order to ensure synchronous operation, the first input signals are connected to an additional synchronization bus.

ПЗ Dynamic serial functional device, according to Пl and П2, characterized in that in order to ensure manufacturability, the capacitor and / or the first resistance can be made on the basis of diodes, the anode of the first diode replacing the capacitor connected to the gate of the MOS transistor, and the cathode to the input bus, the anode of the second diode replacing the first input resistance is connected to the common bus, the cathode to the gate of the MOS transistor, the third resistance is connected to the gate region and to the common bus.

П4 Dynamic serial functional device, according to Пl, П2, ПЗ - differing in order to increase the reliability of operation, the gate region of the MOS transistor is connected to the base of an additional bipolar transistor, the collector of which is connected to the drain region of the MOS transistor, and the emitter to the source region of the MOS transistor.

P5 Dynamic functional device, according to PL P2. PZ, P4, characterized in that in order to simplify the design, the gate region of the MOS transistor is not connected to anything, i.e. Floating potential.

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SUBSTITUTE SHEET (RULE 26)