WO2006128323A1

WO2006128323A1 - A method for implementing the rate change of the data of transmission convergence layer in adsl system and the apparatus thereof

Info

Publication number: WO2006128323A1
Application number: PCT/CN2005/000774
Authority: WO
Inventors: Zhe Wu; Fengshou Guo
Original assignee: Zte Corporation
Priority date: 2005-06-02
Filing date: 2005-06-02
Publication date: 2006-12-07

Abstract

A method for implementing the rate change of the data of Transmission Convergence layer in ADSL system. According to the number of the bits per symbol of Transmission Convergence configured by the system, determine the bit rate of the data transmission and further determine the other required configuration information, such as the number of the symbols corresponding to an FEC frame, the number of the bits comprised in an FEC frame practically, so that the data process is converted from the byte process for PMS-TC layer to the bit process for PMD layer, which enables the data with byte as a unit from PMS-TC layer to satisfy both the requires of the byte process for PMS layer and the bit rate increase in PMD layer in ADSL2 protocol and implements the 4K stepping of the data rate in ADSL system. There is also an apparatus implementing the above method.

Description

Transmission of convergence layer data in an asymmetric digital subscriber line system

Method and device for realizing rate conversion

The present invention relates to an Asymmetric Digital Subscriber Line (ADSL) system, and more particularly to an ADSL system for Physical Media Specific Transmission Convergence (PMS-TC) layer to Physical Medium. A method and apparatus for realizing rate conversion of data in a downlink transmission direction of a PMD) layer. Background technique

The ADSL protocol specifies how the transceivers in the ADSL system send and receive data to and from the ADSL system. Currently, the ADSL2 protocol has been upgraded. The ADSL2 protocol prescribes how the transmitter of the 11⁄2 device processes the data from the specific application interface device, then performs inverse processing on the receiving end of the transceiver device and finally sends it to the application interface device.

Figure 1 is a simplified functional diagram of an ADSL unit (ATU) using the ADSL2 protocol. There are two types of ADSL transceiver units: the ADSL transceiver unit (ATU-C) on the local exchange side and the ADSL transceiver unit on the subscriber side (ATU). -R). The ADSL transceiver unit mainly includes a Transport Protocol Specific Transmission Convergence (TPS-TC) layer module, a PMS-TC layer module, a PMD layer module, and a Management Protocol Specific Transmission Convergence (MPS). -TC) layer module, specific application interface, and operation management interface. The transmitted data is input to the TPS-TC layer module through the specific application interface of the ATU, and processed by the PMS-TC layer module and the PMD layer module, and output to the corresponding port. The process is reversed on the corresponding ATU, and finally sent to the relevant device through the specific application interface. The MPS-TC layer module controls the processing of the PMS-TC layer module.

2 is a schematic diagram of the principle of the PMS-TC layer module in the sending direction specified in the ADSL2 protocol, and the ADSL2 protocol specifies that the PMS-TC layer module can process up to four logical bearer signals. The data of the track can therefore include up to four delay channels. For clarity and clarity, Figure 2 shows only one of the delay channels. As shown in FIG. 2, the delay channel includes a framer, a scrambling unit, an RS encoder, an interleaver, and a CRC checker, and data of a logical bearer frame and an overhead channel from the TPS-TC layer module are formed in the framer. The data frames are multiplexed, then scrambled, RS-encoded, and interleaved, and the data is stored in the RAM. Finally, the data is sent to the PMD layer module in units of L bits through parallel-to-serial conversion.

3 is a schematic diagram showing changes in the structure of a data frame in the delay channel shown in FIG. 2, wherein data, B, C, and D are data at four points A, B, C, and D in FIG. 2, respectively. Data A is a multiplexed data frame MDF formed after passing through the framer; data B is a FEC data frame formed by the scrambling unit and the RS encoder, and has a total of N bytes, including M0 MDF and R0 redundant error correction. The data C is data obtained by interleaving the FEC data frame; the data D is the symbol data obtained by decomposing the data C, and is sent to the PMD layer module, and each symbol includes L bits.

In Figure 3, the FEC data frame ranges from 1 to 255 bytes, which is 1 < N < 255. According to the ADSL2 protocol, data is processed in bytes at the PMS-TC layer, and processed in bits at the PMD layer, and 4K symbols are transmitted every second. Therefore, after the data is interleaved in the PMS-TC layer module, the N bytes of data are decomposed into symbol data and sent to the PMD layer module for bit processing. According to the ADSL2 protocol, the value of L ranges from 0 bits to 4080 bits. As can be seen from the above, if L is not a multiple of 8, data loss is likely to occur between the PMS-TC layer and the PMD layer.

In the ADSL protocol, data is required to be processed in units of bytes, and there is no problem of byte and bit rate coordination between the transport layer and the physical layer. Therefore, if the channel coding circuit of the existing ADSL system is directly used to implement ADSL2 In the PMS-TC layer of the protocol, data loss will definitely occur. Summary of the invention

The present invention has been made in view of the above technical problems in the prior art, and an object thereof is to provide a method for realizing rate conversion of transmitting convergence layer data in an asymmetric digital subscriber line (ADSL) system, which can satisfy PMS-TC layer data. The data rate in the ADSL2 protocol is 4K steps. And no data is lost.

Another object of the present invention is to provide an apparatus for implementing the above method, which is realized

The consistency between the byte processing of the PMS-TC layer and the bit processing of the PMD layer, the circuit implementation is simple.

According to an aspect of the present invention, a method for implementing rate conversion by transmitting convergence layer data in an ADSL system is provided, and the number of bytes of a PMS-TC layer data frame is configured according to a transmission rate of the system to ensure a PMS-TC layer and Matching of data rates between PMD layers.

The method specifically includes: configuring the number of bits included in one symbol of the PMS-TC layer; determining the bit rate used for data transmission; and processing the data of the logical bearer channel in the processing of the PMS-TC layer by using the following configuration:

If the number of bits is between 1 and 255 bits and the bit rate does not exceed 1.02 MHz, it is determined that the number of symbols corresponding to one FEC frame is 8, and the number of bytes actually included in the FEC frame is the same as the number of bits;

If the number of bits is between 256 and 2040 bits, and the bit rate exceeds 1.02 MHz and does not exceed 8.16 MHz, determining that the number of symbols corresponding to one FEC frame is 1; determining whether the number of bits is an integer multiple of 8, if , determining that the number of bytes actually included in the FEC frame is one-eighth of the number of bits; if not an integer multiple of 8, the number of FEC frames in the transmission direction is cyclically counted in the range of 0 to 7, and the count is counted. Whether the value is smaller than the number of bits and the remainder of 8, and if so, determining that the number of bytes actually included in the FEC frame is the number of bits divided by 8 and then rounded up; otherwise, the byte actually included in the FEC frame is determined. The number is the number of bits divided by 8 and rounded up;

If the number of bits is between 2041 and 4080 bits, and the bit rate exceeds 8.16 MHz and does not exceed 16.32 ΜΗζ, determining that the number of symbols corresponding to one FEC frame is 0.5; determining whether the number of bits is an integer multiple of 16, If yes, it is determined that the number of bytes actually included in the FEC frame is one-sixteenth of the number of bits; if not an integer multiple of 16, the number of FEC frames in the transmission direction is cyclically counted in the range of 0 to 15. And determining whether the count value is smaller than the remainder of the number of bits and 16, if yes, determining that the number of bytes actually included in the current FEC frame is the number of bits divided by 16, and then rounding up and adding 1; otherwise, determining the actual FEC frame. The number of bytes included is the number of bits divided by 16 and rounded up. According to another aspect of the present invention, an apparatus for implementing the above method is provided, comprising: a configuration register for registering a number of bits included in a symbol of a PMS-TC layer and a number of bytes of a corresponding FEC frame, and providing a channel coding circuit, a parameter control circuit and a control register; a parameter control circuit for generating a signal for controlling the number of bytes actually contained in the FEC frame, and providing the signal to the control register;

A control register that registers the number of bytes actually contained in the FEC frame and provides it to the channel coding circuit.

The parameter control circuit further includes:

FEC frame counter, used to count the sent FEC frame;

A modulo operation unit is configured to perform a modulo operation on the number of bits included in one symbol with 8 or 16; and a comparator for comparing the number of FEC frames with the result of the modulo operation.

Preferably, the FEC frame counter uses a counter of mode 8.

The invention realizes the bit processing of data conversion from the byte processing of the PMS-TC layer to the PMD layer in the ADSL system, and the byte-based data from the PMS-TC layer can satisfy the PMS layer of the ADSL2 protocol. The byte processing requirements can meet the requirement of the bit rate increase of the PMD layer, and realize the 4K stepping of the data rate in the ADSL system. Further, the implementation device of the present invention has a simple structure and is easy to verify. DRAWINGS

1 is a schematic diagram of a single function of a transceiver unit in an ADSL2 protocol;

2 is a schematic diagram showing the principle of a delay channel of the PMS-TC layer module in the transceiver unit shown in FIG. 1;

3 is a schematic diagram showing changes in a data frame structure in the delay channel shown in FIG. 2. FIG. 4 is a flowchart of a method for realizing rate conversion by transmitting convergence layer data in an ADSL system according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of an apparatus for realizing rate conversion by transmitting convergence layer data in an ADSL system according to an embodiment of the present invention. detailed description

The above and other objects, features and advantages of the present invention will become more apparent from

Figure 1, Figure 2 and Figure 3 all describe the relevant content of the ADSL2 protocol, which has been described in the background section, and will not be described here.

4 is a flow diagram of a method of transmitting rate layer data to implement rate conversion, in accordance with one embodiment of the present invention. In step 401, the system configures the number L of bits included in a symbol, that is, the byte data of the PMS-TC layer is decomposed into the number of bits per symbol included when the symbol data in bits is sent to the PMD layer. According to the ADSL2 protocol, the value range of L is 0 bits < L < 4080 bits. Then, in order to ensure the same rate between the PMS-TC and the PMD layer, the data of the logical bearer channel is processed in the following configuration in the processing of the PMS-TC layer.

In step 410, if the number of bits L is between 1 and 255 bits and the bit rate R is less than 1.02 MHz, then in step 411, one is configured: the number of symbols S corresponding to the FEC frame is 8, and the word actually contained in the FEC frame The number of sections NO is the same as the number of bits L, that is, N0 = L.

In step 420, if the bit number L is between 256 and 2040 bits and the bit rate satisfies 1.02 MHz < R < 8.16 MHz, then in step 421, the number of symbols S corresponding to one FEC frame is set to 1. Then at step 422, it is judged whether or not the bit number L is an integral multiple of 8, that is, whether 1^/ is satisfied. 8=0. If so, then in step 423, it is determined that the number of bytes actually contained in the FEC frame, NO, is one-eighth of the number of bits L, that is, N0 = L/8. If L is not an integer multiple of 8, then in step 424, the number of FEC frames in the transmission direction is cyclically counted in the range of 0 to 7, and it is judged whether the count value is smaller than the remainder of the number of bits L and 8 (L% 8) . If yes, then in step 425, it is determined that the number of bytes actually contained in the FEC frame is NO, the number of bits is divided by 8, and then rounded up and then added, that is, N0=[L/8]+l, where "[],, The rounding operation is performed. Otherwise, in step 426, it is determined that the number of bytes actually contained in the FEC frame, NO, is the number of bits divided by 8, and is rounded, that is, N0 = [L/8].

In step 430, if the number of bits L is between 2041 bits and 4080 bits and the bit rate R satisfies 8.16 MHz < R < 16.32 MHz, then in step 431, the number of symbols S corresponding to one FEC frame is configured to be 0.5. Then, at step 432, it is judged whether or not the bit number L is an integer multiple of 16, that is, whether 1 1⁄416=0 is satisfied. If yes, then in step 433, it is determined that the FEC frame actually contains The number of bytes NO is one-sixteenth of the number L of bits, that is, N0=L/16. If L is not an integer multiple of 16, then in step 434, the number of transmission direction FEC frames is cyclically counted in the range of 0 to 15, and it is judged whether or not the count value is smaller than the remainder of the number of bits L and 16 (L% 16). If yes, then in step 435, it is determined that the number of bytes actually contained in the FEC frame is the number of bits L divided by 16 and then rounded up and then added, that is, N0=[L/16]+1, where "[]" indicates Rounding the operation. Otherwise, in step 436, it is determined that the number of bytes NO actually contained in the FEC frame is rounded up by the number of bits L divided by 16, i.e., N0 = [L/16].

As apparent from the above description, with the present embodiment, data can be converted from the byte processing of the PMS-TC layer to the bit processing of the PMD layer without losing data.

Figure 5 is a block diagram showing the structure of a device for transmitting rate layer data to implement rate conversion according to an embodiment of the present invention. As shown in FIG. 5, the apparatus includes: a configuration register 10, wherein the number of bits L included in one symbol of the system configuration and the number of bytes N included in the system-configured FEC frame are stored. According to the ADSL2 protocol, the value range of N is 1 byte <N < 255 bytes. The configuration relationship between the bit number L and the number of bytes N is: 1) When 1 < L < 255 bits, the bit rate 11 < 1.02 MHz, N = L; 2) When 256 < L < 2040 bits, the bit rate is 1.02 MHz <R< 8.16MHz, if L%8 = 0, then N = L/8; if L%8≠0, then N=[L/8]+l, where "[], means rounding; 3 When 2041 <L< 4080 bits, the bit rate is 8.16MHz<R< 16.32MHz. If L%16 = 0, then N = L/16; ^L%16≠0, then N=[L/16]+ 1. The configuration register 10 supplies the configured bit number L to the parameter control circuit 20 and the channel coding circuit, and outputs the configured number of bytes N to the control register 30.

Also included in the apparatus is a parameter control circuit 20 for generating a signal for controlling the number of bytes NO actually contained in the FEC frame, and outputting it to the control register 30 to select the corresponding configured number of bytes N as the FEC frame actually contains The number of bytes N0 is written to the control register 30. The parameter control circuit 20 further includes an FEC frame counter 201, a modulo operation unit 202, and a comparator 203, wherein the FEC frame counter 201 counts the FEC frame transmitted after the system is started, and outputs the count value Counter to the comparator 203; 202, the modulo operation is performed on the configured number of bits L and 8 or 16, and the result is also output to the comparator 203. The comparator 203 compares the number of the FEC frame Counter with the modulo operation result, and the comparison result is used as the actual FEC frame control. Inclusion The signal of the number of bytes NO is output to the control register 30. The relationship between the comparison result and the number of bytes actually contained in the FEC frame is as follows: 1) When 1 < L < 255 bits, the bit rate 11 < 1.02 MHz, N0 = N; 2) When 256 < L < 2040 bits, the bit The rate is 1.02MHz<R< 8·16ΜΗζ, if L % 8 = 0, then NO - N; if LQ/o 8≠ 0, then if the comparison result is Counter<L%8, then N0-N; If the comparison result For Counter >L%8, then N0-N-1; 3) When 2041 <L< 4080 bits, the bit rate is 8.16MHz<R< 16.32MHz, if 1 / ₀ 16 = 0, M NO = N; %16≠0, if the comparison result is Counter<L%16, M N0=N; if the comparison result is Counter >L%16, then N0=N-1.

Further, a control register 30 is included in the apparatus in which the number of bytes N0 actually contained in the FEC frame is stored and supplied to the channel coding circuit.

When the system is started, the number of bits contained in one symbol of the configuration is written into configuration register 10. According to L, the data transmission rate R of the system and the number of bytes N of the FEC frame configured by the system can be obtained. The parameter control circuit 20 compares the value of the FEC frame counter 201 with the result of the modulo operation unit 202 according to the configured L, and generates a control signal for the number of bits N0 actually contained in the FEC frame written to the control register 30, according to the above. The configuration relationship between the parameters writes the number of bits N0 actually contained in the corresponding FEC to the control register 30, and then is supplied to the channel coding circuit by the control register 30 to achieve a 4K step of the data rate.

As can be seen from the above description, with the embodiment, the consistency between the byte processing and the bit processing of the data can be realized, and the circuit used is simple to implement.

Claims

Rights request

A method for realizing rate conversion of transmission convergence layer data in an asymmetric digital subscriber line system, characterized in that: according to a transmission rate of the system, configuring a number of bytes of a transmission aggregation layer data frame to ensure a transmission convergence layer and Matching of data rates between physical media related layers.

The method according to claim 1, characterized in that: the system configures the number of bits included in one symbol of the transmission aggregation layer; determines the bit rate used for data transmission; and processes the data of the logical bearer channel in the transmission convergence layer In the following configuration, the following configuration is used:

If the number of bits is between 2041 bits and 4080 bits, the bit rate exceeds 8.16 MHz and does not exceed 16.32 MHz, determining that the number of symbols corresponding to one FEC frame is 0.5; determining whether the number of bits is an integer multiple of 16, if If yes, it is determined that the number of bytes actually included in the FEC frame is one-sixteenth of the number of bits; if not an integer multiple of 16, the number of FEC frames in the transmission direction is cyclically counted in a range of 0 to 15. Determining whether the count value is smaller than the number of bits and the remainder of 16, and if so, determining that the number of bytes actually included in the FEC frame is the number of bits divided by 16, and then rounding up and adding 1; otherwise, determining the actual inclusion of the FEC frame The number of bytes is rounded up by dividing the number of bits by 16.

An apparatus for transmitting a convergence layer data in an asymmetric digital subscriber line system to implement rate conversion, comprising: a configuration register for registering the number of bits included in one symbol of the configuration transmission convergence layer and the number of bytes of the corresponding FEC frame, and providing the channel coding circuit, the parameter control circuit, and the control register; and the control circuit for generating the control FEC frame actually a signal containing the number of bytes and supplied to the control register;

4. The apparatus according to claim 3, wherein the parameter control circuit further comprises:

An EEC frame counter for counting the transmitted FEC frames;

The apparatus for realizing rate conversion by transmitting convergence layer data in an ADSL system according to claim 3, wherein the FEC frame counter is a counter of mode 8.