WO2006122957A2 - Mos power device with high integration density and manufacturing process thereof - Google Patents

Mos power device with high integration density and manufacturing process thereof Download PDF

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WO2006122957A2
WO2006122957A2 PCT/EP2006/062394 EP2006062394W WO2006122957A2 WO 2006122957 A2 WO2006122957 A2 WO 2006122957A2 EP 2006062394 W EP2006062394 W EP 2006062394W WO 2006122957 A2 WO2006122957 A2 WO 2006122957A2
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opening
forming
contact
region
body region
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PCT/EP2006/062394
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French (fr)
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WO2006122957A3 (en
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Giuseppe Curro'
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Stmicroelectronics S.R.L.
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Publication of WO2006122957A3 publication Critical patent/WO2006122957A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Definitions

  • the present invention relates to a MOSFET device with high integration density, in particular of the type comprising a plurality of elementary strips in active area, and to the manufacturing process thereof.
  • the invention regards, in particular, but not exclusively, a power vertical-current MOS device (power VDMOS) with a submicrometric strip-shaped cell without any lateral contact, and the following description makes reference to this field with the sole purpose of simplifying exposition thereof.
  • power VDMOS power vertical-current MOS device
  • the most effective planar technology for manufacturing power-VDMOS devices having low drain-to-source on-resistance Rdson i.e., the resistance of the conductive path comprised between the drain region and the source region
  • Rdson drain-to-source on-resistance
  • a plurality of gate electrodes, also strip-shaped extend on top of the active strips, staggered with respect to the bulk regions.
  • a source contact is generally formed between two gate electrodes, and short- circuits the respective source region or regions with the body region that houses them. The source contact is insulated with respect to the gate electrodes by an electrical insulation layer extending on the side walls of the gate electrodes.
  • the reduction of the planar dimensions of the devices causes, during the manufacturing process, problems regarding forming the lateral-insulation layer .
  • the lateral-insulation layer is formed as self-aligned spacer, this has a very small thickness that does not always guarantee the necessary continuity; in this case, the short-circuit may occur between the gate electrode and the source contact. This leads to an increase in the failure rate of the device, above all in devices having a very large channel perimeter (with a length of several ???metres) and hence a very low Rdson resistance.
  • the active strip must have a width at least equal to 0.6 ⁇ m, so as to reach a trade-off between two different requirements: providing a sufficiently wide source contact to enable a good filling by the metallization, so as to obtain a low linear resistance and a low contact resistance; and providing, within the strip, a sufficiently thick lateral-insulation layer to guarantee continuity throughout the channel perimeter of the device.
  • the first of the two requirements not only requires the opening between the gate electrodes to be as large as possible, but also the vertical profile of the opening to be tapered in the top part to minimize the formation of voids in the metal on the contact surface. Consequently, this frequently determines the presence of a step or an obtuse edge in the vertical profile of the lateral- insulation layer. This, in turn, causes an increase, that may at times even be drastic, in the failure rate due to short circuits between the gate electrode and the source region.
  • Another problem resides in the poor mechanical strength of the lateral-insulation layer during the back-end processes, such as assembly, and in response to thermomechanical stresses exerted on the device for evaluating its reliability.
  • the aim of the present invention is to provide a MOSFET semiconductor device that will meet the above requirements .
  • MOSFET semiconductor device and the manufacturing process thereof, as defined in claims 1 and 9, respectively.
  • the idea underlying the invention is that of reducing the width of the opening extending on top of the active strip between two adjacent gate electrodes to have submicrometric dimensions, i.e., at the limit of the resolution factor of the photo exposure equipment.
  • the opening can then be filled with dielectric material that functions as insulation.
  • the contact areas of the source metallization and the source and body areas of diffused silicon are reduced to a finite and small number of islands or contact cells of a greater width than the opening and set periodically along each active strip.
  • these islands or contact cells are separated from the gate electrodes by a lateral insulation, obtained via a self-aligned spacer or via contact masking. Consequently, it is possible to eliminate, in the active strip that contains the channel, the contact between body and source, reserving the opening of a contact window only to the contact cells of a larger width than or equal to the channel strip and arranged periodically along the strip.
  • the surface conductivity and the conductivity of the source and body contact are increased considerably by forming, on the surface of the diffused regions within each active strip, a thin conductive layer, for example a metal-silicide layer, which is then coated by the insulation dielectric layer on top of the active strip.
  • a thin conductive layer for example a metal-silicide layer
  • the insulation dielectric layer on top of the active strip.
  • the contact for the source and body metallization is opened at the islands or contact cells, which are, for example, hexagonal or of any appropriate polygonal shape, interleaved with the channel regions along the active strip.
  • the contact window can be opened either in a completely self-aligned way with the cell via a spacer of dielectric material or through a dedicated photolithography, using well known implementation processes .
  • the device is obtained without any photomask for source-contact definition acting in the active area; the contact within the contact cell or periodic island is opened using a self-aligned spacer.
  • the contact photomask is in any case present on the edge and pad regions where opening of gate contacts is required.
  • the source-contact window in the periodic contact cells along the active strips are opened using a photomask. This solution enables wider dimensions of the periodic contact cell, where necessary.
  • the total filling of the active (submicrometric) strip with dielectric is accompanied by the presence of the source diffusion along the entire active strip, co-axial to the body diffusion, which entails maximization of the channel perimeter.
  • surfacing of the body diffusion is allowed only in one portion of the contact cell thanks to a source implantation using a photomask that is not particularly critical and involves only the contact cell.
  • Said solution enables active strips to be formed having a width smaller or equal to 400 nm in the channel region.
  • FIG. 1 shows a top plan view of the masks used for obtaining the gate electrodes and the source contacts, according to an embodiment of the invention
  • FIGS. 2a-9a show cross-sectional views of the device, taken along line A-A of Figure 1, corresponding to manufacturing steps of the MOSFET device according to a first embodiment of the invention
  • FIG. 2b-9b show cross-sectional views of the device, taken along line B-B of Figure 1, corresponding to the same manufacturing steps of the MOSFET device of Figures 2a-9a;
  • FIG. 10a-17a show cross-sectional views of the device, taken along line A-A of Figure 1 and corresponding to successive manufacturing steps of the present device, according to a second aspect of the invention;
  • FIG. 10b-17b show cross-sectional views of the device, taken along line B-B of Figure 1 and corresponding to successive manufacturing steps of the present device, according to a second aspect of the invention
  • FIGS 18a-21a show cross-sectional views of the device, taken along line A-A of Figure 1 and corresponding to successive manufacturing steps of the present device, according to a third aspect of the invention.
  • FIG. 18b-21b show cross-sectional views of the device, taken along line B-B of Figure 1 and corresponding to successive manufacturing steps of the present device, according to a third aspect of the invention.
  • Figure 1 shows a top plan view of the masks used for manufacturing a MOSFET device, here a VDMOS transistor 1, and specifically shows a gate mask 2 and a source mask 3, described in greater detail with reference to the description of an embodiment of the manufacturing process.
  • a wafer 10 of semiconductor material comprises a highly doped substrate 11
  • a thin gate-dielectric layer 13 is formed on top of the epitaxial layer 12 and has, for example, a thickness of less than 100 nm.
  • the gate-dielectric layer 13 can be formed via a thermal oxidation, or else via the depositing an oxynitride layer or a multilayer formed by the superposition of successive oxide and nitride layers.
  • a gate-electrode layer 14 is deposited on top of the gate- dielectric layer 13 and comprises polysilicide (intrinsic and doped subsequently by ion implantation, or else, possibly, already doped in the deposition step) , for a thickness of between 100 nm and 600 nm.
  • a double layer can be deposited, formed by doped polysilicide and metal suicide.
  • a phototechnique for defining the gate electrodes is performed, thereby obtaining the gate mask 2.
  • a one-directional etch of the first dielectric layer 16 is performed, with end-point on the gate-electrode layer 14, and a one-directional etch of the gate-electrode layer 14 is performed, for a fixed time or with end-point on the gate- dielectric layer 13.
  • the gate-dielectric layer 13 can be partially dry etched to reduce its thickness or else it can be removed altogether with an etch with end-point on the epitaxial silicon. Openings 15 are then formed, and extend through the first dielectric layer 16 and the gate-electrode layer 14, until the gate-dielectric layer 13 or else until the epitaxial layer 12 is reached (as shown in Figures 2a and 2b) .
  • the gate electrodes are strip shaped, extend in a first direction (in Figure 1, in the direction X) and here have a constant width S (typically of between 1 ⁇ m and 2 ⁇ m, for example 1.6 ⁇ m) , and a distance d
  • the openings 15 comprise elongated portions or windows 15a of width d (equal to the distance between the gate electrodes 14) and contact cells 18, which are wider.
  • the contact cells 18 have a substantially hexagonal shape with a maximum width and length equal to L (typically of between 0.8 ⁇ m and 2.6 ⁇ m, for example, 1.2 ⁇ m) , and are arranged one after the other along each opening 15 periodically and at a distance W (typically of between 2 ⁇ m and 6 ⁇ m, for example, 4.8 ⁇ m) .
  • the contact cells 18 formed between adjacent gate electrodes 14 are aligned in a second direction perpendicular to the first direction (here, the direction Y) .
  • the contact cells 18 formed between adjacent gate electrodes 14 can be staggered in the direction Y by a fraction of the distance W.
  • the source mask 3 is defined photolithographically (see also Figure 1) , and ionic dopant species of an N type are implanted and diffused, giving rise to source regions 20, which, given the different diffusivity of the two dopant species, extend within the body wells 19, in a per se known manner.
  • the source regions 20 extend throughout the length of the windows 15a, but only in part of the contact cells 18, where the source mask 3 is present. In this way, within the contact cells 18, which, as has been said, have a width greater than that of the windows 15a, portions of the body wells 19 (surface portions 19a) extend as far as the surface 12a of the epitaxial layer 12 ( Figure 3b) .
  • the portions of the body wells 19 delimited between the source regions 20 and the epitaxial layer 12 underneath the gate electrodes 14 form channel regions 19b of the VDMOS device.
  • the masks 2 and 3 are then removed.
  • a thin oxide layer is formed, not shown in the drawings .
  • a double conformal layer of dielectric material is deposited; namely, a second dielectric material layer 21 and a third dielectric material layer 22 are deposited, made, for example, of silicon oxide and silicon nitride, respectively, for a total thickness of less than 50 nm.
  • a single layer of dielectric material for example, nitride.
  • the double dielectric material layer 21, 22 is etched unidirectionally (dry etch), forming sacrificial spacers, once again designated by 22, and leaving lateral-insulation regions 21 underneath the sacrificial spacers 22), and the thin oxide layer (not shown in the drawings) grown on the surface of the epitaxial layer 12 during the steps of body and source implantation is etched.
  • a metal material layer for example Co, Pt, Ti
  • a thermal treatment is performed to cause reaction of the metal material layer with the silicon where the latter is exposed (on top of the source regions 20 and of the surfacing portions 19a of the body wells 19) so as to obtain suicide regions 25 on the regions 19a and 20, and the residual metal is removed from the surfaces where it has not reacted (on top of the dielectric material) .
  • the source region 20 and the corresponding suicide region 25 hence forms a source structure.
  • an insulating layer 26 of dielectric material for example USG, PSG, TEOS or a multilayer of low-conformality materials is deposited by CVD, the thickness whereof, for example between 300 nm and 700 nm, depends upon the planar technology and is chosen so as to fill the windows 15 but as to have, on the bottom of the contact cells 18, a thickness smaller than the portions on top of the gate electrodes 14 (typically, from one third to one half of the thickness on top of the gate electrodes 14) .
  • dielectric material for example USG, PSG, TEOS or a multilayer of low-conformality materials
  • the insulating layer 26 is etched unidirectionally (dry etch) , with end-point on the suicide 25.
  • the insulating layer 26 is not removed from the windows 15a but is removed within the contact cells 18 (except for the vertical surface, where it forms spacers 26) .
  • the insulating layer 26 is moreover removed to a large extent also on the horizontal surfaces of the gate electrodes 14.
  • a barrier layer 27 (metallurgical barrier to contact formed by a Ti/TiN multilayer or the like) is deposited, and a metal layer 28 formed by an aluminium alloy is deposited on the front.
  • the metal layer 28 and the barrier layer 27 thus together form a source metallization 29, which comprises first portions extending on top of the insulating layer 26 and second portions extending within the contact cells 18.
  • the second portions of the metal layer 28 are in direct electrical contact with the source structures 20, 25 and with the body surfacing portions 19 only at the contact cells 18 (where there is thus a vertical current flow) .
  • the first portions of the metal layer 28 on top of the windows 15a are in indirect electrical contact with the underlying source structures 20, 25, and precisely through the second portions of the metal layer (within the contact cells 18) and the suicide layers 25, with passage of current in a horizontal direction, along the suicide layers 25b.
  • the size of the contact cells 18 is such as not to enable formation of portions of the insulating layer 16 with reduced thickness on the bottom of the cells. In this case, opening of the source contacts can be obtained with a phototechnique . Consequently, it is no longer necessary for the gate electrodes 14 to be protected by the first insulating layer 16, and this may be absent.
  • Figures 10a-18a, 10b-18b refer to this situation, and will be described hereinafter only as regards the steps whereby they differ from Figures 2- 9.
  • the initial steps are similar to those of Figures 2a-5a and 2b-5b, except for the absence of the first dielectric layer 16, as may be noted from Figures 10a-13a and 10b-13b.
  • suicide regions 25a are formed on top of the gate electrodes 14, in addition to suicide regions 25b on the regions 19a and 2Oe ( Figures 14a, 14b) .
  • Figures 16a, 16b which coats the entire surface of the wafer 10, except for windows 31 within the contact cells 18 and, in a way not shown, except for contact windows on the gate pad designed for bonding in the step of assembly of the device.
  • Windows can moreover be provided for possible regions on the edge termination again designed for perimetral contact between the metallization and the gate electrode. Then the insulating layer 16 is etched within the windows 31 as well as on the edge termination and on the bonding pad, with end-point on the suicide regions 25b.
  • Figures 17a, 17b show the structure after forming the source metallization 29.
  • the process follows the steps illustrated in Figures 10a-17a, 10b-17b, with the difference that the insulating layer 16 is deposited on top of the gate electrodes 14 and thus no suicide regions
  • a dry etch of the exposed silicon is performed to form soft trenches.
  • a dry etch is performed for a fixed time, thereby forming recesses 35 in the epitaxial layer 12, which extend as far as the body regions 19 (see Figures 18a, 18b) .
  • the suicide regions 25 are formed ( Figures 19a, 19b) .
  • the suicide regions 25 cover the bottom of the recesses 35, where they contact the body regions 19, and the side walls of the recesses 35, where they contact the source region 20.
  • the sacrificial spacers 22 are removed, and an insulating layer 26 is deposited by CVD and then densified ( Figures 20a, 20b) .
  • the insulating layer 26 is etched unidirectionally, and ( Figures 21a, 21b) the source metallization 29 is deposited (formed also here by the barrier layer 27 and by the front- metal layer 28) .
  • the final steps already described above follow.
  • the contact between the source metallization 29, the body regions 19 and the source regions 20 occurs only at the contact cells 20.
  • the manufacturing process described thus enables a reduction in the dimensions of the device and has a high yield. Therefore the device thus obtained presents a reduced cost and high performance, in addition to affording excellent insulation characteristics.
  • the shape of the contact cells 18 can vary with respect to the one shown, for example, it may be square, rectangular, polygonal, or even circular or oval.
  • the dimensions of the contact cells 18 are moreover chosen on the basis of the specific characteristics of the process and of the materials used, provided that they are such as to guarantee a sufficient removal of the insulating layer 26 from the contact cells.
  • Figure 1 shows only one of the numerous possibilities of layout.
  • the elongated portions or windows 15a of the openings 15 may even have a variable width, if necessary, but in any case preferably close to the lithographic minimum one, in order to be able to exploit the dimensional advantages referred to.
  • the source mask can be modified so as to eliminate the protective portions at the contact cells 18, except for at the short terminations of the active strips, where in any case protective portions must be present to prevent the source implantation and hence prevent formation of the channel regions 19b.

Abstract

MOSFET device formed in a semiconductor layer (12) overlaid by an insulated-gate structure (13, 14, 21) having at least two gate electrodes (14), of semiconductor material, which extend at a distance from one another and delimit between them a strip-shaped opening (15). The semiconductor layer accommodates a strip-shaped body region (19), which in turn accommodates a source region (20). A source-contact metal region (29) extends at least partially in the opening (15) and is in electrical contact with the body region (19) and the source structure (20, 25). The opening (15) is formed by elongated windows (15a) and contact cells (18) extending between pairs of consecutive elongated windows. The elongated windows (15) are filled with dielectric spacer material (26), and the metal contact structure (29) has first portions extending above the opening (15) at the elongated windows (15a) and second portions extending within the opening at the contact cells (18) and in direct electrical contact with the source structure (20, 25).

Description

MOSFET DEVICE WITH HIGH INTEGRATION DENSITY, IN PARTICULAR POWER VDMOS, AND MANUFACTURING PROCESS THEREOF
TECHNICAL FIELD The present invention relates to a MOSFET device with high integration density, in particular of the type comprising a plurality of elementary strips in active area, and to the manufacturing process thereof.
The invention regards, in particular, but not exclusively, a power vertical-current MOS device (power VDMOS) with a submicrometric strip-shaped cell without any lateral contact, and the following description makes reference to this field with the sole purpose of simplifying exposition thereof.
BACKGROUND ART
As is well known, currently, in the field of power VDMOS devices manufactured using low-consumption power technologies, it is necessary to reduce the planar dimensions of the devices in order to increase their integration density. Currently, the most effective planar technology for manufacturing power-VDMOS devices having low drain-to-source on-resistance Rdson, i.e., the resistance of the conductive path comprised between the drain region and the source region, provides, within the active area, a plurality of strip-shaped bulk regions, so- called active strips. A plurality of gate electrodes, also strip-shaped, extend on top of the active strips, staggered with respect to the bulk regions. A source contact is generally formed between two gate electrodes, and short- circuits the respective source region or regions with the body region that houses them. The source contact is insulated with respect to the gate electrodes by an electrical insulation layer extending on the side walls of the gate electrodes.
In this type of devices, the reduction of the planar dimensions of the devices causes, during the manufacturing process, problems regarding forming the lateral-insulation layer .
In particular, in the cases where the active strips are very- narrow (< 0.4 μm) , it is impossible, during the manufacturing process of the device, to define, via photolithography, the source contact within the active strips, since it is not possible to obtain either a good definition of the window of the photoresist used for photolithography or a sufficiently "margined" alignment of the window.
Furthermore, if the lateral-insulation layer is formed as self-aligned spacer, this has a very small thickness that does not always guarantee the necessary continuity; in this case, the short-circuit may occur between the gate electrode and the source contact. This leads to an increase in the failure rate of the device, above all in devices having a very large channel perimeter (with a length of several ???metres) and hence a very low Rdson resistance.
Consequently, the active strip must have a width at least equal to 0.6 μm, so as to reach a trade-off between two different requirements: providing a sufficiently wide source contact to enable a good filling by the metallization, so as to obtain a low linear resistance and a low contact resistance; and providing, within the strip, a sufficiently thick lateral-insulation layer to guarantee continuity throughout the channel perimeter of the device.
Furthermore, the first of the two requirements not only requires the opening between the gate electrodes to be as large as possible, but also the vertical profile of the opening to be tapered in the top part to minimize the formation of voids in the metal on the contact surface. Consequently, this frequently determines the presence of a step or an obtuse edge in the vertical profile of the lateral- insulation layer. This, in turn, causes an increase, that may at times even be drastic, in the failure rate due to short circuits between the gate electrode and the source region.
Another problem resides in the poor mechanical strength of the lateral-insulation layer during the back-end processes, such as assembly, and in response to thermomechanical stresses exerted on the device for evaluating its reliability.
It is consequently clear that, also for currently more scaled technologies, there exists a dimensional limit linked, above all, to the wafer electrical yield and to the robustness, from the reliability standpoint, of the lateral-insulation layer. On the other hand, the dimensional limit determines an overall increase in the cost of the device.
Consequently, it is particularly important to identify new strategies to increase the electrical yield for planar technologies and increasingly scale the dimensions of the device .
DISCLOSURE OF INVENTION
The aim of the present invention is to provide a MOSFET semiconductor device that will meet the above requirements .
According to the present invention, there are provided a MOSFET semiconductor device and the manufacturing process thereof, as defined in claims 1 and 9, respectively.
The idea underlying the invention is that of reducing the width of the opening extending on top of the active strip between two adjacent gate electrodes to have submicrometric dimensions, i.e., at the limit of the resolution factor of the photo exposure equipment. The opening can then be filled with dielectric material that functions as insulation. To this end, the contact areas of the source metallization and the source and body areas of diffused silicon are reduced to a finite and small number of islands or contact cells of a greater width than the opening and set periodically along each active strip. Advantageously, these islands or contact cells are separated from the gate electrodes by a lateral insulation, obtained via a self-aligned spacer or via contact masking. Consequently, it is possible to eliminate, in the active strip that contains the channel, the contact between body and source, reserving the opening of a contact window only to the contact cells of a larger width than or equal to the channel strip and arranged periodically along the strip.
Conveniently, in order to reduce the impact of the reduction in the contact areas on silicon on the resistance of the device and on the robustness to switching, the surface conductivity and the conductivity of the source and body contact are increased considerably by forming, on the surface of the diffused regions within each active strip, a thin conductive layer, for example a metal-silicide layer, which is then coated by the insulation dielectric layer on top of the active strip. This guarantees the physical short-circuit between the top surface of the body region and that of the source region. Furthermore, the absence of source interruptions within the active strip contributes considerably to minimizing the drain-to-source on-resistance Rdson per unit area of the device.
The contact for the source and body metallization is opened at the islands or contact cells, which are, for example, hexagonal or of any appropriate polygonal shape, interleaved with the channel regions along the active strip. The contact window can be opened either in a completely self-aligned way with the cell via a spacer of dielectric material or through a dedicated photolithography, using well known implementation processes .
According to a first embodiment of the invention, the device is obtained without any photomask for source-contact definition acting in the active area; the contact within the contact cell or periodic island is opened using a self-aligned spacer. The contact photomask is in any case present on the edge and pad regions where opening of gate contacts is required. With this solution, limits are present on the dimensions of the periodic window to be able to provide a lateral-insulation spacer without the use of masks and exploiting the properties of non-conformality of the insulation-dielectric layer.
In a second embodiment of the invention, the source-contact window in the periodic contact cells along the active strips are opened using a photomask. This solution enables wider dimensions of the periodic contact cell, where necessary.
In either case, an important structural factor is achieved. The total filling of the active (submicrometric) strip with dielectric is accompanied by the presence of the source diffusion along the entire active strip, co-axial to the body diffusion, which entails maximization of the channel perimeter. In this way, surfacing of the body diffusion is allowed only in one portion of the contact cell thanks to a source implantation using a photomask that is not particularly critical and involves only the contact cell. Said solution enables active strips to be formed having a width smaller or equal to 400 nm in the channel region.
In either case, after forming a spacer within the opening, it is moreover possible to vertically etch the silicon for forming a soft trench; thereby a short circuit is ensured between source and body by the subsequent silicidation along the entire active strip (and not only within the periodic contact cells) . This solution is advantageous as regards switching robustness of the device, but increases the distributed source-contact resistance and hence, in part, the Rdson of the device. BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the invention, some embodiments are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein: - Figure 1 shows a top plan view of the masks used for obtaining the gate electrodes and the source contacts, according to an embodiment of the invention;
- Figures 2a-9a show cross-sectional views of the device, taken along line A-A of Figure 1, corresponding to manufacturing steps of the MOSFET device according to a first embodiment of the invention;
- Figures 2b-9b show cross-sectional views of the device, taken along line B-B of Figure 1, corresponding to the same manufacturing steps of the MOSFET device of Figures 2a-9a; - Figures 10a-17a show cross-sectional views of the device, taken along line A-A of Figure 1 and corresponding to successive manufacturing steps of the present device, according to a second aspect of the invention;
- Figures 10b-17b show cross-sectional views of the device, taken along line B-B of Figure 1 and corresponding to successive manufacturing steps of the present device, according to a second aspect of the invention;
- Figures 18a-21a show cross-sectional views of the device, taken along line A-A of Figure 1 and corresponding to successive manufacturing steps of the present device, according to a third aspect of the invention; and
- Figures 18b-21b show cross-sectional views of the device, taken along line B-B of Figure 1 and corresponding to successive manufacturing steps of the present device, according to a third aspect of the invention.
BEST MODE FOR CARRYING OUT THE INVENTION
Figure 1 shows a top plan view of the masks used for manufacturing a MOSFET device, here a VDMOS transistor 1, and specifically shows a gate mask 2 and a source mask 3, described in greater detail with reference to the description of an embodiment of the manufacturing process. With reference to Figures 2a and 2b, a wafer 10 of semiconductor material comprises a highly doped substrate 11
(for example, of N+ type) and a less doped semiconductor layer (in the example, of N type) , for instance grown epitaxially on top of the substrate 11 (epitaxial layer 12) .
After forming edge-termination structures and after pre- cleaning, per se known and hence not described in detail herein, a thin gate-dielectric layer 13 is formed on top of the epitaxial layer 12 and has, for example, a thickness of less than 100 nm. The gate-dielectric layer 13 can be formed via a thermal oxidation, or else via the depositing an oxynitride layer or a multilayer formed by the superposition of successive oxide and nitride layers.
A gate-electrode layer 14 is deposited on top of the gate- dielectric layer 13 and comprises polysilicide (intrinsic and doped subsequently by ion implantation, or else, possibly, already doped in the deposition step) , for a thickness of between 100 nm and 600 nm. Alternatively, a double layer can be deposited, formed by doped polysilicide and metal suicide. Furthermore, a first dielectric layer 16, for example of USG, PSG, TEOS or other dielectric multilayer, is deposited by CVD.
Next (see also Figure 1) , a phototechnique for defining the gate electrodes is performed, thereby obtaining the gate mask 2. Then, a one-directional etch of the first dielectric layer 16 is performed, with end-point on the gate-electrode layer 14, and a one-directional etch of the gate-electrode layer 14 is performed, for a fixed time or with end-point on the gate- dielectric layer 13. In particular, the gate-dielectric layer 13 can be partially dry etched to reduce its thickness or else it can be removed altogether with an etch with end-point on the epitaxial silicon. Openings 15 are then formed, and extend through the first dielectric layer 16 and the gate-electrode layer 14, until the gate-dielectric layer 13 or else until the epitaxial layer 12 is reached (as shown in Figures 2a and 2b) .
Thereby, the gate electrodes (designated once again by 14) are strip shaped, extend in a first direction (in Figure 1, in the direction X) and here have a constant width S (typically of between 1 μm and 2 μm, for example 1.6 μm) , and a distance d
(typically of between 0.25 μm and 0.6 μm, for example 0.4 μm) , except for an area corresponding to regions (hereinafter, referred to also as contact cells 18) where the gate electrodes 14 are at a greater distance apart. In practice, the openings 15 comprise elongated portions or windows 15a of width d (equal to the distance between the gate electrodes 14) and contact cells 18, which are wider. In the example shown, the contact cells 18 have a substantially hexagonal shape with a maximum width and length equal to L (typically of between 0.8 μm and 2.6 μm, for example, 1.2 μm) , and are arranged one after the other along each opening 15 periodically and at a distance W (typically of between 2 μm and 6 μm, for example, 4.8 μm) . In addition, the contact cells 18 formed between adjacent gate electrodes 14 are aligned in a second direction perpendicular to the first direction (here, the direction Y) . Alternatively, the contact cells 18 formed between adjacent gate electrodes 14 can be staggered in the direction Y by a fraction of the distance W.
Then (Figures 3a and 3b) , ionic dopant species of a P type are implanted and diffused in the epitaxial layer 12, giving rise to body wells 19, which extend, to a first approximation, at the openings 15.
Next, the source mask 3 is defined photolithographically (see also Figure 1) , and ionic dopant species of an N type are implanted and diffused, giving rise to source regions 20, which, given the different diffusivity of the two dopant species, extend within the body wells 19, in a per se known manner. The source regions 20 extend throughout the length of the windows 15a, but only in part of the contact cells 18, where the source mask 3 is present. In this way, within the contact cells 18, which, as has been said, have a width greater than that of the windows 15a, portions of the body wells 19 (surface portions 19a) extend as far as the surface 12a of the epitaxial layer 12 (Figure 3b) . Furthermore, in a per se known manner, the portions of the body wells 19 delimited between the source regions 20 and the epitaxial layer 12 underneath the gate electrodes 14 form channel regions 19b of the VDMOS device. The masks 2 and 3 are then removed.
During the body and the source diffusions, on the exposed surface of the epitaxial layer 12 a thin oxide layer is formed, not shown in the drawings .
Then (Figures 4a and 4b) , a double conformal layer of dielectric material is deposited; namely, a second dielectric material layer 21 and a third dielectric material layer 22 are deposited, made, for example, of silicon oxide and silicon nitride, respectively, for a total thickness of less than 50 nm. Alternatively, it is possible to deposit a single layer of dielectric material, for example, nitride.
Next (Figures 5a and 5b) , the double dielectric material layer 21, 22 is etched unidirectionally (dry etch), forming sacrificial spacers, once again designated by 22, and leaving lateral-insulation regions 21 underneath the sacrificial spacers 22), and the thin oxide layer (not shown in the drawings) grown on the surface of the epitaxial layer 12 during the steps of body and source implantation is etched.
Next (Figures 6a and 6b) , a metal material layer (for example Co, Pt, Ti) is deposited, a thermal treatment is performed to cause reaction of the metal material layer with the silicon where the latter is exposed (on top of the source regions 20 and of the surfacing portions 19a of the body wells 19) so as to obtain suicide regions 25 on the regions 19a and 20, and the residual metal is removed from the surfaces where it has not reacted (on top of the dielectric material) . In each active strip, the source region 20 and the corresponding suicide region 25 hence forms a source structure.
Then (Figures 7a and 7b) , the sacrificial spacers 22 are removed and an insulating layer 26 of dielectric material, for example USG, PSG, TEOS or a multilayer of low-conformality materials is deposited by CVD, the thickness whereof, for example between 300 nm and 700 nm, depends upon the planar technology and is chosen so as to fill the windows 15 but as to have, on the bottom of the contact cells 18, a thickness smaller than the portions on top of the gate electrodes 14 (typically, from one third to one half of the thickness on top of the gate electrodes 14) .
After densification of the dielectric material of the insulating layer 26, a photomasking is provided for opening pad contacts, in a per se known manner and hence not shown. This masking does not provide any covering with photoresist in the active area, but acts only on the edge terminations and on the bonding pad. Next (Figures 8a and 8b) , the insulating layer 26 is etched unidirectionally (dry etch) , with end-point on the suicide 25. In particular, given the different geometries of the windows 15a and of the contact cells 18, the insulating layer 26 is not removed from the windows 15a but is removed within the contact cells 18 (except for the vertical surface, where it forms spacers 26) . The insulating layer 26 is moreover removed to a large extent also on the horizontal surfaces of the gate electrodes 14.
Next, the contacts are provided (Figures 9a, 9b) . In particular, a barrier layer 27 (metallurgical barrier to contact formed by a Ti/TiN multilayer or the like) is deposited, and a metal layer 28 formed by an aluminium alloy is deposited on the front. The metal layer 28 and the barrier layer 27 thus together form a source metallization 29, which comprises first portions extending on top of the insulating layer 26 and second portions extending within the contact cells 18. In practice, on top of each active strip, the second portions of the metal layer 28 are in direct electrical contact with the source structures 20, 25 and with the body surfacing portions 19 only at the contact cells 18 (where there is thus a vertical current flow) . Instead, the first portions of the metal layer 28 on top of the windows 15a are in indirect electrical contact with the underlying source structures 20, 25, and precisely through the second portions of the metal layer (within the contact cells 18) and the suicide layers 25, with passage of current in a horizontal direction, along the suicide layers 25b.
The usual final operations then follow, with possible deposition and photolithographic definition of a final passivation layer, and the preparation and metallization of the back of the wafer (drain), in a per se known manner.
In some applications, the size of the contact cells 18 is such as not to enable formation of portions of the insulating layer 16 with reduced thickness on the bottom of the cells. In this case, opening of the source contacts can be obtained with a phototechnique . Consequently, it is no longer necessary for the gate electrodes 14 to be protected by the first insulating layer 16, and this may be absent. Figures 10a-18a, 10b-18b refer to this situation, and will be described hereinafter only as regards the steps whereby they differ from Figures 2- 9.
In detail, the initial steps are similar to those of Figures 2a-5a and 2b-5b, except for the absence of the first dielectric layer 16, as may be noted from Figures 10a-13a and 10b-13b. Instead, when the thermal treatment for causing reaction of the deposited layer of metal material with the silicon is carried out, suicide regions 25a are formed on top of the gate electrodes 14, in addition to suicide regions 25b on the regions 19a and 2Oe (Figures 14a, 14b) .
Furthermore, when the insulating layer 26 is deposited, given the geometry of the contact cells 18, this has the same thickness on the gate electrodes 14 and within the contact cells 18, as may be seen from Figures 15a, 15b. Consequently, the opening of the source contacts requires an appropriate phototechnique and thus the formation of a contact mask 30
(Figures 16a, 16b) , which coats the entire surface of the wafer 10, except for windows 31 within the contact cells 18 and, in a way not shown, except for contact windows on the gate pad designed for bonding in the step of assembly of the device. Windows (not shown) can moreover be provided for possible regions on the edge termination again designed for perimetral contact between the metallization and the gate electrode. Then the insulating layer 16 is etched within the windows 31 as well as on the edge termination and on the bonding pad, with end-point on the suicide regions 25b.
The process terminates with the steps already described previously. In particular, Figures 17a, 17b show the structure after forming the source metallization 29.
According to another embodiment (not shown) , the process follows the steps illustrated in Figures 10a-17a, 10b-17b, with the difference that the insulating layer 16 is deposited on top of the gate electrodes 14 and thus no suicide regions
25a are formed on top of the gate electrodes 14. Opening of the contacts is, however, performed as shown in Figures 15a- 17a and 15b-17b.
According to a different embodiment, illustrated with reference to Figures 18a-21a and 18b-21b, after one- directional (dry) etching of the double dielectric material layer 21, 22 and prior to depositing the metal material layer designed to form the suicide regions 25a, 25b, a dry etch of the exposed silicon is performed to form soft trenches. In this case, after the structure of Figures 5a, 5b is obtained and after formation of an appropriate mask that protects, among, i.a., the gate electrodes, a dry etch is performed for a fixed time, thereby forming recesses 35 in the epitaxial layer 12, which extend as far as the body regions 19 (see Figures 18a, 18b) .
Then, analogously to Figures 6a, 6b, the suicide regions 25 are formed (Figures 19a, 19b) . Here the suicide regions 25 cover the bottom of the recesses 35, where they contact the body regions 19, and the side walls of the recesses 35, where they contact the source region 20. Next, the sacrificial spacers 22 are removed, and an insulating layer 26 is deposited by CVD and then densified (Figures 20a, 20b) . Then, the insulating layer 26 is etched unidirectionally, and (Figures 21a, 21b) the source metallization 29 is deposited (formed also here by the barrier layer 27 and by the front- metal layer 28) . Then the final steps already described above follow.
Also here, the contact between the source metallization 29, the body regions 19 and the source regions 20 occurs only at the contact cells 20.
According to a different embodiment (not shown) , it is possible to proceed as described with reference to Figures 10a-13a and 10b-13 (hence, without using the first dielectric layer 16) and proceed as described with reference to Figures 18a-21a, 18b-21b.
The manufacturing process described thus enables a reduction in the dimensions of the device and has a high yield. Therefore the device thus obtained presents a reduced cost and high performance, in addition to affording excellent insulation characteristics.
Finally, it is clear that modifications and variations can be made to the process and to the device described herein, without departing from the scope of the present invention.
The shape of the contact cells 18 can vary with respect to the one shown, for example, it may be square, rectangular, polygonal, or even circular or oval. The dimensions of the contact cells 18 are moreover chosen on the basis of the specific characteristics of the process and of the materials used, provided that they are such as to guarantee a sufficient removal of the insulating layer 26 from the contact cells.
It is moreover highlighted that Figure 1 shows only one of the numerous possibilities of layout. In particular, the elongated portions or windows 15a of the openings 15 may even have a variable width, if necessary, but in any case preferably close to the lithographic minimum one, in order to be able to exploit the dimensional advantages referred to.
With the second embodiment, the source mask can be modified so as to eliminate the protective portions at the contact cells 18, except for at the short terminations of the active strips, where in any case protective portions must be present to prevent the source implantation and hence prevent formation of the channel regions 19b.

Claims

C L A I M S
1. A MOSFET device, comprising:
- a semiconductor layer (12) having a first conductivity type; - an insulated-gate structure (13, 14, 16, 21, 25a) formed on top of said semiconductor layer (12) and comprising at least two gate electrodes (14) of semiconductor material, extending at a distance from one another and delimiting between them a strip-shaped opening (15) ; - a body region (19) , formed within said semiconductor layer (12) and having a strip shape and a second conductivity type, said body region (19) extending underneath said opening (15) and partially underneath said gate electrodes (14);
- a source structure (20, 25; 25b) including at least one conductive region (20) of semiconductor material having said first conductivity type and formed within said body region (19); and
- a source-contact metal region (29) , extending at least partially in said opening (15) and in electrical contact with said body region (19) and said source structure (20, 25; 25b) ; characterized in that said opening (15) comprises elongated windows (15a) and contact cells (18) extending between pairs of consecutive elongated windows and in that said elongated windows (15a) are filled with dielectric spacer material (26) , and said metal contact structure (29) has first portions extending above said opening (15) at said elongated windows (15a) and second portions extending within said opening at said contact cells (18) and in direct electrical contact with said source structure (20, 25; 25b) .
2. The MOSFET device of claim 1, wherein said elongated windows (15a) have a first width (d) and said contact cells
(18) have a second maximum width (L) greater than said first width.
3. The MOSFET device of claim 2, wherein said contact cells (18) have a polygonal shape.
4. The MOSFET device of any of claims 1-3, wherein said first portions of said metal contact structure (29) are electrically connected to said source structure (20, 25; 25b) through said second portions .
5. The MOSFET device of any of claims 1-4, wherein said semiconductor layer (12) has a surface (12a) and said body region (19) has surface portions (19a) facing said surface and surrounded by said conductive region (20) , and wherein said source structure (20, 25; 25b) comprises a metal-silicide region (25; 25b) extending along said opening (15) and in direct electrical contact with said conductive region (20) and said surface portions (19b) of said body region.
6. The MOSFET device of claim 5, wherein said surface portions (19b) of said body region (19) extend at said contact cells (18) .
7. The MOSFET device of claim 5, wherein said surface (12a) of said semiconductor layer (12) has a recess (35) passing through said conductive region (20) and said surface portions (19b) of said body region (19) extend along said opening (15) underneath said recess (35) .
8. The MOSFET device of claim 7, wherein said insulated-gate structure (13, 14, 16, 21, 25a) comprises at least two lateral-insulation portions (21) of dielectric material extending throughout the length of said gate electrodes (14) within said opening (15) .
9. A process for manufacturing of a MOSFET device, comprising the steps of:
- forming a semiconductor layer (12) having a first conductivity type;
- forming an insulated-gate structure (13, 14, 21, 25; 25a) on top of said semiconductor layer (12) and comprising at least two gate electrodes (14) of semiconductor material, extending at a distance from one another and delimiting between them an opening (15) having a strip shape;
- forming, within said semiconductor layer (12), underneath said opening (15) and partially underneath said gate electrodes (14), a body region (19) having a strip shape and a second conductivity type;
- forming, within said body region (19) , at least one source structure (20, 25; 25b) including a conductive region (20) of semiconductor material having said first conductivity type; and
- forming a source-contact metal region (29) , extending at least partially in said opening (15) and in electrical contact with said body region (19) and said source structure (20, 25; 25); characterized in that said step of forming an opening (15) comprises forming elongated windows (15a) and contact cells (18) and comprising, prior to said step of forming a source- contact metal region (29) , filling said elongated windows (15a) with dielectric spacer material (26) so that said metal contact structure (29) has first portions extending above said opening (15) at said elongated windows (15a) and second portions extending within said opening (15) at said contact cells (18) and in direct electrical contact with said source structure (20, 25; 25b) .
10. The process of claim 9, wherein said elongated windows (15a) have a first width (d) and said contact cells (18) have a second maximum width (L) greater than said first width.
11. The process of claim 8 or 9, wherein said step of forming a body region (19) comprises forming surface portions (19a) facing a surface (12a) of said semiconductor layer (12) and surrounded by said conductive region (20) and said step of forming a source structure (20, 25; 25b) comprises forming a metal-silicide region (25; 25b) extending along said opening
(15) and in direct electrical contact with said conductive region (20) and said surface portions (19a) of said body region (19) .
12. The process of claim 11, wherein said step of forming a source structure (20, 25; 25b) comprises selectively covering said body region (19) with a mask (3) at said contact cells
(18) , introducing ionic dopant species of said first conductivity type within said body region (19) except at said mask (3) so as to delimit said surface portions (19a) of said body region (19) .
13. The process of claim 11, wherein said step of forming a source structure (20, 25; 25b) comprises introducing ionic dopant species of said first conductivity type within said body region (19) to form said conductive region (20) , the process moreover comprising, prior to forming a metal-silicide region (25) , removing a portion of said semiconductor layer
(12) in said opening (15), forming a recess (35) extending as far as said body region (19) , and wherein said step of forming a metal-silicide region (25) comprises providing said metal- silicide region within said recess (35) and in electrical contact laterally with said conductive region (20) and, at the bottom, with said body region (19) .
14. The process of any one of claims 11-13, comprising, prior to forming a metal-silicide region (25; 25b) , forming lateral- insulation regions (21, 22) of dielectric material along said gate electrodes (14) within said opening (15) .
15. The process of claim 11, wherein said step of forming lateral-insulation regions (21, 22) comprises providing an insulation layer (21) covering said gate electrodes (14) and coating said opening (15) , forming sacrificial spacer regions (22) on lateral surfaces of said opening (15), removing exposed portions of said insulation layer (21) and removing said sacrificial spacer regions (22).
16. The process of any of claims 9-14, wherein said step of filling comprises depositing insulating layer (26) of low- conformality dielectric material, and etching said insulating layer (26) unidirectionally .
17. The process of any of claims 9-14, wherein said step of filling comprises depositing an insulating layer (26) of low- conformality dielectric material, and etching said insulating layer (26) in a masked way (30) .
PCT/EP2006/062394 2005-05-19 2006-05-17 Mos power device with high integration density and manufacturing process thereof WO2006122957A2 (en)

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