WO2006120470A3 - Processor and interface - Google Patents

Processor and interface Download PDF

Info

Publication number
WO2006120470A3
WO2006120470A3 PCT/GB2006/001756 GB2006001756W WO2006120470A3 WO 2006120470 A3 WO2006120470 A3 WO 2006120470A3 GB 2006001756 W GB2006001756 W GB 2006001756W WO 2006120470 A3 WO2006120470 A3 WO 2006120470A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
execution
instruction set
memory
master computer
Prior art date
Application number
PCT/GB2006/001756
Other languages
French (fr)
Other versions
WO2006120470A2 (en
Inventor
Alistair Guy Morfey
Karl Leighton Swepson
Neil Edward Johnson
Martin David Cooper
Alan Mycroft
Original Assignee
Cambridge Consultants
Alistair Guy Morfey
Karl Leighton Swepson
Neil Edward Johnson
Martin David Cooper
Alan Mycroft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0509738.1A external-priority patent/GB0509738D0/en
Application filed by Cambridge Consultants, Alistair Guy Morfey, Karl Leighton Swepson, Neil Edward Johnson, Martin David Cooper, Alan Mycroft filed Critical Cambridge Consultants
Priority to EP06727101A priority Critical patent/EP1891515A2/en
Publication of WO2006120470A2 publication Critical patent/WO2006120470A2/en
Publication of WO2006120470A3 publication Critical patent/WO2006120470A3/en
Priority to US11/983,754 priority patent/US8683163B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4434—Reducing the memory space required by the program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

The present invention relates to a processor which comprises an instruction set for execution on the processor, a processor architecture and a memory, wherein the instruction set and the processor architecture comprise characteristics which have been specifically tailored to ensure that the code density compiled for execution at least in part on the processor memory is relatively high. The invention -alsorelates-tο-a compiler.-The-invention-extends to a system comprising a master computer; one or more control pods; and one or more integrated circuits, each comprising one or more processors; wherein the master computer is operable to interact with any of said processors via said one or more control pods.
PCT/GB2006/001756 2005-05-12 2006-05-12 Processor and interface WO2006120470A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06727101A EP1891515A2 (en) 2005-05-12 2006-05-12 Processor and interface
US11/983,754 US8683163B2 (en) 2005-05-12 2007-11-08 Processor and interface

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0509738.1 2005-05-12
GBGB0509738.1A GB0509738D0 (en) 2005-05-12 2005-05-12 Processor and interface
GB0524772.1 2005-12-05
GB0524772A GB2427722A (en) 2005-05-12 2005-12-05 Computer system, processor and interface to other processors.

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/983,754 Continuation US8683163B2 (en) 2005-05-12 2007-11-08 Processor and interface

Publications (2)

Publication Number Publication Date
WO2006120470A2 WO2006120470A2 (en) 2006-11-16
WO2006120470A3 true WO2006120470A3 (en) 2007-09-07

Family

ID=36607605

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2006/001756 WO2006120470A2 (en) 2005-05-12 2006-05-12 Processor and interface

Country Status (2)

Country Link
EP (1) EP1891515A2 (en)
WO (1) WO2006120470A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9684294B2 (en) * 2015-01-09 2017-06-20 Tyco Safety Products Canada Ltd. Multi-core processor for optimized power consumption in a security and home automation system
CN108388446A (en) * 2018-02-05 2018-08-10 上海寒武纪信息科技有限公司 Computing module and method
GB201810785D0 (en) 2018-06-29 2018-08-15 Nordic Semiconductor Asa Asynchronous communication

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
AMD: "AMD64 Techology, AMD64 Architecture, Programmer's Manual, Vol. 3, Revision 3.09; Pages xvii, 17, 49, 183, 222, 232, 252, 261", September 2003, AMD, XP002424885 *
JERRY ASCIERTO: "AMD provides a glimpse of Hammer MPU", 16 October 2001, UNITED BUSINESS MEDIA, XP002424906 *
MCGEADY S ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "A programmer's view of the 80960 architecture", INTELLECTUAL LEVERAGE. SAN FRANCISCO, FEB. 27 - MAR. 3, 1989, COMPUTER SOCIETY INTERNATIONAL CONFERENCE (COMPCON), WASHINGTON, IEEE COMP. SOC. PRESS, US, vol. CONF. 34, 27 February 1989 (1989-02-27), pages 4 - 9, XP010014713, ISBN: 0-8186-1909-0 *

Also Published As

Publication number Publication date
EP1891515A2 (en) 2008-02-27
WO2006120470A2 (en) 2006-11-16

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