WO2006113754A2 - Underfill dispense at substrate aperture - Google Patents

Underfill dispense at substrate aperture Download PDF

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Publication number
WO2006113754A2
WO2006113754A2 PCT/US2006/014631 US2006014631W WO2006113754A2 WO 2006113754 A2 WO2006113754 A2 WO 2006113754A2 US 2006014631 W US2006014631 W US 2006014631W WO 2006113754 A2 WO2006113754 A2 WO 2006113754A2
Authority
WO
WIPO (PCT)
Prior art keywords
underfill material
gap
substrate
aperture
underfill
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/014631
Other languages
French (fr)
Other versions
WO2006113754A3 (en
Inventor
Charles Anthony Odegard
Marvin Wayne Cowens
Leon Stiborek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of WO2006113754A2 publication Critical patent/WO2006113754A2/en
Anticipated expiration legal-status Critical
Publication of WO2006113754A3 publication Critical patent/WO2006113754A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors

Definitions

  • the invention relates to the manufacture of integrated circuit assemblies. More particularly, the invention relates to the dispensing of underfill material between an IC device and a substrate.
  • solder nodules or "bumps” having spherical, near-spherical, or other shapes are frequently used to join an IC to a substrate, such as a printed circuit board (PCB).
  • PCB printed circuit board
  • the IC and substrate have corresponding metallized locations generally known as contact points, or bond pads.
  • the components are aligned, typically using sophisticated optical aligning tools. Solder bumps positioned at the prepared metallized locations are heated, and solder bonds are formed between the contact points upon cooling.
  • the IC-to-substrate assembly solder joints are typically "blind,” that is, they are not readily accessible for visual inspection. Often the gap between the IC and substrate is filled with a dielectric underfill material. The IC assembly is then encapsulated in a protective plastic package in order to provide increased strength and protection.
  • underfill dispensing techniques include "I" pass dispensing as shown in the cut-away view of an IC assembly 10 of FIG. 1 (prior art). The IC assembly 10 is shown during the dispensing of underfill material 12 in a view looking down on the gap between a die (cut away) and a substrate 16.
  • a dispensing needle makes one or more passes along one edge 18 of the gap between the die and substrate and the underfill material 12 flows into the gap by capillary action or by the application of vacuum or suction force.
  • Another common underfill dispensing technique is L-dispensing, as shown in FIG. 2, in which underfill material 12 is dispensed along two adjacent edges 18 of the gap.
  • the underfill fluid 12 may be pulled into the gap by capillary action or may be assisted by the use of external force.
  • U dispensing patterns in a similar manner, and also to attempt to supplement I-dispensed, L-dispensed, or U-dispensed underfill fluid flow using external dams at one or more edges of the gap.
  • IC assemblies are provided with underfill using methods designed to decrease the propensity for void formation.
  • a method for dispensing underfill material into the gap between a die and a substrate of an IC assembly includes steps for providing an aperture in the substrate for receiving underfill material into the gap. Underfill material is dispensed into the gap through the aperture, filling the gap with underfill material with a reduction in the propensity for the formation of voids.
  • a method for dispensing underfill material through a substrate aperture to fill the gap between a substrate and die uses capillary action.
  • a method for dispensing underfill material through a substrate aperture to fill the gap between a substrate and die uses the application of force to the underfill material.
  • a method for dispensing underfill material through a substrate aperture to fill the gap between a substrate and die uses the application of force with a vacuum.
  • a method for dispensing underfill material through a substrate aperture to fill the gap between a substrate and die uses the application of positive pressure.
  • a method for dispensing underfill material into the gap between a die and substrate of an IC assembly includes steps for providing an aperture in the substrate for receiving underfill material into the gap wherein the aperture is positioned in the approximate geographic center of the substrate and material is dispensed into the gap through the aperture.
  • a method for dispensing underfill material into the gap between a die and substrate of an IC assembly includes steps for providing more than one aperture in the substrate for receiving underfill material into the gap.
  • the underfill material is dispensed into the gap through the apertures.
  • FIG. 1 (prior art) is a cut-away top view representing an example of prior art I-dispensed underfill
  • FIG. 2 (prior art) is a cut-away top view representing an example of prior art L-dispensed underfill
  • FIGS. 3 A — 3B are cut-away top views of example steps according to an example embodiment of the invention. DETAILED DESCRIPTION
  • FIGS. 3A and 3B depict cut-away top views looking down on the gap between a die and substrate 16 in an IC assembly 30 using the invention.
  • An aperture 32 is provided in the substrate 16.
  • the aperture 32 provides communication with the gap to facilitate the dispensing of underfill material 12 into the gap from outside of substrate 16.
  • the dispensing of underflow material 12 is represented by arrows representing a generally radial flow of underfill material 12 into the gap from the aperture 32.
  • the flow of underfill material 12 from the aperture 32 provides a relatively short flow path to the edges 18 of the assembly 30 for more rapid coverage.
  • the outward- flowing underfill material 12 forces air ahead of it, out from the gap, thereby tending to decrease the occurrence of capture voids in the completed assembly 30. Additionally, the capture of impurities such as flux or other residue is made less likely due to the outward flow pattern. It should also be appreciated that the use of the invention in applications having higher bump density 20 at one or more edges 18 of the device, or the entire perimeter, provides additional advantages in distributing the underfill material 12 from a relatively slow-flowing area at the interior 22 of the device to the faster- flowing edges 18. Those reasonably skilled in the art to which the invention relates will recognize that various alternatives exist for the adaptation of the methods of the invention to specific applications.
  • the dispensed underfill material 12 may be flowed using capillary action or may be assisted using force applied to the underfill material 12 such as by a vacuum or by pressurized dispensing means.
  • the aperture 32 shown in the examples of FIGS. 3 A and 3B is positioned in the approximate geographic center of the substrate 16, the use of other positions and/or multiple apertures is possible, without departure form the scope of the invention.

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

An IC assembly (10) having a die mounted on a substrate (16) with a gap therebetween, receives underfill material (12) through an aperture (32) provided in the substrate to fill the gap. This provides a favorable flow rate and improved underfilling, with less voiding. Embodiments of the invention are disclosed in which capillary action, a vacuum, or positive pressure, are used to assist the flow of underfill material.

Description

UNDERFILL DISPENSE AT SUBSTRATE APERTURE The invention relates to the manufacture of integrated circuit assemblies. More particularly, the invention relates to the dispensing of underfill material between an IC device and a substrate. BACKGROUND
Semiconductor devices are subject to many competing design goals. Since it is very often desirable to minimize the size of electronic apparatus, surface mount semiconductor devices are often used due to their small footprint. Solder nodules or "bumps" having spherical, near-spherical, or other shapes are frequently used to join an IC to a substrate, such as a printed circuit board (PCB).
The IC and substrate have corresponding metallized locations generally known as contact points, or bond pads. The components are aligned, typically using sophisticated optical aligning tools. Solder bumps positioned at the prepared metallized locations are heated, and solder bonds are formed between the contact points upon cooling. When completed, the IC-to-substrate assembly solder joints are typically "blind," that is, they are not readily accessible for visual inspection. Often the gap between the IC and substrate is filled with a dielectric underfill material. The IC assembly is then encapsulated in a protective plastic package in order to provide increased strength and protection.
Among the problems encountered with packaged IC assemblies, some of the most common and debilitating are the separation of layers, and open or short circuits caused by separation of materials, or the ingress of moisture between separated materials. For these reasons, void-free underfill processes and materials are highly desirable. Various combinations of underfill materials, dispensing patterns, and flow techniques have been used in efforts to reduce the formation of voids and reduce underfill process time. Common underfill dispensing techniques include "I" pass dispensing as shown in the cut-away view of an IC assembly 10 of FIG. 1 (prior art). The IC assembly 10 is shown during the dispensing of underfill material 12 in a view looking down on the gap between a die (cut away) and a substrate 16. A dispensing needle (not shown) makes one or more passes along one edge 18 of the gap between the die and substrate and the underfill material 12 flows into the gap by capillary action or by the application of vacuum or suction force. Another common underfill dispensing technique is L-dispensing, as shown in FIG. 2, in which underfill material 12 is dispensed along two adjacent edges 18 of the gap. As with I-dispensing, the underfill fluid 12 may be pulled into the gap by capillary action or may be assisted by the use of external force. It is also known to use "U" dispensing patterns in a similar manner, and also to attempt to supplement I-dispensed, L-dispensed, or U-dispensed underfill fluid flow using external dams at one or more edges of the gap.
Problems persist in the efforts to achieve void-free underfills while optimizing throughput. Leaving aside the properties of the underfill fluid itself, the geometry of the die, substrate, and solder bumps in an assembly also have an effect on underfill fluid flow rate and coverage. In general, smaller vertical gaps increase flow rate and larger horizontal distances tend to reduce flow rate. The flow rate is also increased as the density of solder bumps increases, due to the stronger capillary action provided by the increased surface area. Fillets are often formed at the edges of the die-substrate gap during the underfill process. Dispensing a relatively large volume of underfill material can enhance flow, assure an adequate supply of fluid, and reduce voids, but excessive fillet size can increase stress on the edges of the completed package. Generally, stress increases with distance from the center of the die, and the larger the die, the greater the stress. Efforts to increase flow rate by force such as pumps and vacuums are sometimes successful. However, in addition to increasing flow rate, prevention of void formation is a challenge. Voids form when air becomes entrapped by the flowing underfill material. Flow rate, flow pattern, temperature, drag, and fluid viscosity are all intertwined in the completion of the underfill process and in the potential formation of voids. Many instances of void formation can be attributed to the differences in flow rate in different areas of an assembly. For example, in assemblies such as those shown in FIGS. 1 and 2 (prior art) having relatively high solder bump 20 density at the perimeter, faster flow of underfill material 12 at the perimeter can result in the entrapment of air pockets in the interior 22 of the device 10.
Due to these and other problems, improved methods for the manufacture of integrated circuit assemblies with reduced potential for underfill voids and increased throughput would be useful and advantageous in the art. SUMMARY
In carrying out the principles of the present invention, in accordance with preferred embodiments thereof, IC assemblies are provided with underfill using methods designed to decrease the propensity for void formation. According to one aspect of the invention, a method for dispensing underfill material into the gap between a die and a substrate of an IC assembly includes steps for providing an aperture in the substrate for receiving underfill material into the gap. Underfill material is dispensed into the gap through the aperture, filling the gap with underfill material with a reduction in the propensity for the formation of voids. According to another aspect of the invention, a method for dispensing underfill material through a substrate aperture to fill the gap between a substrate and die uses capillary action.
According to yet another aspect of the invention, a method for dispensing underfill material through a substrate aperture to fill the gap between a substrate and die uses the application of force to the underfill material.
According to still another aspect of the invention, a method for dispensing underfill material through a substrate aperture to fill the gap between a substrate and die uses the application of force with a vacuum.
According to another aspect of the invention, a method for dispensing underfill material through a substrate aperture to fill the gap between a substrate and die uses the application of positive pressure.
According to one aspect of the invention, a method for dispensing underfill material into the gap between a die and substrate of an IC assembly includes steps for providing an aperture in the substrate for receiving underfill material into the gap wherein the aperture is positioned in the approximate geographic center of the substrate and material is dispensed into the gap through the aperture.
According to yet another aspect of the invention, a method for dispensing underfill material into the gap between a die and substrate of an IC assembly includes steps for providing more than one aperture in the substrate for receiving underfill material into the gap. The underfill material is dispensed into the gap through the apertures. The invention has advantages including but not limited to improved underfill material dispensing and IC assemblies with improved strength and resistance to stress. These and other features, advantages, and benefits of the present invention can be understood by one of ordinary skill in the art from the detailed description of representative embodiments and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 (prior art) is a cut-away top view representing an example of prior art I-dispensed underfill;
FIG. 2 (prior art) is a cut-away top view representing an example of prior art L-dispensed underfill; and
FIGS. 3 A — 3B are cut-away top views of example steps according to an example embodiment of the invention. DETAILED DESCRIPTION
In general the invention provides methods for underfill dispensing in the manufacture of semiconductor device assemblies; and semiconductor assemblies manufactured using the same. FIGS. 3A and 3B depict cut-away top views looking down on the gap between a die and substrate 16 in an IC assembly 30 using the invention. An aperture 32 is provided in the substrate 16. The aperture 32 provides communication with the gap to facilitate the dispensing of underfill material 12 into the gap from outside of substrate 16. hi FIG. 3B, the dispensing of underflow material 12 is represented by arrows representing a generally radial flow of underfill material 12 into the gap from the aperture 32. The flow of underfill material 12 from the aperture 32 provides a relatively short flow path to the edges 18 of the assembly 30 for more rapid coverage. Also, the outward- flowing underfill material 12 forces air ahead of it, out from the gap, thereby tending to decrease the occurrence of capture voids in the completed assembly 30. Additionally, the capture of impurities such as flux or other residue is made less likely due to the outward flow pattern. It should also be appreciated that the use of the invention in applications having higher bump density 20 at one or more edges 18 of the device, or the entire perimeter, provides additional advantages in distributing the underfill material 12 from a relatively slow-flowing area at the interior 22 of the device to the faster- flowing edges 18. Those reasonably skilled in the art to which the invention relates will recognize that various alternatives exist for the adaptation of the methods of the invention to specific applications. For example, the dispensed underfill material 12 may be flowed using capillary action or may be assisted using force applied to the underfill material 12 such as by a vacuum or by pressurized dispensing means. Although the aperture 32 shown in the examples of FIGS. 3 A and 3B is positioned in the approximate geographic center of the substrate 16, the use of other positions and/or multiple apertures is possible, without departure form the scope of the invention.
The methods and apparatus of the invention provide advantages including but not limited to promoting electrical and mechanical bonding in IC assemblies. It will be appreciated by those skilled in the art that the invention may be used with various types of semiconductor device packages. Various modifications and combinations of the illustrative embodiments as well as other advantages and embodiments of the invention will be apparent to persons skilled in the art, upon reference to the drawings, description, and claims.

Claims

1. A method for dispensing underfill material in an IC assembly having a die mounted on a substrate with a gap therebetween, comprising the steps of: providing at least one aperture in the substrate for receiving underfill material into the gap; dispensing underfill material into the gap through the at least one aperture, thereby filling the gap with underfill material,
2. A method according to Claim 1 , wherein the step of filling the gap with dispensed underfill material further comprises using capillary action.
3. A method according to Claim 1, wherein the step of filling the gap with dispensed underfill material further comprises using the application of force to the underfill material.
4. A method according to Claim 3, wherein the step of using the application of force to the underfill material further comprises the use of a vacuum.
5. A method according to Claim 3, wherein the step of using the application of force to the underfill material further comprises the use of positive pressure.
6. A method according to Claim 1, wherein the step of providing the at least one aperture in the substrate further comprises the step of positioning an aperture in the approximate geographic center of the substrate.
7. An IC assembly having a die mounted on a substrate with a gap; at least one aperture provided in the substrate for receiving underfill material into the gap; underfill material received into the gap through the at least one aperture.
PCT/US2006/014631 2005-04-19 2006-04-19 Underfill dispense at substrate aperture Ceased WO2006113754A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/109,259 US20060234427A1 (en) 2005-04-19 2005-04-19 Underfill dispense at substrate aperture
US11/109,259 2005-04-19

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WO2006113754A2 true WO2006113754A2 (en) 2006-10-26
WO2006113754A3 WO2006113754A3 (en) 2007-11-08

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WO (1) WO2006113754A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8759961B2 (en) 2012-07-16 2014-06-24 International Business Machines Corporation Underfill material dispensing for stacked semiconductor chips
US9917068B2 (en) * 2014-03-14 2018-03-13 Taiwan Semiconductor Manufacturing Company Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5203076A (en) * 1991-12-23 1993-04-20 Motorola, Inc. Vacuum infiltration of underfill material for flip-chip devices
US5766982A (en) * 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
CA2198305A1 (en) * 1996-05-01 1997-11-02 Yinon Degani Integrated circuit bonding method and apparatus
US6140144A (en) * 1996-08-08 2000-10-31 Integrated Sensing Systems, Inc. Method for packaging microsensors
US6734540B2 (en) * 2000-10-11 2004-05-11 Altera Corporation Semiconductor package with stress inhibiting intermediate mounting substrate
US20020173074A1 (en) * 2001-05-16 2002-11-21 Walsin Advanced Electronics Ltd Method for underfilling bonding gap between flip-chip and circuit substrate
SG122743A1 (en) * 2001-08-21 2006-06-29 Micron Technology Inc Microelectronic devices and methods of manufacture
US20030113952A1 (en) * 2001-12-19 2003-06-19 Mahesh Sambasivam Underfill materials dispensed in a flip chip package by way of a through hole
US6979600B2 (en) * 2004-01-06 2005-12-27 Intel Corporation Apparatus and methods for an underfilled integrated circuit package
US20060099736A1 (en) * 2004-11-09 2006-05-11 Nagar Mohan R Flip chip underfilling

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Publication number Publication date
WO2006113754A3 (en) 2007-11-08
US20080085573A1 (en) 2008-04-10
US20060234427A1 (en) 2006-10-19

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