WO2006103395A1 - Preparing instruction groups in a processor having multiple issue ports - Google Patents

Preparing instruction groups in a processor having multiple issue ports Download PDF

Info

Publication number
WO2006103395A1
WO2006103395A1 PCT/GB2006/001000 GB2006001000W WO2006103395A1 WO 2006103395 A1 WO2006103395 A1 WO 2006103395A1 GB 2006001000 W GB2006001000 W GB 2006001000W WO 2006103395 A1 WO2006103395 A1 WO 2006103395A1
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
pool
instructions
pools
target
Prior art date
Application number
PCT/GB2006/001000
Other languages
English (en)
French (fr)
Inventor
William Owen Lovett
David Haikney
Matthew Evans
Original Assignee
Transitive Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0506469A external-priority patent/GB2424727B/en
Application filed by Transitive Limited filed Critical Transitive Limited
Priority to JP2008503571A priority Critical patent/JP5102758B2/ja
Priority to EP06710120A priority patent/EP1866759B1/de
Publication of WO2006103395A1 publication Critical patent/WO2006103395A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/52—Binary to binary
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
PCT/GB2006/001000 2005-03-30 2006-03-17 Preparing instruction groups in a processor having multiple issue ports WO2006103395A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008503571A JP5102758B2 (ja) 2005-03-30 2006-03-17 複数の発行ポートを有するプロセッサにおける命令グループを形成する方法、並びに、その装置及びコンピュータ・プログラム
EP06710120A EP1866759B1 (de) 2005-03-30 2006-03-17 Erstellung von anweisungsgruppen in einem prozessor mit mehreren ausgabeports

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0506469.6 2005-03-30
GB0506469A GB2424727B (en) 2005-03-30 2005-03-30 Preparing instruction groups for a processor having a multiple issue ports
US11/139,232 2005-05-27
US11/139,232 US7934203B2 (en) 2005-03-30 2005-05-27 Preparing instruction groups for a processor having multiple issue ports

Publications (1)

Publication Number Publication Date
WO2006103395A1 true WO2006103395A1 (en) 2006-10-05

Family

ID=36337508

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2006/001000 WO2006103395A1 (en) 2005-03-30 2006-03-17 Preparing instruction groups in a processor having multiple issue ports

Country Status (2)

Country Link
EP (1) EP1866759B1 (de)
WO (1) WO2006103395A1 (de)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008129315A1 (en) 2007-04-19 2008-10-30 Transitive Limited Apparatus and method for handling exception signals in a computing system
WO2010012657A1 (en) 2008-07-29 2010-02-04 International Business Machines Corporation Apparatus and method for handling page protection faults in a computing system
US7895407B2 (en) 2006-11-22 2011-02-22 International Business Machines Corporation Memory consistency protection in a multiprocessor computing system
US8001535B2 (en) 2006-10-02 2011-08-16 International Business Machines Corporation Computer system and method of adapting a computer system to support a register window architecture
US8458674B2 (en) 2006-06-20 2013-06-04 International Business Machines Corporation Method and apparatus for handling exceptions during binding to native code
EP3270286A1 (de) * 2016-07-13 2018-01-17 Bayerische Motoren Werke Aktiengesellschaft Fahrzeugsteuerlogik unter berücksichtigung von zeitmarken

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040054517A1 (en) * 2002-09-17 2004-03-18 International Business Machines Corporation Method and system for multiprocessor emulation on a multiprocessor host system
EP1457881A1 (de) 2003-03-13 2004-09-15 Northrop Grumman Corporation Ein rekonfigurierbarer binärer Übersetzer
US6799262B1 (en) 2000-09-28 2004-09-28 International Business Machines Corporation Apparatus and method for creating instruction groups for explicity parallel architectures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6799262B1 (en) 2000-09-28 2004-09-28 International Business Machines Corporation Apparatus and method for creating instruction groups for explicity parallel architectures
US20040054517A1 (en) * 2002-09-17 2004-03-18 International Business Machines Corporation Method and system for multiprocessor emulation on a multiprocessor host system
EP1457881A1 (de) 2003-03-13 2004-09-15 Northrop Grumman Corporation Ein rekonfigurierbarer binärer Übersetzer

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BARAZ L ET AL: "IA-32 execution layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems", MICROARCHITECTURE, 2003. MICRO-36. PROCEEDINGS. 36TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON 3-5 DEC. 2003, PISCATAWAY, NJ, USA,IEEE, 3 December 2003 (2003-12-03), pages 191 - 201, XP010674593, ISBN: 0-7695-2043-X *
INTEL CORPORATION: "Intel Itanium® 2 Processor Reference Manual For Software Development and Optimization", 2004, INTEL CORPORATION, XP002382964 *
ZHENG C ET AL: "PA-RISC TO IA-64: TRANSPARENT EXECUTION, NO RECOMPILATION", COMPUTER, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 33, no. 3, March 2000 (2000-03-01), pages 47 - 52, XP001075149, ISSN: 0018-9162 *

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8458674B2 (en) 2006-06-20 2013-06-04 International Business Machines Corporation Method and apparatus for handling exceptions during binding to native code
US8001535B2 (en) 2006-10-02 2011-08-16 International Business Machines Corporation Computer system and method of adapting a computer system to support a register window architecture
US8381168B2 (en) 2006-10-02 2013-02-19 International Business Machines Corporation Computer system and method of adapting a computer system to support a register window architecture
TWI403898B (zh) * 2006-11-22 2013-08-01 Ibm 在多處理器計算系統中之記憶體一致性保護方法
US7895407B2 (en) 2006-11-22 2011-02-22 International Business Machines Corporation Memory consistency protection in a multiprocessor computing system
WO2008129315A1 (en) 2007-04-19 2008-10-30 Transitive Limited Apparatus and method for handling exception signals in a computing system
WO2010012657A1 (en) 2008-07-29 2010-02-04 International Business Machines Corporation Apparatus and method for handling page protection faults in a computing system
US8719541B2 (en) 2008-07-29 2014-05-06 International Business Machines Corporation Apparatus and method for handling page protection faults in a computing system
US9483419B2 (en) 2008-07-29 2016-11-01 International Business Machines Corporation Apparatus and method for handling page protection faults in a computing system
US10534727B2 (en) 2008-07-29 2020-01-14 International Business Machines Corporation Apparatus and method for handling page protection faults in a computing system
US11061833B2 (en) 2008-07-29 2021-07-13 International Business Machines Corporation Apparatus and method for handling page protection faults in a computing system
US11119949B2 (en) 2008-07-29 2021-09-14 International Business Machines Corporation Apparatus and method for handling page protection faults in a computing system
US11163702B2 (en) 2008-07-29 2021-11-02 International Business Machines Corporation Apparatus and method for handling page protection faults in a computing system
EP3270286A1 (de) * 2016-07-13 2018-01-17 Bayerische Motoren Werke Aktiengesellschaft Fahrzeugsteuerlogik unter berücksichtigung von zeitmarken

Also Published As

Publication number Publication date
EP1866759B1 (de) 2012-06-13
EP1866759A1 (de) 2007-12-19

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