WO2006099198A1

WO2006099198A1 - Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

Info

Publication number: WO2006099198A1
Application number: PCT/US2006/008707
Authority: WO
Inventors: Jack Kavalieros; Justin Brask; Mark Doczy; Matthew Metz; Suman Datta; Brian Doyle; Robert Chau; Everett Wang; Philippe Matagne; Lucian Shifren; Been Jin; Mark Stettler; Martin Giles
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2005-03-11
Filing date: 2006-03-08
Publication date: 2006-09-21
Anticipated expiration: 2007-09-11
Also published as: US20090075445A1; US7470972B2; TWI307127B; US20060205167A1; TW200644128A

Abstract

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Description

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

INTEGRATED CIRCUIT USING UNIAXIAL COMPRESSIVE

STRESS AND BIAXIAL COMPRESSIVE STRESS

5 Background

This invention relates generally to the fabrication of integrated circuits. To increase performance of NMOS and PMOS deep sub-micron transistors in CMOS technology, current state-of-the-art technology uses compressive stress in the channel of the PMOS transistors, and tensile stress in the case of NMOS transistors. This 0 is usually achieved by substrate induced strain which is a very expensive technology option and is also difficult to implement using a single substrate approach.

Brief Description of the Drawings

Figure 1 is an enlarged, cross-sectional view of an NMOS transistor at an early stage of manufacture; 5 Figure 2 is an enlarged, cross-sectional view of a PMOS transistor at an early stage of manufacture;

Figure 3 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in Figure 1 in accordance with one embodiment of the present invention;

Figure 4 is an enlarged, cross-sectional view at a stage subsequent to the stage O shown in Figure 2 in accordance with one embodiment of the present invention;

Figure 5 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in Figure 3 in accordance with one embodiment of the present invention;

Figure 6 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in Figure 4 in accordance with one embodiment of the present invention; 5 Figure 7 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in Figure 6 in accordance with one embodiment of the present invention;

Figure 8 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in Figure 7 in accordance with one embodiment of the present invention;

Figure 9 is an enlarged, cross-sectional view at a stage subsequent to the stage O shown in Figure 8 in accordance with one embodiment of the present invention;

Figure 10 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in Figure 9 in accordance with one embodiment of the present invention; and Figure 11 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in Figure 5 in accordance with one embodiment of the present invention.

Detailed Description

Referring to Figure 1, a silicon substrate 12 may be covered by a graded buffer layer 14. The buffer layer 14 may be formed of silicon germanium of the formula Sii_-xGe_x where x is from .05 to .3. In one embodiment, the buffer layer 14 may be epitaxially grown, while gradually increasing the concentration of germanium. Thus, the germanium concentration is highest at the top of the layer 14, lowest at the bottom, and linearly increases from bottom to top in one embodiment. Over the layer 14 may be deposited a constant concentration silicon germanium buffer layer 16. In one embodiment of the present invention, this layer 16 may have a thickness of from 2000 to 10,000 Angstroms. The layer 16 may have a constant germanium concentration substantially equal to that of the highest germanium level of the layer 14, in one embodiment. A tensile strained silicon layer 18 is formed thereover. Shallow trench isolations

20 may be provided as well. In one embodiment of the present invention, the structure 10b, shown in Figure 1, will be utilized to form both NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit technology.

The gradient of germanium in the graded buffer layer 14 can vary depending on the thickness and final germanium concentration. In some embodiments, the concentration of germanium in the graded layer 14 extends from about zero percent at the bottom to about 40 percent at the top. Other percentages may be utilized in different situations. The layer 14 functions to achieve a relaxed silicon germanium layer and to reduce dislocation formation due to mismatch in the lattice constraints between silicon and the silicon germanium. The constant germanium concentration silicon germanium buffer layer 16 further stabilizes the structure.

The tensile strained silicon layer 18 may be grown. The strained nature of the layer 18 is limited by the critical layer thickness associated with the concentration of germanium in the underlying buffer layer 16. At the same time, the PMOS structure 10a may be fabricated, as shown in Figure

2. The PMOS structure 10a may initially have the same components as the NMOS structure 10b. Thereafter, as shown in Figure 3, a hard mask 21 may be deposited over the tensile strained silicon layer 18 on the NMOS side 10b and PMOS side 10a.

Then, a hard mask etch and resist removal may be utilized to remove the tensile strained silicon 18 and the hard mask 21 on the PMOS transistor structure 10a as shown in Figure 4. The selective etch may use 5 to 8 percent NH₄OH with a pH between about 10.2 and 10.4 at a temperature between 20⁰C and 27⁰C in one embodiment. The resulting structure has the tensile strained silicon removed on the PMOS side 10a. The NMOS side 10b is still covered by the hard mask 21 (Figure 3).

The selective wet etch of the strained silicon layer 18 is such that nucleophillic binding energy of silicon is surpassed and an etch of the silicon layer 18 is effected. However, the nucleophillic binding energy may be only about 0.5 kJ/mol too little to solubilize the germanium to the corresponding aqueous species, so the layer 16 is preserved.

Then, a compressively strained silicon germanium layer 28 is deposited as shown in Figure 6 on the PMOS side 10a. The silicon germanium may be of the formula Si_1- _yGe_y, where y is greater than x. The higher concentration y means the layer 28 has a larger lattice than the underlying layers, resulting in compressive strain applied upwardly by the layers 14 and 16 to biaxially compress the layer 28.

The layer 28 may be selectively grown on the PMOS side 10a only and not on the NMOS side 10b as indicated in Figure 5 because only the NMOS side 10b was covered by the hard mask 21 at the time the layer 28 was deposited.

The fabrication of the PMOS transistor proceeds as shown in Figures 7-11. On both the NMOS and PMOS sides a silicon dioxide gate oxide 30 may be deposited in one embodiment. The gate oxide 30 may be covered by a gate material 34, such as polysilcon, in turn covered by a hard mask 34 for patterning. Then the gate material 34 and gate oxide

30 are patterned to generate the Figure 7 structure on the PMOS side 10a (and the same structure is created on the NMOS side 10b with the layer 18 replacing the layer 28).

Then, separate tip implants I (Figure 7) and standard lithographic patterning form the lightly doped source drain regions 39 on both NMOS and PMOS sides (Figure 8). A nitride spacer material may be deposited and anisotropically etched on both NMOS and

PMOS sides to form the spacers 36.

On the PMOS side 10a only, a trench 24 is formed through the layer 28 and into the layer 16, as shown in Figure 9. The trench 24 may be formed by reactive ion etching using SF₆ chemistry. The etching is constrained by the isolation 20 on one side and may isotropically undercut the gate structure on the other side. As a result, an isotropic etch profile may be achieved on the inward edges of the trench 24 as shown in Figure 9. During this step the NMOS side 10a may be covered by an oxide mask (not shown). Then, an epitaxial silicon germanium source drain 40 may be grown which fills the trench 24 and extends thereabove as indicated at Figure 10. The trench 24 may be filled using silicon germanium having 10-40 atomic percent germanium. Source drain doping may be done by insitu doping using a diborane source. The epitaxial source drain 40 only grows in the trench 24 because all other material is masked or covered. The source drain 40 is raised and continues to grow until the facets meet.

The fabrication of the NMOS transistor 10b, shown in Figure 11, proceeds correspondingly. However, a conventionally non-epitaxially grown deeper source drain (not shown) may be created.

The PMOS device 10a may have both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. The Si_1-yGe_y layer 28 acts as a channel and is grown on a relaxed Si_1-xGe_x buffer layer 16 with x less than y to produce in-plane biaxial compressive stress. In addition, a silicon germanium epitaxial source drain 40 produces uniaxial compressive stress in the channel <110> crystallographic direction. The source drain 40 has a higher germanium concentration than the layer 14 so the source drain 40 pushes inwardly from the sides compressing layer 28. With this combination of stress, higher mobility and, thus, higher device performance may be achieved compared to using either of the stresses alone in some embodiments.

Once the optimal stress condition is known, the device may be engineered to produce such stress through an epitaxial silicon germanium source drain 40 and a silicon germanium layered structure. Then, a graded silicon germanium buffer layer 14 may be grown on the silicon substrate 12 followed by a relaxed Si_1-xGe_x layer 16 as shown in Figure 10. Then, a thin Si_1-yGe_y layer 28 is grown to form a biaxial compressive strained channel.

The uniaxial stress is produced by the epitaxial source drain process using epitaxial Si_1-2Ge₂ grown in recessed source drain regions 40. Selecting the germanium fractions so that x is less than y and z is less than x achieves the desired compressive states.

The mobility gain may remain high even as vertical field (gate field) is applied in some embodiments. In addition, more head room may be provided to increase performance before the device hits the physical stress limit in some embodiments. With the provision of combined stress, holes may stay in their lowest transport effective mass in the <110> channel direction where scattering suppression is also the strongest. Silicon band structure has a minimum at the gamma point. It also has twelve wings in (0, +-1, +- 1), (+-1, 0, +-1) and (+-1, +-1, 0) directions. Ideally, almost all of the holes are placed in two wings in the (1, -1, 0) and (-1, 1, 0) direction to achieve the lowest possible transport effective mass in the channel direction. This can be achieved by applying both uniaxial compressive and biaxial compressive stress.

The biaxial compressive stress lowers the energy level of the four in-plane wings and removes holes from the eight off plane wings, placing them in the four in-plane wings. The four in-plane wings not only have smaller effective mass, but also have smaller density states, which leads to a reduction of scattering. The greatest mobility enhancement happens when the uniaxial compressive stress along the channel direction is added to the biaxial compressed device. According to simulation, when hole-optical phonon and surface roughness scattering occurs, most of the holes stay only in the wings along (1, -1, 0) and (-1, 1, 0), which has the smallest transport effective mass in the channel direction. Since only two wings are occupied, the density of states is also greatly reduced, enhancing scattering suppression. As a result, the combination stressed device may have higher mobility. While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

What is claimed is:

1. A method comprising: forming a PMOS transistor having both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress.

2. The method of claim 1 including forming a substrate covered by a first layer having an increasing concentration of germanium extending upwardly through the layer.

3. The method of claim 2 including covering said first layer with a second layer of constant germanium concentration.

4. The method of claim 3 including forming said second layer of Si_1-yGe_y and forming the first layer with Si_1-xGe_x where x is less than y.

5. The method of claim 4 including forming a source and drain of epitaxial silicon germanium of the form

Si_1-2Ge₂.

6. The method of claim 5 including making z greater than x and x less than y.

7. The method of claim 1 including forming uniaxial compressive stress in the channel direction by forming a silicon germanium epitaxial source drain.

8. The method of claim 1 including forming in-plane biaxial compressive stress by depositing a silicon germanium layer as a channel having the form Si_1-yGe_y and forming an underlying buffer layer of the form Si_1-xGe_x where x is less than y.

9. The method of claim 1 including forming NMOS and PMOS transistors at the same time.

10. The method of claim 9 including forming a graded germanium concentration silicon germanium buffer layer, covering said buffer layer with a layer of silicon germanium of constant germanium concentration, and covering said constant germanium concentration layer with a tensile strained silicon layer on both the NMOS and PMOS sides.

11. The method of claim 10 including selectively removing the tensile strained biaxial silicon layer on the PMOS side.

12. The method of claim 11 including selectively removing the tensile strained silicon layer using about 5 to 8 percent NH₄OH with a pH between about 10.2 and 10.4 at a temperature between about 20°C and 27°C.

13. The method of claim 11 including removing said tensile strained silicon layer on the PMOS side using an etchant that solubilizes the tensile strained silicon layer but does not solubilize underlying layers having higher germanium concentrations.

14. A semiconductor structure comprising: a substrate having a raised source drain of Si_1-2Ge₂; a gate electrode; a first layer under said gate electrode of

Si_1-yGe_y; and a second layer underneath said first layer, said second layer having Si_1- _xGe_x.

15. The structure of claim 14 wherein z is greater than x.

16. The structure of claim 15 wherein x is less than y.

17. The structure of claim 14 wherein said second layer has a graded germanium concentration.

18. The structure of claim 17 wherein said graded germanium concentration increases as it extends towards the gate electrode.

19. The structure of claim 14 including a third layer between said first and second layers.

20. The structure of claim 19 wherein said third layer has a relatively constant concentration germanium.

21. The structure of claim 20 wherein said third layer includes a concentration of germanium approximately equal to the maximum concentration of germanium in said second layer.

22. A semiconductor structure comprising: a substrate; a gate electrode over said substrate; and a channel under said gate electrode having uni-axial compressive stress and in-plane biaxial compressive stress.

23. The structure of claim 22 including an epitaxial source drain of Si_1-2Ge₂.

24. The structure of claim 23 including a first layer under said gate electrode of

Si_1-yGe_y and a second layer under said first layer, said second layer having Sii_-xGe_x.

25. The structure of claim 24 wherein z is greater than x.

26. The structure of claim 25 wherein x is less than y .

27. The structure of claim 24 wherein said second layer has a graded germanium concentration.

28. The structure of claim 27 wherein said graded germanium concentration increases as it extends towards the gate electrode.

29. The structure of claim 24 including a third layer between said first and second layers.

30. The structure of claim 29 wherein said third layer has a relatively constant concentration germanium.

31. The structure of claim 30 wherein said third layer includes a concentration of germanium approximately equal to the maximum concentration of germanium in said second layer.