WO2006093304A1 - Dispositif de stockage, methode de gestion de blocs memoire et programme - Google Patents

Dispositif de stockage, methode de gestion de blocs memoire et programme Download PDF

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Publication number
WO2006093304A1
WO2006093304A1 PCT/JP2006/304189 JP2006304189W WO2006093304A1 WO 2006093304 A1 WO2006093304 A1 WO 2006093304A1 JP 2006304189 W JP2006304189 W JP 2006304189W WO 2006093304 A1 WO2006093304 A1 WO 2006093304A1
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WIPO (PCT)
Prior art keywords
logical
block
data
definition information
unit
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PCT/JP2006/304189
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English (en)
Inventor
Tsuyoshi Takahashi
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Tokyo Electron Device Limited
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Publication of WO2006093304A1 publication Critical patent/WO2006093304A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory

Definitions

  • the present invention relates to a storage device, a memory block managing method, and a program.
  • Flash memories are used as storage media accessible (data readable and erasable) by computers, etc.
  • a data erasing process on a flash memory is done in a predetermined unit of storage capacity (generally called "block").
  • the storage device to store the address translation table must have a larger storage capacity, making the structure of the device complicated.
  • Unexamined Japanese Patent Application KOKAI Publication No. 2000-305839 discloses a storage device convenient for accessing, with an address translation table generated efficiently.
  • the blocks of the flash memory are classified into a plurality of zones, and the address translation table indicates the correspondence between the logical addresses and physical addresses of storage areas belonging to one of the zones. Then, when there comes a request for access to a storage area belonging to another zone, the address translation table is re-generated so that it will indicate the correspondence between the logical addresses and physical addresses of the storage areas belonging to that zone.
  • some devices are designed to reject access to a flash memory in a case where there are not a predetermined required number of good blocks (blocks in which data can be read and written properly) in one zone of the flash memory, from a viewpoint of improving the convenience of use of flash memories by unifying their standards.
  • Such a device has a problem that if occurrence of defective blocks (blocks in which data cannot be read and written properly) is concentrated in one zone of one flash memory and a required number of good blocks cannot be secured in that zone, all the zones included in that flash memory become access-prohibited.
  • the present invention was made in view of the above-described circumstance, and an object of the present invention is to provide a storage device, a memory block managing method, and a program capable of easily securing or keeping a required number of good blocks in a predetermined zone.
  • a storage device comprises: a storage unit (11) which includes a plurality of non- volatile memory blocks for storing data, each of which belongs to any of a plurality of logical zones and assigned a physical address; a logical zone definition information storage unit (123) which stores logical zone definition information for defining to which of the logical zones each of the memory blocks belongs; and a processing unit (121) which performs processes for storing user data in said storage unit (11), erasing the user data stored in said storage unit (11), and rewriting the logical zone definition information stored in the zone definition information storage unit (123), wherein: each of the memory blocks is constituted by a plurality of pages; and the processing unit (121) stores the user data in the memory block in a unit of page, and erases the user data or the logical zone definition information in a unit of memory block except in a case where it overwrites a predetermined value, based on the logical zone definition information stored in the logical zone definition information storage
  • the ranges of the logical zones can be redefined so that the required number of normal blocks can be secured in all of the logical zones, by rewriting the logical zone definition information. Accordingly, it becomes easy for the logical zones to secure or keep the required number of normal blocks.
  • the storage device may comprise a defective block detection unit (121) which detects a defective block which is a memory block in which data cannot be read or written properly, and in a case where the defective block detection unit (121) detects a defective block, the processing unit (121) may determine whether or not a number of normal blocks which are included in each of the logical zones and in which data can be read or written properly satisfies a predetermined condition, and in a case where determining that there is a logical zone in which the condition cannot be satisfied, rewrite the logical zone definition information in a manner that the condition is satisfied in all of the logical zones.
  • the processing unit (121) may determine whether or not each of the logical zones included in the storage unit (11) includes equal to or larger than a predetermined number of normal blocks, and in a case where determining that there is a logical zone that does not include equal to or larger than the predetermined number of normal blocks, rewrite the logical zone definition information in a manner that the logical zone includes equal to or larger than the predetermined number normal blocks and a difference in the number of normal blocks among the logical zones becomes small.
  • processing unit (121) may rewrite the logical zone definition information in a manner that the difference in the number of normal blocks among the logical zones becomes the smallest.
  • This structure makes a situation in which the required number of normal blocks are not secured more unlikely to happen, even in a case where a defective block is produced after the logical zones are redefined, thereby making it easier for the logical zones to secure or keep the required number of normal blocks.
  • the processing unit (121) may erase the logical zone definition information by overwriting the predetermined value, which represents that the logical zone definition information has been erased, on the logical zone definition information stored in the logical zone definition information storage unit (123). This enables the logical zone definition information to be rewritten with no need of erasing data in the memory block unit, further making it easier for the logical zones to secure or keep the required number of normal blocks.
  • the logical zone definition information stored in the logical zone definition information storage unit (123) may include the physical address of a memory block at a top of each of the logical zones.
  • the logical zone definition information stored in the logical zone definition information storage unit (123) may include a most-lately appearing physical address that can be taken by a memory block at a tail of each of the logical zones.
  • the memory blocks included in the storage unit (11) may be classified into either of exclusive occupation areas which are to be assigned only to fixed logical zones, and common areas which are to be assigned selectively to two predetermined logical zones, and the logical zone definition information stored in the logical zone definition information storage unit (123) may include the physical address of a memory block at a top of each of the logical zones, and/or a most-lately appearing physical address that can be taken by a memory block at a tail of each of the logical zones.
  • the processing unit (121) may comprise: a reception unit (121) which receives a logical address indicating a memory block to which a storage position of data to be read or written belongs; a logical zone specifying unit (121) which specifies the logical zone to which the memory block indicated by the received logical address belongs, based on the logical address received by the reception unit (121); an address translation table storage unit (11) which stores an address translation table storing information indicating correspondence between the logical address received by the reception unit (121) and a physical address of the memory block belonging to the logical zone specified by the logical zone specifying unit (121); an address translation table generation unit (121) which generates the address translation table and stores it in the address translation table storage unit (11); and a physical address specifying unit (121) which specifies the physical address associated with the logical address received by the reception unit (121), based on the address translation table stored in the address translation table storage unit (11).
  • the processing unit (121) may perform a process for reading and outputting data stored in the memory block specified by the physical address specifying unit (121), and/or a process for receiving data to be written in the memory block specified by the physical address specifying unit (121) and storing the received data in the memory block.
  • a memory block managing method is a method for managing a memory including a plurality of non- volatile memory blocks for storing data, each of which belongs to any of a plurality of logical zones, each of which is assigned a physical address, and each of which is constituted by a plurality of pages, wherein data is written in the memory block in a unit of page while data stored in the memory block is erased in a unit of memory block except in a case where a predetermined value is overwritten in the memory block, the method comprising: a processing step of performing a process for storing logical zone definition information defining to which of the logical zones each of the memory blocks belongs, in the memory block; and a detecting step of detecting any defective block in which data cannot be read or written properly, from the memory blocks, wherein in a case where any defective block is detected at the detecting step, it is determined, at the processing step, whether or not a number of normal blocks which are included in each of the logical zones and in which data can be read
  • the ranges of the logical zones can be redefined so that the required number of normal blocks can be secured in all of the logical zones, by rewriting the logical zone definition information. Accordingly, it becomes easy for the logical zones to secure or keep the required number of normal blocks.
  • a program controls a computer, connected to a memory including a plurality of non-volatile memory blocks for storing data, each of which belongs to any of a plurality of logical zones, each of which is assigned a physical address, and each of which is constituted by a plurality of pages, wherein data is written in the memory block in a unit of page while data stored in the memory block is erased in a unit of memory block except in a case where a predetermined value is overwritten in the memory block, to function as: a logical zone definition information storage unit which stores logical zone definition information defining to which of the logical zones each of the memory blocks belongs; a defective block detection unit which detects any defective block in which data cannot be read or written properly, from the memory blocks; and a processing unit which, in a case where the defective block detection unit detects any defective block, determines whether or not a number of normal blocks which are included in each of the logical zones and in which data can be read or written properly satisfies
  • the ranges of the logical zones can be redefined so that the required number of normal blocks can be secured in all of the logical zones, by rewriting the logical zone definition information. Accordingly, it becomes easy for the logical zones to secure or keep the required number of normal blocks.
  • a storage deyice, a memory block managing method, and a program capable of easily securing or keeping a required number of normal blocks in a predetermined zone can be realized.
  • FIG. 1 is a block diagram showing the structure of a storage system according to an embodiment of the present invention
  • FIG. 2 is a diagram exemplarily showing a logical structure of a storage area of a flash memory
  • FIG. 3 is a diagram exemplarily showing the ranges of physical zones and logical zones
  • FIG. 4 is a diagram showing the relationship among physical zone, logical zone, and logical zone boundary pointer
  • FIG. 5 is a diagram exemplarily showing information stored in a RAM
  • FIG. 6A is a diagram exemplarily showing the data structure of a BPT
  • FIG. 6B is a diagram showing a formula for obtaining the address assigned to each storage area of the BPT;
  • FIG. 7 is a flowchart showing an initial process
  • FIG. 8 is a flowchart showing a data reading process
  • FIG. 9 is a flowchart showing a BSFBPT generation process
  • FIG. 10 is a flowchart showing a data writing process
  • FIG. 11 is a continuation of the flowchart showing the data writing process
  • FIG. 12 is a continuation of the flowchart showing the data writing process
  • FIG. 13 is a continuation of the flowchart showing the data writing process.
  • FIG. 1 is a block diagram showing the physical structure of a storage system according to an embodiment of the present invention. As shown in FIG. 1, the storage system comprises a memory unit 1 and a computer 2.
  • the memory unit 1 is detachably mounted on the computer 2 via a slot of the computer 2.
  • the slot of the computer 2 is one for relaying a bus which is based on, for example, PC Card Standard.
  • the memory unit 1 comprises a flash memory 11 and a controller 12.
  • the flash memory 11 stores data supplied from the controller 12, supplies stored data to the controller 12, or erases stored data, in response to an access from the controller 12.
  • the storage area possessed by the flash memory 11 is made up of 262,144 pages as shown in, for example, FIG. 2, and each page has a storage capacity of 2,112 bytes. Memory cells included in each page are assigned addresses of 0 to 2111 serially.
  • Each page is made up of four columns each having a storage area of 528 bytes as shown in, for example, FIG. 2.
  • the columns included in each page are assigned column addresses of 0 to 3 serially.
  • Each column is made up of a data area occupying an area of 512 bytes from the start portion of the column, and a redundant area occupying the remaining 16 bytes. Accordingly, in the example shown in FIG. 2, the storage capacity of the data areas of the flash memory 11 is totally 512 megabytes.
  • Stored in the data area are data supplied from the computer 2 to be written, data to be supplied to the computer 2, etc. (hereinafter referred to as "user data").
  • a defective block flag for example, a defective block flag, an ECC (Error Correction Code), etc. are stored.
  • the defective block flag is a flag that indicates that the block including this redundant area is a block (defective block) which cannot properly store data.
  • ECC is data for confirming that the content of the usej data stored in the data area of the column to which the redundant area belongs is not destroyed.
  • a block is made up of a plurality of pages. For example, one block is constituted to include 128 pages counted from the top page.
  • the erasion of data stored in the flash memory 11 is done in the unit of block.
  • the flash memory 11 When instructed by the controller 12 of the memory unit 1 to erase data in a specific block, the flash memory 11 resets the stored content in all the memory cells included in that block.
  • the flash memory 11 is constituted by, for example, a NAND type flash memory, the stored value in each memory cell is reset to "1" by the data erasion.
  • the data areas in each block have a storage capacity of 256 kilobytes.
  • the whole storage area of the flash memory 11 is made up of 2,048 blocks.
  • the respective blocks are assigned physical block addresses of 00Oh to 7FFh serially from the top block. Note that in the present specification and drawings, the numbers with a letter "h" at the tail represent hexadecimal numbers. Pages belonging to each block are assigned page addresses of 0 to 127 serially.
  • the logical block address is recognized by the controller 12 as the unit of data reading, writing, or erasing, when data is read, written, or erased in the flash memory 11 in a later-described operation.
  • the total number of blocks to which the logical block addresses are assigned is a predetermined number (for example, 2,000 blocks) that is smaller than the total number of blocks physically existing in the flash memory 11.
  • the blocks of the flash memory 11 are classified into a plurality of physical zones in advance. Specifically, as shown in, for example, FIG. 3, the 512 blocks that are assigned the physical block addresses of 00Oh to IFFh constitute the first physical zone (physical zone 0). The 512 blocks that are assigned the physical block addresses of 200h to 3FFh constitute the second physical zone (physical zone 1). The 512 blocks assigned the physical block addresses of 40Oh to 5FFh constitute the third physical zone (physical zone 2). The remaining 512 blocks assigned the physical block addresses 60Oh to 7FFh constitute the fourth physical zone (physical zone 3). The physical zone 0, the physical zone 1, the physical zone 2, and the physical zone 3 are assigned the physical zone addresses of 0, 1, 2, and 3 in this order.
  • the blocks of the flash memory 11 are also classified into the same number of logical zones as the number of physical zones (according to the present embodiment, the number of logical zones is four including the logical zone 0 to logical zone 3).
  • the logical zone 0, the logical zone 1, the logical zone 2, and the logical zone 3 are identified by the logical zone addresses of 0, 1, 2, and 3 in this order.
  • the classification into the logical zones are made by the controller 12 in accordance with the rules (a) to (e) described below.
  • each physical zone the blocks belonging to the physical zone are classified into three kinds of areas of "front zebra area” "exclusive occupation area”, and “rear zebra area” in the order of blocks having smaller physical block addresses to those having larger addresses sequentially.
  • two continuous physical zones (k-1) and k include a shared "zebra area” of an ordinal number k-th. That is, the "rear zebra area” of the physical zone (k-1) and the “front zebra area” of the physical zone k constitute the k-th "zebra area”.
  • the blocks belonging to this zone are classified into two areas of "exclusive occupation area” and "rear zebra area”, in the order of blocks having smaller physical block addresses to those having larger addresses. Further, in the last physical zone (the physical zone 3 according to the present embodiment), the blocks are classified into two areas of "front zebra area” and "exclusive occupation area” in the order of blocks having smaller physical block addresses to those having larger addresses.
  • the blocks in the "exclusive occupation area" of a physical zone n (where n being 0, 1, 2, or 3) are assigned to a logical zone n. The blocks assigned here are the area indicated by "#1" in FIG. 3.
  • the "exclusive occupation area" of the physical zone 0 is 00Oh to IFCh;
  • the "rear zebra area" of the physical zone 0 is IFDh to IFFh;
  • the "front zebra area" of the physical zone 1 is 200h to 209h;
  • the "exclusive occupation area” of the physical zone 1 is 20Ah to 3F8h;
  • the "rear zebra area” of the physical zone 1 is 3F9h to 3FFh;
  • the "front zebra area" of the physical zone 2 is 400h to 405h;
  • the "exclusive occupation area" of the physical zone 2 is 406h to 5F5h;
  • the "rear zebra area" of the physical zone 2 is 5F6h to 5FFh;
  • the "front zebra area” of the physical zone 3 is 60Oh to 602h; - The "exclusive occupation area” of the physical zone 3 is 603h to 7FFh;
  • the physical zone 0 has no "front zebra area"
  • the physical zone 3 has no "rear zebra area". In case of FIG. 3:
  • the first "zebra area” is IFDh to 209h; - The second “zebra area” is 3F9h to 405h; and
  • the third "zebra area" is 5F6h to 602h.
  • FIG. 4 is a diagram for explaining a relationship among physical zone, logical zone, and logical zone boundary pointer, in a case where one block of the flash memory 11 is assigned to N (where N being an integer equal to or larger than 1) number of logical zones.
  • a logical zone boundary pointer is a pointer for storing the physical block address of the last block to be assigned to a logical zone n, among blocks belonging to an (n+l)-th "zebra area".
  • a (k-l)th zebra area is constituted by the rear zebra area of a (k-l)th physical zone and the front zebra area of a k-th physical zone.
  • a logical zone boundary pointer (indicated as "BP" in the drawing) indicating the boundary between a (k-l)th logical zone and a k-th logical zone is defined in the (k-l)th zebra area.
  • a logical zone boundary pointer indicating the boundary between the k-th logical zone and a (k+l)th logical zone is defined in a k-th zebra area.
  • the logical zone boundary pointer is stored in a predetermined storage area of the flash memory 11, and is updated in accordance with processes by the controller 12. Specifically, the update of the logical zone boundary pointer is done by overwriting an old logical zone boundary pointer with a sequence of bits representing a value "0" and writing a new logical zone boundary pointer. This eliminates the necessity for an operation for erasing the stored content of a vacant block in order to update the logical zone boundary pointer.
  • the initial value of a logical zone boundary pointer is set in advance by the manufacturer of the controller 12, or the like. This initial value is set in a manner that a block belonging to an n-th "zebra area" and already assigned to a logical zone (n-1) is not redundantly assigned to a logical zone n, in a state (initial state) where no postnatal defective block (i.e., a block which becomes defective after the flash memory 11 starts to be used) has been produced yet since the flash memory 11 started to be used. Furthermore, the initial value is defined such that any logical zone can secure therein equal to or larger than the above-described predetermined number of good blocks. Ih other words, the initial value of the logical zone boundary pointer is determined so as to indicate the largest physical block address that can be taken by the logical block address of the block at the tail of each logical zone, in the state where no postnatal defective block exists.
  • the controller 12 updates the logical zone boundary pointer. With this updating, the controller 12 can secure equal to or greater than the above-described number of good blocks in all the logical zones, even if the newly found postnatal defective block is excluded from the accessing target.
  • the controller 12 performs adjustments such that a block in an n-th "zebra area" that has already been assigned to a logical zone (n-1) is not redundantly assigned to a logical zone n. That is, the logical zone boundary pointer is reset so as to indicate the largest physical block address that can be taken by the logical block address of the last block of each logical zone, in the state where the newly found postnatal defective block is excluded from the accessing target.
  • a specific method of classifying the blocks to the logical zones 0 to 3 there is a method in which a range of logical block addresses to be assigned to the blocks of each logical zone is predefined, and the controller 12 assigns a logical block address to each block so as to match the range.
  • the range of logical block addresses to be assigned to the blocks of each logical zone may be as follows, for example.
  • the logical block addresses to be assigned to the blocks are equal to or larger than 000Oh and equal to or smaller than 01 FCh for the blocks belonging to the logical zone 0, equal to or larger than 01 FDh and equal to or smaller than 03F9h for the blocks belonging to the logical zone 1, equal to or larger than 03FAh and equal to or smaller than 05F6h for the blocks belonging to the logical zone 2, and equal to or larger than 05F7h and equal to or smaller than 07F3h for the blocks belonging to the logical zone 3, respectively.
  • the details will be described later.
  • the controller 12 comprises a CPU (Central Processing Unit) 121, a ROM (Read Only Memory) 122, and a RAM (Random Access Memory) 123, as shown in FIG. 1.
  • the CPU 121 is connected to the ROM 122, the RAM 123, and the flash memory 11, and is also connected to the computer 2.
  • the connection between the CPU 121 and the computer 2 may be via the above-described slot of the computer 2 detachably.
  • the CPU 121 performs processes to be described later, in accordance with a program in the ROM 122 stored therein in advance by the manufacturer of the controller 12 or the like.
  • the CPU 121 executes the instruction. Instructions to be executed by the CPU 121 include an instruction for accessing the flash memory 11.
  • the RAM 123 is constituted by, for example, an SRAM (Static RAM) or the like.
  • the RAM 123 includes a work memory area 131 and saving memory area 132 for the CPU 121.
  • the saving memory area 132 is a storage area for keeping, for a limited period of time, data that is stored in a block including a page targeted for writing in, in a later-described data writing process.
  • the RAM 123 stores a BSI (Block Search Index) 133 and a BPT (Block Pointer Table) 134 which are generated by the CPU 121.
  • BSI Block Search Index
  • BPT Block Pointer Table
  • the BSI 133 stores information for specifying which blocks belonging to one logical zone of the storage area of the flash memory 11 are vacant blocks.
  • the BSI 133 is generated ,and updated in accordance with the processes of the controller 12 and stored in the RAM 123.
  • the BSI 133 needs to have equal to or larger than a predetermined number of bits, which is the total number of good blocks to which logical block addresses are assigned in each logical zone. For example, if the total number of good blocks to which logical block addresses are assigned are 509 blocks per logical zone, the BSI 133 stores information associating the bits with predetermined vacant block codes in one-to-one correspondence in the order of earlier bits to later bits, for the top good block to the 509th block of a logical zone respectively.
  • the vacant block code represents "1" in a case where the associated good block is being a vacant block, and "0" in a case where not being a vacant block.
  • the CPU 121 generates zone information 135 which indicates which logical zone the BSI 133 currently stored in the RAM 123 concerns, and stores the zone information 135 in the RAM 123.
  • the BPT 134 stores information indicating correspondence between logical block addresses and physical block addresses, concerning the respective blocks belonging to a logical zone including blocks indicated by the BSI 133 as being vacant blocks (that is, this logical zone is the one indicated by the zone information 135 stored in the RAM 123).
  • the BPT 134 is generated or updated in accordance with a later-described process of the CPU 121, and is stored in the RAM 123.
  • the BPT 134 is stored in, for example, a predetermined storage area of the RAM 123.
  • the BPT 134 has a storage area for storing the physical block address corresponding to each logical block address.
  • the BPT 134 has a data structure as shown in, for example, FIG. 6A.
  • FIG. 6A shows an example where the total number of logical block addresses to be assigned to blocks in one logical zone is 509.
  • the BPT 134 has the total of 509 wards of storage areas which have addresses of lOOOh to 11 FCh assigned ward by ward, in the order of the top ward down.
  • Each address in the RAM 123 assigned to each storage area of the BPT 134 shown in FIG. 6A is calculated by the formula shown in FIG. 6B. That is, each address is equal to a value obtained by subtracting the product of the number of the logical zone indicated by the zone information 135 and 01FDh (i.e., a decimal number "509"), from the sum of a given logical block address and the minimum value among the addresses assigned to the storage areas (wards) making up the BPT 134 (this minimum value is an offset value).
  • the content stored in each one ward of storage area assigned its own ward address represents a block's physical block address that is associated with the logical block address associated with that ward address.
  • the block having the physical block address 02AIh is associated with a logical block address OOlh.
  • the computer 2 is typically constituted by a personal computer or the like.
  • the computer 2 has a slot of PCMCIA (Personal Computer Memory Card International Association) standard, stores program data representing an OS (Operating System) and driver, and executes the OS after the power is on.
  • PCMCIA Personal Computer Memory Card International Association
  • OS Operating System
  • the computer 2 activates the driver in accordance with the operation of the OS.
  • the computer 2 supplies the above-described instructions to the controller 12 or supplies target data to be written in the flash memory 11 (referred to as "user data"), to cause the CPU 121 to access the flash memory 11 to write the user data therein. Or, the computer 2 acquires data which the CPU 121 reads from the flash memory 1 in accordance with an instruction from the computer 2, from the CPU 121.
  • FIG. 7 is a flowchart showing an initial process.
  • FIG. 8 is a flowchart showing a data reading process.
  • FIG. 9 is a flowchart showing a BSI/BPT generation process.
  • FIG. 10 to FIG. 13 are flowcharts showing a data writing process.
  • the CPU 121 of the controller 12 of the memory unit 1 When the present storage system are activated, the CPU 121 of the controller 12 of the memory unit 1 performs the "initial process" shown in FIG. 7.
  • the CPU 121 When the initial process is started, the CPU 121 initializes part of the storage area of the RAM 123 in which the BPT 134, the BSI 133, and the zone information 135 are to be stored (FIG. 7, step SlOl).
  • the CPU 121 writes a predetermined value (for example, the above-described value "OFFFh") representing that no physical block address is associated, in the part of the storage area of the RAM 123 in which the BPT 134 is to be stored, for each block associated with the above-described address assigned ward by ward.
  • a predetermined value for example, the above-described value "OFFFh"
  • the CPU 121 initializes the logical values of all the bits in the part in which the
  • the CPU 121 reads the logical zone boundary pointers from the predetermined storage area of the flash memory 11 and stores them in the part in which the zone information 135 is to be stored.
  • the CPU 121 finds a block that stores yet-unread data in a redundant area thereof and that has the smallest physical block address, among the blocks belonging to the logical zone indicated by the zone information 135 stored in the RAM 123 at step SlOl.
  • the CPU 121 reads the data stored in the redundant area in a column belonging to the found block (step S 102).
  • the CPU 121 determines whether the block from which the data is read at step S 102 is a vacant block or not, based on the data read at step S102 (step S103). Specifically, for example, the CPU 121 determines whether a predetermined vacant block code is included or not in the data read at step S 102.
  • the CPU 121 writes a value representing that the block having been determined as a vacant block is a vacant block, in the BSI 133 (step S104).
  • the CPU 121 uses the physical block address of the block having been determined as a vacant block in order to find the position of a bit representing this physical block in the storage area of the RAM 123 in which the BSI 133 is to be stored, and rewrites the logical value of the bit at the found position to "1".
  • step S 103 the CPU 121 adds new information indicating the correspondence between the physical block address and logical block address of the block determined as not a vacant block to the BPT 134 (step S105). For example, in a case where the BPT
  • the CPU 121 writes the physical block address of the now-concerned block whose logical block address is read from the flash memory 11, in a part of the storage area of the RAM 123 for storing the BPT 134 which part is assigned a ward address associated with the logical block address read from the flash memory 11.
  • the CPU 121 determines whether or not the logical zone including the block from which the data in the redundant area has been read at step S 102 still has any block left after that block (step S106). In a case where it is determined that there is such a block left (step S106; YES), the CPU 121 returns the process to step S102. In a case where it is determined that there is not such a block left (step S106; NO), the CPU 121 terminates the initial process.
  • the BSI 133 and the BPT 134 are generated through the above-described initial process. (Data Reading Process)
  • the CPU 121 obtains an instruction for data reading, and a logical block address, page address, and column address indicating the page to read from (FIG. 8, step S201).
  • the CPU 121 specifies the logical zone which includes the obtained logical block address (step S202).
  • the computer 2 may cause the memory unit 1 to read a directory and FAT (File Allocation Tables) beforehand to obtain these data, and specify the column address of the column to read from, the page address of the page to which the column belongs, and the logical block address of the block to which the page belongs based on the obtained directory and FAT.
  • the block in which the directory and FAT are stored may be assigned a predetermined logical block address.
  • step S203 the CPU 121 goes to step S205.
  • the CPU 121 performs a "BSI/BPT generation process" shown in FIG. 9 for the logical zone specified at step S202 (i.e. the logical zone to which the target block of reading belongs), in order to generate a new BSI 133 and a new BPT 134 (step S204).
  • the CPU 121 specifies a block that stores yet-unread data in a redundant area thereof and that has the smallest physical block address, among the blocks belonging to the logical zone specified at step S202.
  • the CPU 121 reads the data stored in the redundant area of a column belonging to the specified block (FIG. 9, step S301). •
  • the CPU 121 performs the same process as step S103 based on the data read at step
  • step S301 to determine whether the block from which data has been read at step S301 is a vacant block or not (step S302).
  • step S302 the CPU 121 writes a value representing that the block determined as a vacant block is a vacant block in the BSI 133 (step S303).
  • the CPU 121 adds new information indicating the correspondence between the physical block address and logical block address of the block determined as not a vacant block to the BPT 134 (step S304).
  • the CPU 121 determines whether or not the logical zone specified at step S202 still has any block left after the block from which the data stored in the redundant area of a column has been read at step S301 (step S305). In a case where it is determined that there is such a block left (step S305; YES), the CPU 121 returns the process to step S301.
  • step S305 In a case where it is determined that there is not such a block left (step S305; NO), the
  • CPU 121 rewrites the zone information 135 stored in the RAM 123 so as to indicate the logical zone specified at step S202 (step S306), and terminates the BSFBPT generation process.
  • the CPU 121 having completed the BSI/BPT generation process at step S204 searches the BPT 134 using the logical block address supplied from the computer 2 at step S201 as the search key to obtain the physical block address associated with this logical block address (step S205). Then, the CPU 121 reads data from a column which is specified by the physical block address obtained at step S205 and the page address and column address supplied from the computer 2 (step S206), and supplies the read data to the computer 2. Through the above-described process, data is read from the flash memory 11 and supplied to the computer 2. (Data Writing Process)
  • the computer 2 supplies the controller 12 with an instruction for writing data in the flash memory 11, and the logical block address, page address, and column address of a column in which data included in a target file to be written is to be written.
  • the CPU 121 receives the instruction for writing data, and the logical block address, page address, and column address of the column in which the data included in the target file to be written is to be written (FIG. 10, step S401).
  • the computer 2 may obtain beforehand a directory and FAT from the memory unit 1, and specify the column address, page address, and logical block address of a column in which no data is stored, based on the obtained data. Then, the computer 2 may update the directory or FAT to register that logical block address therein, and writes back the updated directory or FAT to the flash memory 11. Also in this case, the block in which the directory and FAT are stored may be assigned a predetermined logical block address.
  • the CPU 121 specifies the logical zone to which the received logical block address belongs (step S402). Then, the CPU 121 reads the zone information 135 stored in the RAM 123, and determines whether or not the logical zone indicated by the read zone information 135 is the same as the logical zone specified at step S402 (step S403).
  • step S403 In a case where it is determined that they are the same as each other (step S403;
  • step S405 the CPU 121 goes to step S405.
  • step S403 the CPU 121 performs substantially the same process as the BSI/BPT generation process for the logical zone specified at step S402 to generate the BSI 133 and the BPT 134 (step S404).
  • the CPU 121 searches the BPT 134 by using the logical block address received at step S401 as the search key. That is, the CPU 121 searches and obtains a physical block address that is associated with the received logical block address (step S405). Then, the CPU 121 determines whether or nqt it has been able to search out and obtain a physical block address associated with the received logical block address (step S406).
  • step S406 In a case where it is determined that it has not been able to obtain a physical block address (step S406; NO), the CPU 121 erases data stored in the saving memory area 132 of the RAM 123 to initialize the saving memory area 132 (step S407). Specifically, for example, the CPU 121 updates each bit of the data stored in the saving memory area 132 to "1". To the contrary, in a case where it is determined that it has obtained a physical block address (step S406; YES), the CPU 121 reads the data stored in the block indicated by the obtained physical block address, and stores the read data in the saving memory area 132 of the RAM 123 (step S408).
  • the CPU 121 carries out the procedures at step S409 and thereafter, as if also the saving memory area 132 initialized at step S407 had gone through the storing of data at step S408.
  • the CPU 121 searches for the physical block address of a vacant block in which new data is to be written (step S409).
  • the CPU 121 determines whether or not there is any vacant block (step S410). In a case where it is determined that there is no vacant block (step S410; NO), the CPU 121 informs the computer 2 that there is no vacant block so that writing cannot be performed, and abends the data writing process.
  • step S410 the CPU 121 updates the BSI 133 so that the BSI 133 will indicate that the searched-out vacant block is no longer a vacant block (step S411).
  • the CPU 121 asserts its use of a register (writing register), which is for storing a variable representing a page in which user data is to be written at step S414 and step S415 to be described later.
  • the CPU 121 stores the page address of the top page of the block searched out at step S409 in the writing register.
  • the CPU 121 initializes the page address stored in the writing register (step S412) F Next, the CPU 121 determines whether or not the page address currently stored in the writing register is the same as the page address received at step S401 (step S413). In a case where it is determined that they are not the same as each other (step S413; NO), the CPU 121 goes to step S415.
  • the CPU 121 requests the computer 2 to supply a data portion which is included in the target user data to be written and which should be written in the page indicated by the page address stored in the writing register. In response to this request, the computer 2 supplies the corresponding data portion to the CPU 121.
  • the CPU 121 overwrites the user data portion supplied from the computer 2 on the data portion which is included in the data having been stored in the saving memory area 132 at step S408 and which was stored in a page indicated by the same page address as that currently stored in the writing register (step S414).
  • the CPU 121 reads the data portion which is included in the data having been stored in the saving memory area 132 at step S408 and which was stored in the page indicated by the same page address as that currently stored in the writing register, from the saving memory area 132. Then, the CPU 121 writes the read data portion in each column of the page which is specified by the physical block address searched out at step S409 and the page address stored in the writing register (step S415).
  • the CPU 121 determines whether or not the data writing at step S415 has been properly performed (step S416). This determination may be performed by, for example, reading the data from the page in which the data has been written and checking whether the read data and the written data are identical with each other. In a case where it is determined that the data writing has been performed properly (step S416; YES), the CPU 121 advances the process to step S421.
  • step S416 the CPU 121 determines that the block in which the data writing has not been performed properly has become a postnatal defective block, and writes a defective block flag in a redundant area of a column of that block (FIG. 12, step S417).
  • the CPU 121 determines whether or not each logical zone of the flash memory 11 has kept equal to or larger than a predetermined number of good blocks (step S418). This determination may be performed by, for example, reading data stored in a redundant area of a column of each block of the flash memory 11 and determining whether or not a defective block is included in the redundant area. Then, in a case where it is determined that all the logical zones have kept equal to or larger than the predetermined number of good blocks (step S418; YES), the CPU 121 returns the process to step S409.
  • the CPU 121 determines whether or not it is possible to lay a new setting so that that logical zone may include equal to or larger than the predetermined number of good blocks by rewriting the logical zone boundary pointers (step S419).
  • the CPU 121 determines whether or not it is possible to reset the logical zones to achieve a state in which "equal to or larger than the predetermined number of good blocks can be secured in all the logical zones even if the block having been determined at step S417 as a new postnatal defective block is excluded from the accessing target, plus no block in an n-th zebra area already assigned to a logical zone (n-1) is redundantly assigned to a logical zone n".
  • step S419 In a case where it is determined that is it impossible to reset the logical zones (step S419; NO), the CPU 121 determines that the flash memory 11 is no longer usable, and abends the data writing process. To the contrary, in a case where it is determined that resetting is possible (step S419; YES), the CPU 121 resets the logical zones so that all of them will include equal to or larger than the predetermined number of good blocks, by rewriting the logical zone boundary pointers stored in the zone information 135 and the flash memory 11 (step S420).
  • the CPU 121 may rewrite the logical zone boundary pointers, in a manner that, for example, the number of extra good blocks beyond the predetermined number is as uniform as possible among all the logical blocks.
  • the CPU 121 resets the logical zones in a manner that the difference in number of good blocks among all the logical blocks is the minimum.
  • the CPU 121 determines whether or not the page address currently stored in the writing register indicates the last page of the block in which to write the data (step S421). In a case where it is determined that it does not indicate the last page (step S421;
  • step S422 the CPU 121 increments the page address stored in the writing register (step S422). That is, the CPU 121 updates the page address stored in the writing register so as to indicate the next page of the page indicated by the page address currently stored. Finished with step S422, the CPU 121 returns the process to step S413. To the contrary, in a case where it is determined that the page address stored in the writing register indicates the last page of the block to write data in (step S421; YES), the CPU 121 advances the process to step S423 shown in FIG. 13.
  • the CPU 121 updates the BPT 134 by overwriting the physical block address of the block in which the user data has newly been written at step S415 on a storage area of the BPT 134 in which the physical block address obtained at step S405 is stored (step S423). However, in a case where no physical block address has been obtained at step S405, the CPU 121 overwrites the physical block address on a storage area of the BPT 134 in which a predetermined value representing that no physical block address is associated (for example, the above-described value "OFFFh”) is stored.
  • a predetermined value representing that no physical block address is associated for example, the above-described value "OFFFh"
  • the physical block address indicating the block in which the data has been newly written is newly associated with the logical block address which has been associated with the physical block address obtained at step S405 before, or newly associated with a logical block address which has been associated with no physical block address before.
  • the CPU 121 determines whether or not a physical block address has been obtained at step S405. That is, the CPU 121 determines whether or not there is any block whose data has been saved in the saving memory area 132 at step S408 (step S424). In a case where there is no block whose data has been saved (step S424; NO), the CPU 121 notifies the computer 2 that the writing of the user data is completed, and terminates the data writing process.
  • the CPU 121 erases (flash-erases) the data stored in the block indicated by the physical block address obtained at step S405, and writes a vacant block code in a redundant area of a column belonging to the block having the data erased
  • the CPU 112 updates the BSI 133 by rewriting it to indicate that the block having the data erased at step S425 is a vacant block (step S426). Then, the CPU 121 notifies a completion of the data writing to the computer 2, and terminates the data writing process.
  • the user data supplied from the computer 2 is stored in the flash memory 11.
  • the BSI 133 is updated by the CPU 121 so as to properly indicate any vacant block newly produced and any vacant block having vanished as the result of the data writing.
  • the BPT 134 is updated by the CPU 121 so as to indicate the right correspondence between the physical block addresses and the logical block addresses.
  • the logical zones are reset by the CPU 121 so that all the logical zones can secure equal to or larger than the predetermined number of good blocks. That is, the flash memory 11 can be saved from being unusable totally because some of its logical zones do not include equal to or larger than the predetermined number of good blocks.
  • the structure of the storage system is not limited to be above-described one.
  • the number of physical zones and logical zones in the storage area of the flash memory 11 are all arbitrary; the above-described embodiment is one example.
  • an arbitrary computer-readable/writable storage device can be used instead of the flash memory 11.
  • the format of the information representing the storage area of the data stored in the flash memory 11 is arbitrary, except that of the logical zone.
  • CHS Cylinder-Head-Sector
  • the logical zone boundary pointer may be stored in a predetermined area of the RAM 123.
  • the RAM 123 may have adaptability to being backed up by a battery, etc., or to functioning as a non-volatile memory.
  • the ROM 122 may be constituted by an EEPROM (Electrically Erasable Programmable Read-Only Memory) or other types of non- volatile memory that can rewritably store data, so that the ROM 122 may assume the function of the RAM 123.
  • the CPU 121 may associate data stored in the flash memory 11 accessed by the CPU 121 with the logical block address and physical block address of the page in which the data is stored and store them in the RAM 123 as a record, or may store them by itself.
  • the CPU 121 may obtain the addresses of vacant blocks appearing after a vacant block in which data was written last, sequentially in the order of smaller physical block addresses to larger physical block addresses in each logical zone. However, in a case where there is no succeeding vacant block, it is preferred that the address of the top vacant block be obtained.
  • the CPU 121 writes the physical block address of a vacant block in which data was written last, in a predetermined storage area of each logical zone of the flash memory 11. Then, at step S409, the CPU 121 reads the physical block address of the formerly vacant block stored in the predetermined storage area of the logical zone in which data is to be written. Then, the CPU 121 obtains the vacant block appearing first among those blocks appearing after the formerly vacant block indicated by the read physical block address. However, in a case where there is no such vacant block in the logical zone in which data is to be written, the CPU 121 obtains a block having the smallest physical block address in the logical zone.
  • This realizes cyclic writing of data into the vacant blocks in each logical zone, and ensures that only certain ones of the blocks are not updated more frequently than the other ones are, preventing the performance of only certain blocks from being deteriorated.
  • the CPU 121 may specify a vacant block appearing first among those blocks appearing after a vacant block in which data was written last in each logical zone, by searching the BSI 133. Then, the CPU 121 may write mark data indicating that this block is the vacant block in which data is to be written next, in a redundant area of the specified vacant block. However, in a case where there is no vacant block appearing after the block in which data was written last, it is preferred that the top vacant block in the same logical zone be used next.
  • the CPU 121 may search the redundant area of each block in the flash memory 11 to obtain the mark data, and use the vacant block in which the mark data is written and the vacant blocks appearing thereafter, sequentially in the order of those having smaller physical block addresses to those having larger physical block addresses.
  • mark data a predetermined value represented by two digits in hexadecimal, other than a value "00h", is typically used, in a case where the flash memory 11 is a NAND type EEPROM.
  • the CPU 121 writes user data in the data area of the vacant block in which the mark data is written. Then, the CPU 121 removes the mark data by overwriting a value "00h" in the redundant area in which the mark data is written. Hence, the stored data in the block including the mark data needs not be erased in order to remove the mark data.
  • the storage system of the present invention can be realized by an ordinary computer system, not by a dedicated system.
  • a program for executing the above-described operations of the controller 12 and computer 2 may be installed on a personal computer connected to the flash memory 11, from a recording medium (a flexible disk, a CD-ROM, etc.) storing the program, whereby a storage system capable of performing the above-described processes can be constructed.
  • the storage system for performing the above-described processes can be built up, alternatively by installing a program for executing the above-described operation of the controller 12 on a first personal computer connected to the flash memory 11 from a recording medium storing the program, and installing a program for executing the above-described operation of the computer 2 on a second personal computer connected to the first personal computer from a recording medium storing the program.
  • these programs may be uploaded on a BBS (Bulletin Board System) of a communication line and distributed through the communication line.
  • a carrier wave may be modulated by a signal representing these programs, and the obtained modulated wave may be transmitted, so that an apparatus that receives the modulated wave may demodulate the modulated wave and restore the programs.
  • Such an apparatus can perform the above-described processes by activating these programs and executing the programs under the control of an OS (Operating System) in the same way as executing other application programs.
  • OS Operating System
  • OS constitutes a part of one structural element of the present invention
  • a program from which such a part is excluded may be stored in a recording medium. Even in this case, according to the present invention, a program for realizing each function or each step to be executed by the computer is stored in the recording medium.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Les blocs d'une mémoire flash (11), qui font chacun partie de l'une des zones logiques, se voient attribuer une adresse physique, tandis qu'un pointeur réinscriptible définit à quelle zone appartient chacun des blocs. Lorsqu'un bloc défectueux est détecté dans la mémoire flash, une unité centrale détermine si le nombre des blocs normaux de chaque zone logique satisfait ou non à une condition prédéterminée, et restructure les zones logiques de manière à satisfaire ladite condition dans toutes les zones logiques au cas où elle ne serait pas satisfaite dans certaines d'entre elles.
PCT/JP2006/304189 2005-03-01 2006-02-28 Dispositif de stockage, methode de gestion de blocs memoire et programme WO2006093304A1 (fr)

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JP2005-55746 2005-03-01

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963983A (en) * 1996-04-15 1999-10-05 International Business Machines Corporation Method and apparatus for dynamically creating conversion tables to access a semiconductor memory device
WO2004053888A2 (fr) * 2002-12-09 2004-06-24 Sandisk Corporation Ajustement de limites de zones de defauts dans des memoires remanentes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963983A (en) * 1996-04-15 1999-10-05 International Business Machines Corporation Method and apparatus for dynamically creating conversion tables to access a semiconductor memory device
WO2004053888A2 (fr) * 2002-12-09 2004-06-24 Sandisk Corporation Ajustement de limites de zones de defauts dans des memoires remanentes

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