WO2006091785A1 - Interface de conversion permettant une vue unifiee de simulations de systemes de plusieurs ordinateurs - Google Patents

Interface de conversion permettant une vue unifiee de simulations de systemes de plusieurs ordinateurs Download PDF

Info

Publication number
WO2006091785A1
WO2006091785A1 PCT/US2006/006541 US2006006541W WO2006091785A1 WO 2006091785 A1 WO2006091785 A1 WO 2006091785A1 US 2006006541 W US2006006541 W US 2006006541W WO 2006091785 A1 WO2006091785 A1 WO 2006091785A1
Authority
WO
WIPO (PCT)
Prior art keywords
simulation
simulations
recited
readable medium
computer readable
Prior art date
Application number
PCT/US2006/006541
Other languages
English (en)
Inventor
Niels Vanspauwen
Tom Michaels
Karl Rompaey
Original Assignee
Coware, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/066,945 external-priority patent/US7742905B2/en
Priority claimed from US11/066,841 external-priority patent/US7716031B2/en
Application filed by Coware, Inc. filed Critical Coware, Inc.
Publication of WO2006091785A1 publication Critical patent/WO2006091785A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3664—Environments for testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3632—Software debugging of specific synchronisation aspects

Abstract

L'invention permet d'avoir une vue unifiée de simulations de systèmes de plusieurs ordinateurs, et sur un processus de simulation comportant: une filière de simulation exécutant plusieurs simulations de systèmes d'ordinateurs; ainsi qu'une filière d'assistance au débogage fournissant une vue unifiée des simulations. Pour fournir cette vue unifiée, la filière utilise une interface externe et une interface interne pour chacune des simulations et une interface effectuant des conversions entre l'interface externe et l'interface interne. L'interface externe fournit ainsi une vue unifiée des simulations. Tout en permettant à une seule plate-forme de débogage de gérer et observer les situations.
PCT/US2006/006541 2005-02-25 2006-02-22 Interface de conversion permettant une vue unifiee de simulations de systemes de plusieurs ordinateurs WO2006091785A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/066,841 2005-02-25
US11/066,945 US7742905B2 (en) 2005-02-25 2005-02-25 Method and system for dynamically adjusting speed versus accuracy of computer platform simulation
US11/066,841 US7716031B2 (en) 2005-02-25 2005-02-25 Interface converter for unified view of multiple computer system simulations
US11/066,945 2005-02-25

Publications (1)

Publication Number Publication Date
WO2006091785A1 true WO2006091785A1 (fr) 2006-08-31

Family

ID=36927763

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2006/006541 WO2006091785A1 (fr) 2005-02-25 2006-02-22 Interface de conversion permettant une vue unifiee de simulations de systemes de plusieurs ordinateurs
PCT/US2006/006298 WO2006093762A1 (fr) 2005-02-25 2006-02-22 Simulation de plate-forme informatique

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2006/006298 WO2006093762A1 (fr) 2005-02-25 2006-02-22 Simulation de plate-forme informatique

Country Status (1)

Country Link
WO (2) WO2006091785A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10303592B2 (en) 2015-03-02 2019-05-28 Adp, Llc Multiple device testing system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3077910B1 (fr) * 2013-12-02 2018-07-11 Intel Corporation Procédés et appareil pour optimiser la consommation de ressources de simulation de plateforme

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980032143A (ko) * 1996-10-18 1998-07-25 윤종용 멀티프로세서 회로의 시뮬레이션을 위한 방법 및 장치
US5790778A (en) * 1996-08-07 1998-08-04 Intrinsa Corporation Simulated program execution error detection method and apparatus
US6418392B1 (en) * 1998-03-20 2002-07-09 National Instruments Corporation System and method for simulating operations of an instrument
US6587995B1 (en) * 2000-04-19 2003-07-01 Koninklijke Philips Electronics N.V. Enhanced programmable core model with integrated graphical debugging functionality
US6601229B1 (en) * 2000-03-09 2003-07-29 International Business Machines Corporation Client/server behavioral modeling and testcase development using VHDL for improved logic verification
US6625572B1 (en) * 1999-12-22 2003-09-23 Lsi Logic Corporation Cycle modeling in cycle accurate software simulators of hardware modules for software/software cross-simulation and hardware/software co-simulation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784552A (en) * 1993-07-28 1998-07-21 Digital Equipment Corporation Debugging a computer program by simulating execution forwards and backwards in a main history log and alternative history logs
US5911073A (en) * 1997-12-23 1999-06-08 Hewlett-Packard Company Method and apparatus for dynamic process monitoring through an ancillary control code system
US6826717B1 (en) * 2000-06-12 2004-11-30 Altera Corporation Synchronization of hardware and software debuggers
KR100425690B1 (ko) * 2001-12-29 2004-04-01 엘지전자 주식회사 조건부 메모리 억세스 회로

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790778A (en) * 1996-08-07 1998-08-04 Intrinsa Corporation Simulated program execution error detection method and apparatus
KR19980032143A (ko) * 1996-10-18 1998-07-25 윤종용 멀티프로세서 회로의 시뮬레이션을 위한 방법 및 장치
US6418392B1 (en) * 1998-03-20 2002-07-09 National Instruments Corporation System and method for simulating operations of an instrument
US6625572B1 (en) * 1999-12-22 2003-09-23 Lsi Logic Corporation Cycle modeling in cycle accurate software simulators of hardware modules for software/software cross-simulation and hardware/software co-simulation
US6601229B1 (en) * 2000-03-09 2003-07-29 International Business Machines Corporation Client/server behavioral modeling and testcase development using VHDL for improved logic verification
US6587995B1 (en) * 2000-04-19 2003-07-01 Koninklijke Philips Electronics N.V. Enhanced programmable core model with integrated graphical debugging functionality

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10303592B2 (en) 2015-03-02 2019-05-28 Adp, Llc Multiple device testing system

Also Published As

Publication number Publication date
WO2006093762A1 (fr) 2006-09-08

Similar Documents

Publication Publication Date Title
US8903703B2 (en) Dynamically adjusting speed versus accuracy of computer platform simulation
US7716031B2 (en) Interface converter for unified view of multiple computer system simulations
US8180620B2 (en) Apparatus and method for performing hardware and software co-verification testing
US7133820B2 (en) Method and apparatus for debugging programs in a distributed environment
JP6086230B2 (ja) 中央演算装置、情報処理装置、および仮想コア内レジスタ値取得方法
EP2652600B1 (fr) Ramification de machines virtuelles et exécution parallèle
JP5270330B2 (ja) マルチコアマイコンシステムのシミュレーション方法及びシミュレーション装置
US20080208555A1 (en) Simulation method and simulation apparatus
US8843910B1 (en) Identifying a set of functionally distinct reorderings in a multithreaded program
US8473921B2 (en) Debugging mechanisms in a cache-based memory isolation system
US20130159977A1 (en) Open kernel trace aggregation
US8495344B2 (en) Simultaneous execution resumption of multiple processor cores after core state information dump to facilitate debugging via multi-core processor simulator using the state information
US7650259B2 (en) Method for tuning chipset parameters to achieve optimal performance under varying workload types
US20230342198A1 (en) Method for reproducible parallel simulation at electronic system level implemented by means of a multi-core discrete-event simulation computer system
US7895027B2 (en) HDL re-simulation from checkpoints
JP5542643B2 (ja) シミュレーション装置及びシミュレーションプログラム
WO2006091785A1 (fr) Interface de conversion permettant une vue unifiee de simulations de systemes de plusieurs ordinateurs
CN111506395B (zh) 一种混合仿真的全数字虚拟运行环境的实现方法及装置
US11243873B2 (en) Concurrency testing
CN114780409A (zh) 基于程序运行进程的断点设置方法、电子设备和存储介质
US8914274B1 (en) Method and system for instruction set simulation with concurrent attachment of multiple debuggers
Ko et al. Hardware-in-the-loop simulation for CPU/GPU heterogeneous platforms
US9600422B2 (en) Monitoring accesses to memory in a multiprocessor system
Pouget et al. User level DB: a debugging API for user-level thread libraries
Jämbäck Evaluation of Real-Time Linux on RISC-V processor architecture

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06735984

Country of ref document: EP

Kind code of ref document: A1