WO2006091785A1 - Interface de conversion permettant une vue unifiee de simulations de systemes de plusieurs ordinateurs - Google Patents

Interface de conversion permettant une vue unifiee de simulations de systemes de plusieurs ordinateurs Download PDF

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Publication number
WO2006091785A1
WO2006091785A1 PCT/US2006/006541 US2006006541W WO2006091785A1 WO 2006091785 A1 WO2006091785 A1 WO 2006091785A1 US 2006006541 W US2006006541 W US 2006006541W WO 2006091785 A1 WO2006091785 A1 WO 2006091785A1
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WIPO (PCT)
Prior art keywords
simulation
simulations
recited
readable medium
computer readable
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PCT/US2006/006541
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English (en)
Inventor
Niels Vanspauwen
Tom Michaels
Karl Rompaey
Original Assignee
Coware, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/066,945 external-priority patent/US7742905B2/en
Priority claimed from US11/066,841 external-priority patent/US7716031B2/en
Application filed by Coware, Inc. filed Critical Coware, Inc.
Publication of WO2006091785A1 publication Critical patent/WO2006091785A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3664—Environments for testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3632—Software debugging of specific synchronisation aspects

Definitions

  • Embodiments here presented relate to the field of software tools for debugging
  • simulations relate to methods and systems that provide a single debugging platform with a unified view of multiple simulations.
  • ASIP application-specific instruction set processors
  • SoC systems-on-chip
  • One of the key factors for a successful design of application-specific instruction set processors (ASIP) is an efficient architecture exploration phase.
  • the objective of the architecture exploration is to reduce the huge design space in order to find the best-suited architecture for a given application under a number of constraints, such as performance, power consumption, chip size, and flexibility.
  • large parts of the design space exploration stiil have to be carried out by simulating alternative architecture implementations. Therefore, design methodology and simulation performance have a significant impact on the efficiency of the exploration process, and hence, on the quality of the architecture implementation and the design time.
  • Figure 1 depicts a conventional simulation environment in which a separate debugger is required to observe and control each simulation.
  • the environment is used to simulate an architecture (or platform) that in this case includes multiple processor cores and hardware, such that the platform may be debugged.
  • the hardware debugger 150 and each processor core debugger e.g., CPU1 and CPU2 debuggers 170
  • the hardware debugger 150 executes a simulation kernel 160 comprising a hardware simulation 180 and two processor core simulations (CPU1 and CPU2 simulations 175).
  • the hardware debugger 150 has an application program interface (API) to communicate with the hardware simulation 180.
  • API application program interface
  • the processor core simulations 175 each have a software wrapper 185.
  • the software wrapper 185 does not allow the processor core simulations 175 to be debugged via the hardware debugger 150. That is, the software wrappers do not allow control and observation of the actual simulation. Rather, separate processor core debuggers 170 are required to control and observe the processor core simulations 175, such that the processor cores may be debugged. Thus, a separate debugger is required to control and observe each simulation in order to debug the platform.
  • embodiments of the present invention provide methods and systems that provide a unified view of multiple simulations being used to simulate different aspects of a computer system platform.
  • the unified view allows a single debugger to control and observe all simulations.
  • the simulations may include a processor core simulation, a hardware simulation, or the like.
  • Embodiments of the present invention allow the simulations to be rewound with synchronization of the simulations preserved.
  • Embodiments of the present invention allow breakpoints/watchpoints involving events in multiple simulations. Embodiments of the present invention provide these advantages and others not specifically mentioned above but described in the sections to follow.
  • One embodiment in accordance with the present invention is a computer readable medium having stored thereon instructions for implementing a method of providing a unified view of multiple computer system simulations.
  • the instructions comprise a simulation process having a simulation thread that executes a plurality of computer system simulations.
  • the simulation process also has a debug support thread that provides a unified view of the simulations.
  • the debug support thread has an external interface, an internal interface to each of the simulations, and an interface converter that converts between the external interface and the internal interfaces.
  • the external interface provides a unified view of the simulations.
  • the external interface allows a single debugging platform to control and observe the simulations.
  • the instructions include a debugger process that is operable to communicate with the debug support thread via the external interface.
  • the single debugger has debug access to control and observe each of the simulations.
  • Another embodiment in accordance with the present invention is a computer-implemented method of providing a unified view for debugging with multiple simulations, such as processor core and hardware simulations.
  • the method comprises receiving a request from a debugging process for debugging access to one of a plurality of simulations in a simulation process.
  • the debugging access may be for controlling or observing a simulation.
  • the simulations have different debugging interfaces from each other.
  • the request is converted to a format that is compliant with the debugging interface of the simulation specified in the request.
  • the converted request is passed on to the simulation via its debugging interface. Therefore, the converting and passing the request provides the debugging process a unified view of the simulations.
  • a simulation process has a simulation thread that executes a plurality of computer system simulations.
  • the simulation process also has a debug support thread that provides a unified view of the simulations.
  • the debug support thread has an external interface, an internal interface to each of the simulations, and an interface converter that converts between the external interface and the internal interfaces.
  • the external interface provides a unified view of the simulations.
  • the external interface allows a single debugging platform to control and observe the simulations.
  • Figure 1 is a diagram of a conventional debugging environment employing separate debuggers for each simulation.
  • Figure 2 is a diagram of a system for presenting a unified view of multiple simulations, in accordance with an embodiment of the present invention.
  • Figure 3 is a flowchart illustrating a computer-implemented method of facilitating debugging via circuit simulations.
  • Figure 4 illustrates a breakpointing sequence diagram, in accordance with an embodiment of the present invention.
  • Figure 5 depicts a sequence diagram for implemented a watchpoint, in accordance with an embodiment of the present invention.
  • Figure 6 is an exemplary computer system that may serve as a platform upon which embodiments of the present invention may be executed.
  • Figure 7 is a block diagram illustrating a simulation kernel in accordance with an embodiment of the present invention.
  • Figure 8A is a diagram illustrating dynamically modifying a quantum of execution units performed by simulation while maintaining behaviorally correct results, in accordance with an embodiment of the present invention.
  • Figure 8B is a diagram illustrating dynamically modifying a quantum when a simulation detects a dependency on another simulation or a halting point in its simulation, in accordance with an embodiment of the present invention.
  • Figure 8C is a diagram illustrating dynamically modifying a quantum when a simulation runs ahead of other simulations, in accordance with an embodiment of the present invention.
  • Figure 9 is a flowchart illustrating steps of a process of performing a simulation of a computer system platform, in accordance with the present invention.
  • Figure 10 is a block diagram of a simulation kernel illustrating backdoor memory accesses, in accordance with the present invention.
  • Embodiments of the present invention allow a computer system platform developer to have a unified view of the platform under development.
  • Embodiments of the present invention provide a unified view of various simulations being used to simulate the computer platform. For example, by allowing a unified view of multiple simulations, embodiments of the present invention allow a user to observe and control one or more processor core simulations, a hardware simulation, etc., from a single debugging application.
  • Embodiments of the present invention allow breakpoints and watchpoints to be set using a combination of events in different simulations.
  • FIG. 2 is a diagram of a system for presenting a unified view of multiple simulations, in accordance with an embodiment of the present invention.
  • the simulation process 250 comprises a debug support thread 210 and a simulation kernel thread 230.
  • the simulation kernel thread 230 comprises multiple simulations (275a, 275b, 280), each of which simulates one or more aspects or portions of the computer system platform.
  • the simulations include two processor core simulations 275a, 275b and a separate hardware simulation 280.
  • the simulation kernel thread 230 may contain other types of simulations.
  • any particular type of simulation be present.
  • the simulation kernel thread controls the execution of the various simulations.
  • the simulation kernel thread invokes the various simulations, wherein each simulation is allowed to execute for up to a pre-determined number of clock cycles without stopping to, for example, synchronize with other simulations.
  • the pre-determined number of clock cycles is referred to herein as a quantum.
  • the simulation may halt prior to the end of the quantum of clock cycles. For example, if the simulation encounters a breakpoint or watchpoint it halts prior to completing the quantum of clock cycles.
  • the quantum is dynamically adjustable and may be based on simulation events. If the quantum is set relatively high, the computer system platform simulation may be faster but possibly less accurate. If the quantum is set lower, the platform simulation may be slower and possibly more accurate. For example, a hardware designer may desire a very accurate simulation, whereas a software developer may desire a faster simulation and be willing to trade some accuracy.
  • the platform debugger 270 is a tool that allows a user to observe and control the simulations 275a, 275b, 280, wherein the platform being simulated may be debugged.
  • the debug support thread 210 comprises an interface converter 220 that allows the platform debugger 270 to have a unified view of all of the simulations 275a, 275b, 280 in the simulation kernel thread 230.
  • the interface converter 220 presents an external API 222 to the platform debugger 270.
  • Each of the simulations has a debug interface 277a-c that allows observation and control of the actual simulation.
  • the interface converter has API converter blocks 240a-c that each convert from the external API to the respective debug APIs used by each of the simulations.
  • the platform debugger 270 has a uniform view to observe and control the simulations 275a, 275b, 280.
  • the platform debugger 270 may use an API call to inspect or to modify a simulation.
  • API calls that modify a simulation are allowed only when the simulation is halted.
  • the inter-process communication between the platform debugger 270 and the simulation process 250 is implemented with the Common Object Request Broker Architecture (CORBA), in one embodiment.
  • CORBA Common Object Request Broker Architecture
  • interprocess communication is not limited to CORBA.
  • the platform debugger 270 may execute on the same computer system as the simulation process 250. Alternatively, the platform debugger 270 executes on a different computer system than the simulation process 250.
  • "stand-alone" debuggers (not depicted in Fig. 2) that control and observe only one simulation may be added to the debugging environment.
  • Some of the simulations may have a software wrapper 285, in order to allow inter-simulation communication.
  • the CPU1 and CPU2 simulations 275a, 275b each have their own software wrapper 285 to allow communication with the hardware simulation 280.
  • the platform debugger 270 does not need the software wrappers 285 to control and observe the simulations 275a, 275b, 280.
  • the simulation process 250 comprises a control mechanism 290 for halting and starting execution of the simulation kernel thread 230. Furthermore, embodiments of the present invention synchronize the various simulations at various points in their execution. In other words, the simulations are halted at a common point in execution. For example, the simulations may execute sequentially and may be aware of a common clock such that each simulation can be halted at the same clock cycle (e.g., a common point in their respective executions).
  • the control mechanism 290 comprises a semaphore, although the present invention is not so limited.
  • the debug support thread 210 allows continued viewing of the simulations when they are halted.
  • the control mechanism 290 is used to halt execution of all simulation processes. For example, if the CPU 1 simulation 275a detects that a breakpoint is hit, it may signal the control mechanism 290, which halts the execution of the entire simulation kernel thread 230.
  • the debug support thread 210 may signal the control mechanism 290, wherein the simulation kernel thread 230 resumes execution.
  • thread may apply to an operating system process.
  • thread is not limited to an operating system process.
  • the thread may be a part of an application program process.
  • Halt-points may include breakpoints, watchpoints, and the like.
  • a , breakpoint typically refers to a location in code, wherein the simulation halts and passes control, of execution to the debugger when the code is hit.
  • a watchpoint typically refers to a data access (e.g., a read or write of memory, hardware register, etc.), wherein a simulation halts and passes control of execution to the debugger when the data access occurs.
  • Haltpoints are not limited to the examples herein and may be triggered by any event related to a simulation.
  • embodiments of the present invention allow a user to set multi- simulation halt-points.
  • multi-simulation halt- point, multi-simulation breakpoint, multi-simulation watchpoint, multi-simulation breakpointVwatchpoint, or the like means that the halt-point or the like is based on events in two different simulations.
  • the events may be the combination of the program counter in the CPU 1 simulation 275a reaching a user-defined value and an access to a register of a hardware simulation 280.
  • FIG. 3 is a flowchart illustrating a computer-implemented method of facilitating debugging via circuit simulations.
  • Step 310 is receiving a request from a debugging process for debugging access to one of a plurality of simulations in a simulation process.
  • Debugging access allows observation and control of the simulations.
  • the request may be received by a debug support thread in the simulation process.
  • the plurality of simulations may be executing in a separate thread in the simulation process.
  • the simulations have different debugging interfaces from each other for control and observation of the actual simulation.
  • Step 320 is converting the request to a format that is compliant with a debugging interface of the requested simulation. Step 320 may be performed by one of the interface converter blocks 240.
  • Step 330 is passing the converted request to the simulation via the debugging interface.
  • the debugging process e.g., platform debugger 270
  • the term debugging access with respect to a simulation means access that allows control and observation of the simulation.
  • the request is for establishing multi-simulation breakpoints.
  • Step 340 is storing synchronized results of the simulations in a database.
  • the database stores information that allows the results from each simulation to be compared at like points in time or execution.
  • Embodiments of the present invention allow the simulations to be rewound, such that stored values may be viewed by the debugger. Moreover, the synchronization of the simulations is maintained. Moreover, the debugger can step through the results, wherein the results of all simulations are stepped together.
  • Step 350 is rewinding the simulations.
  • the results stored in the database are presented to the debugger, wherein the debugger views the results synchronized by time as measured by clock cycles.
  • FIG. 4 illustrates a breakpointing sequence diagram 400, in accordance with an embodiment of the present invention.
  • a semaphore is used as the control mechanism.
  • the control mechanism is not limited to a semaphore.
  • a user 268 inputs the breakpoint information to the platform debugger (arrow 405).
  • the platform debugger sends a message to the debug support thread identifying the processor core simulation and breakpoint information (arrow 410).
  • the debug thread uses the interface converter to convert from the external API to the debug API for the processor core simulation (arrow 415).
  • the breakpoint information is then passed on to the core simulation (arrow 420).
  • the processor core simulation sends a message to the control mechanism indicating the time at which the breakpoint occurred (arrow 425).
  • the processor core simulation executes in a run-ahead loop and allows other simulations to catch up after a breakpoint is hit, in one embodiment.
  • the simulations may be invoked by the simulation kernel thread to each execute up to a pre-determined number of clock cycles. If a simulation hits a breakpoint while executing its quantum of clock cycles, it notifies the simulation kernel thread of the time at which the breakpoint is hit such that the other simulations can execute up to that point in time rather than the entire quantum.
  • the processor core simulation when the processor core simulation hits the breakpoint, it breaks from its run-ahead loop and tells the control mechanism to break at time 'T," where 'T' is the point where the breakpoint occurs (arrow 425).
  • the processor core simulation then waits until it is notified by the simulation kernel thread that the other simulations have caught up.
  • the simulation kernel thread will schedule other simulations (e.g., other processor core simulations, hardware simulation) for execution, which allows them to synchronize (e.g., catch up) with the core processor simulation that hit the breakpoint.
  • the control mechanism may subscribe to a time advance callback of the simulation kernel thread (arrow 430) so that it is the first to be notified when time "T' is reached.
  • time 'T time advance callback
  • the simulation kernel thread notifies the control mechanism (arrow 435), which then unsubscribes from the time advance notification (arrow 440) and "waits on the control mechanism" to suspend the simulation kernel thread (arrow 445).
  • the debugger platform still has complete visibility of all the simulations through the debug support thread.
  • the user inputs a command into the platform debugger (arrow 450).
  • the platform debugger sends a message to the debug support thread to initiate re-start of the simulation (arrow 455).
  • the debug support thread signals the control mechanism to re-start the simulation kernel thread (arrow 460).
  • the simulation kernel responds to the control mechanism by re-starting execution of all simulations (arrow 465).
  • a user may also wish to break at a certain simulation time (or have complex breakpoint conditions that involve time). This can be implemented very similar to a breakpoint depicted in Figure 4.
  • an event is scheduled in the simulation at the time specified by the user. When this event is triggered by the simulation, it sends a message to the control mechanism passing the current time as a parameter (similar to arrow 425 in Rg. 4). Then steps similar to arrows 430, 435, and 440 of Figure 4 may be taken in order to help synchronize the simulations.
  • the control mechanism receives a callback from the simulation kernel (similar to arrow 435 of Fig.4) the simulation kernel thread will wait on the control mechanism (similar to arrow 445 of Fig. 4).
  • Watchpoints may be used to suspend the simulation when a hardware register is read or written, in embodiments of the present invention.
  • Figure 5 depicts a sequence diagram for implementing a watchpoint 500, in accordance with an embodiment of the present invention.
  • a user 268 inputs the desired watchpoint to the platform debugger (arrow 505).
  • the platform debugger sends a message to the debug support thread indicating the watchpoint (arrow 510).
  • the debug support thread invokes the interface converter to send messages to a processor core simulation and to the hardware simulation indicating the watchpoint (arrows 515, 520, and 525).
  • the watchpoint is an event (e.g., memory or register access) that the hardware simulation will detect.
  • the processor core is made aware of the watchpoint for purposes of synchronizing the halting of the simulations, which will be discussed herein below.
  • the processor core simulation runs "ahead of time.” If the processor core simulation model determines that it, is about to access a part of the hardware that has a watchpoint associated with it, the processor core simulation model will first synchronize with the other simulation models before doing the hardware access, effectively allowing them to "catch up.” Thus, the processor core simulation model may notify the control mechanism (arrow 530) and the simulation kernel (arrow 535) as if a breakpoint were hit. The simulation kernel may then schedule other simulation models to allow them to catch up to the processor core simulation model.
  • the processor core simulation model continues and executes the instruction that accesses the hardware simulation (arrow 440). If the hardware simulation detects that the watchpoint is hit, it notifies the simulation kernel of this fact (arrow 445). As soon as the hardware access is over, control is returned to the processor core simulation model, which asks the simulation kernel to process any watchpoint that have been hit by the previously executed instruction (arrow 450). If the simulation kernel determines the watchpoint was hit, it "waits on the control mechanism" to suspend the simulation kernel thread (arrows 455 and 460).
  • the user inputs a command into the platform debugger (arrow 465).
  • the platform debugger sends a message to the debug support thread to initiate re-start of the simulation (arrow 470).
  • the debug support thread signals the control mechanism (arrow 475).
  • the simulation kernel responds to the control mechanism by re-starting execution of all simulations (arrow 480).
  • Figure 6 illustrates circuitry of an exemplary computer system 100, which . may form a platform for embodiments of the present invention.
  • Computer system 100 may serve as a platform for the platform debugger (270, Fig. 2), the simulation process (210, Fig. 2), the simulation kernel (Fig. 7, 700; Fig. 10, 1000), or process 900 (Fig. 9).
  • the platform debugger and simulation process execute computer system 100. In other embodiments, they execute on separate computer systems.
  • Computer system 100 includes an address/data bus 99 for communicating information, a central processor 101 coupled with the bus for processing information and instructions, a volatile memory 102 (e.g., random access memory RAM) coupled with the bus 99 for storing information and instructions for the central processor 101 and a non-volatile memory 103 (e.g., read only memory ROM) coupled with the bus 99 for storing static information and instructions for the processor 101.
  • the instructions may include steps of process 300 of Figure 3 or process 900 of Figure 9.
  • Computer system 100 also includes an optional data storage device 104 (e.g., a magnetic or optical disk and disk drive) coupled with the bus 99 for storing information and instructions.
  • the simulation results may be stored optional data storage device 104 or volatile memory 102.
  • system 100 may also include an alphanumeric input device 106 including alphanumeric and function keys coupled to bus 99 for communicating information and command selections to central processor unit 101.
  • a user may input commands to the platform debugger via alphanumeric input device 106.
  • System 100 may also include a cursor control device 107 coupled to bus 99 for communicating user input information and command selections to central processor unit 101.
  • System 100 of the present embodiment may also include a display device 105 coupled to bus 99 for displaying information.
  • the platform debugger may be a graphical debugger capable of displaying data and graphics from the simulations.
  • the platform debugger executes on a device external to computer system 100.
  • Computer system 100 has a signal input/output communication device 108 coupled to bus 99 providing communication with external devices for this and other purposes.
  • FIG. 7 is a block diagram illustrating a simulation kernel in accordance with an embodiment of the present invention.
  • the same overall simulation comprising simulation models 720, 730, 740, 750, 760 can be dynamically tuned for more accuracy or for more speed.
  • the simulation results will be behaviorally correct even when the overall simulation is tuned for maximum speed.
  • the user selects a desired accuracy level and the simulation engine 710 can dynamically decide to temporarily increase accuracy to ensure behavioral correctness.
  • the simulation engine 710 should not simulate with less accuracy than requested by the user.
  • the simulation models 720, 730, 740, 750, 760 are capable of cycle accurate simulation, in one embodiment. However, the simulation models may be executed in a mode that is less than cycle accurate, while still achieving behaviorally correct simulation results. Embodiments of the present invention increase simulation speed without sacrificing accurate results by reducing the impact of simulation bottlenecks.
  • An example of a bottleneck in the simulation is the communication between one of the CPU simulations 720, 730 and the memory simulation 750.
  • Another example of a bottleneck is between one of the CPU simulations 720, 730 and one the hardware simulations 760, which may be modeling a peripheral component.
  • a bus simulation 740 may be invoked in a cycle-accurate simulation, which provides greater simulation accuracy but may reduce the simulation efficiency.
  • clock signals may be used to synchronize the different simulations (as may be done in the architecture being simulated).
  • a large portion of the work of the simulation engine 710 is to manage and schedule clock signals.
  • Embodiments of the present invention reduce the simulation engine's clock management workload by reducing the number of times that the simulations (e.g., 720, 730, 740, 750, 760) are synchronized.
  • embodiments of the present invention synchronize every "quantum" of execution units.
  • the "quantum” is a number of clock cycles in one embodiment. However, the quantum may be any convenient unit of execution.
  • Using a quantum allows a simulation to execute many clock cycles without having to stop to synchronize.
  • a CPU simulation model may execute dozens, hundreds, thousands or more instructions in a row, without having to stop to synchronize with the other simulation models.
  • the CPU simulation may not be dependent upon an event in another simulation for a substantial time period.
  • the CPU simulation result may be behaviorally accurate without synchronizing even though the CPU simulation is not cycle-accurate.
  • the simulations may be invoked by the simulation engine, wherein each simulation is allowed to execute up to the quantum of execution units (e.g., clock cycles) without stopping, for example, to synchronize with another simulation.
  • simulation 1 may execute its quantum (block 805), followed by simulation 2 (block 810), then the rest of the simulations may be invoked (blocks 815, 816, 817.
  • the simulations are synchronized (Simulation Time T1). It is not required that the simulations be executed one at a time.
  • the simulation models could execute in parallel on different processors of a multi-processor system. However, the simulation models are allowed to execute a quantum of instructions without the need to stop and synchronize with another simulation.
  • the simulation models have an internal clock that is shut off when the simulation is asleep to save the overhead of the clock running.
  • peripheral hardware may be modeled to be responsive or mostly responsive rather than autonomous.
  • the bus simulation model may also be written to be responsive. This , allows a processor simulation to execute very large numbers of instructions, while still providing a behaviorally accurate simulation.
  • the quantum may be dynamically adjusted so that a simulation does not run past an autonomous event scheduled in another simulation.
  • an autonomous event may be scheduled to occur in simulation 4 at a known time.
  • Simulation 4 informs the simulation engine of this autonomous event and its simulation time at some convenient time prior to the autonomous event.
  • the simulation engine stores this and other simulation events (Fig. 10, 1020).
  • the simulation engine dynamically adjusts the quantum such that other simulations do not run past this autonomous event.
  • the autonomous event may be an event scheduled to take place in a hardware simulation.
  • An embodiment of the present invention typically schedules a processor simulation prior to memory and hardware simulations.
  • the quantum is reduced in size prior to the processor simulation being invoked. If the frequency of events in memory, bus, or hardware simulations is too high, the quantum can be negatively impacted.
  • embodiments of the present invention provide for techniques to reduce the impact of such events, wherein the quantum is not impacted by certain classes of events. These events are not necessarily autonomous events.
  • each simulation executes for quantum 1.
  • Simulation 4 has an event scheduled at simulation time T2. Therefore, quantum 2 is reduced to end at simulation time T2. The reduction is done prior to simulation 1 being invoked to execute its block 820, such that all simulations execute for the reduced quantum and do not run past the autonomous event.
  • simulation 2 is then invoked to execute (block 821). Simulations 3-5 may then be invoked.
  • the size of the quantum may be based on a value input by the user. Typically, the quantum should be given the highest possible value that still gives a behaviorally correct simulation result. Thus, since there are no autonomous events scheduled between synchronization times T2 and T3, the quantum is increased back to it maximum possible value (quantum 3). The simulation engine should not increase the quantum to a value larger than the user-specified value.
  • a simulation is able to determine that it should halt prior to completion of its maximum quantum of execution units based on either an event in its simulation or one that it may trigger in another simulation model.
  • the quantum is "quantum 1" (ending at simulation time T2) and no known dependencies exist that would indicate the quantum should be shortened.
  • simulation 1 stops its execution partway through its quantum of execution units (block 872). This may occur because simulation 1 determined that it has a dependency on another simulation at simulation time T1 such that it cannot continue behaviorally accurate simulation. Alternatively, simulation 1 may have hit a breakpoint or watchpoint. Or simulation 1 may determine that it may cause an event in another simulation.
  • simulation 1 may determine that by writing to a register in another simulation it may cause a watchpoint in that other simulation to be hit. Simulation 1 will inform the simulation engine of the stopping point (T1) when returning control to the simulation engine.
  • the singulation engine then dynamically adjusts the quantum to "quantum 2" so that the rest of the simulations stay synchronized with simulation 1.
  • the simulation engine then invokes simulations 2-4 to execute up to the quantum, which has been dynamically modified to "quantum 2.”
  • the simulation engine may invoke simulations 1 -4 to execute to simulation time T3 by dynamically modifying the quantum to "quantum 3.”
  • the simulation engine then dynamically adjusts the quantum to "quantum 2" so that the rest of the simulations stay synchronized with simulation 2.
  • the simulation engine then invokes simulations 3-5 to execute up to the quantum, which has been dynamically modified to "quantum 2.”
  • Simulations 2-5 will be synchronized at simulation time T4. It is not required that simulation 1 be synchronized with the rest of the simulations at this point. If a user views simulation results at this point, the user will be informed that simulation 1 has "run ahead of time” and is stopped at simulation time T5.
  • the simulation engine may invoke simulations 2-5 to execute to simulation time T5 by dynamically modifying the quantum to "quantum 3.” Then, the quantum may be re-set to a higher value for more efficient simulations (quantum 4), wherein simulations 1-5 are invoked and allowed to execute up to simulation time T6 without any of the simulation models stopping to synchronize with another simulation model.
  • FIG. 9 is a flowchart illustrating steps of a computer-implemented process 900 of performing a simulation of a computer system platform, in accordance with the present invention.
  • a simulation engine accesses an initial value for a quantum.
  • the initial value is typically received from a user and is typically a maximum value that the quantum can ever be in the simulation.
  • the quantum is dynamically adjustable, wherein the current value of the quantum specifies a maximum number of units of execution a simulation is allowed to perform.
  • the user may change the quantum during the execution of the simulation, without having to recompile the simulation. Therefore, the user may adjust the dynamic quantum to select between a between a cycle accurate simulation mode and a behaviorally accurate simulation mode.
  • Step 920 comprises the simulation engine invoking a first simulation for execution and informing the simulation of the current value of the quantum.
  • the simulation is aware of the maximum number of units of execution it is allowed to perform.
  • the simulation is not required to complete all of the execution units. For example, if the simulation identifies a dependency on another simulation in step 930, it halts in step 940. Moreover, in step 940 the simulation notifies the simulation engine of the time at which it halted. Thus, in step 950, the simulation engine modifies the dynamic quantum. Then, the process 900 returns to step 920 wherein the simulation engine invokes the next simulation, providing it with the current value of the dynamic quantum.
  • a simulation will complete the entire quantum of execution units. If the simulation is aware of an autonomous event in its simulation (step 955), it may inform the simulation of this in step 960. For example, a hardware simulation may inform the simulation engine that it has an upcoming autonomous event so that it will be awoken to simulate the autonomous event. Moreover, the simulation engine may modify the quantum to prevent other simulations from running ahead of this autonomous event. The simulation engine keeps track of this and other autonomous events, such that it may modify the dynamic quantum at the appropriate time.
  • step 970 the simulation completes and returns control to the simulation engine.
  • the process 900 then returns to step 920, wherein the simulation engine invokes the next simulation model.
  • simulation modes may be described as functional models, which simulate the function of the hardware instead of the actual hardware implementation.
  • the hardware simulation model normally "sleeps” and is “woken up” by incoming communication.
  • the hardware simulation model then executes the needed behavior and goes to "sleep” again. If a hardware simulation model needs to execute behavior in the future, it asks the simulation engine to wake it up again at that time in the future and goes to "sleep” again.
  • the vast majority of hardware e.g., peripherals
  • busses and memory can be modeled in this functional fashion, as well.
  • Another embodiment of the present invention provides for bypassing invocation of a simulation model to bypass a non-autonomous simulation event when behavior of the non-autonomous simulation event is not desired.
  • backdoor memory accesses are used in order to improve simulation efficiency.
  • the backdoor memory access can bypass a simulation event that might impact the quantum.
  • the bypassed events may be non-autonomous events. For example, for every instruction that a real-world processor executes, there is at least one memory access, e.g., the opcode fetch. Thus, it is possible to simulate this by invoking the processor simulator and the memory simulator (along with the bus simulator). Invoking the simulators in this fashion could cause the dynamic quantum to be very low, typically two or three clock cycles.
  • a memory simulation model 750 may allocate a large array 1010 of bytes to model the memory. When a communication request comes into the memory simulation model 750, the memory simulation indexes into the array and returns the proper value.
  • an embodiment of the present invention performs a "backdoor access," in which the memory simulation 750 is not invoked.
  • the processor simulation 720 uses a pointer to index the memory array 1010.
  • the simulation engine has pointer storage 1005 and receives pointers from the memory model 750, and possibly other simulation models. Neither the bus simulation 740 nor the memory simulation model 750 need be invoked. Therefore, the quantum is not impacted by this event. The user may be allowed to specify whether such backdoor accesses are permitted or not.
  • Backdoor memory accesses may reduce the accuracy of the simulation.
  • One reason for reduced accuracy is that a backdoor access may take zero simulation time.
  • a real CPU to memory access over the bus would require several clock cycles.
  • an embodiment of the present invention allows a user to estimate the number of clock cycles that a backdoor access would take and input this as a simulation parameter. More than one estimate can be provided, based on the type and/or sequence of accesses (e.g., read, write, write followed by read, etc.)
  • the processor simulation 720 factors in the estimated access time when it determines the number of instructions it can execute within its quantum. Thus, the potential loss of simulation accuracy is reduced or eliminated by factoring in the estimate.
  • Backdoor accesses may apply to other than instruction fetches.
  • the processor simulation model understands when it is safe to perform a backdoor access. That is, the processor simulation model understands when a behavior that should be simulated is associated with the memory access. If there is such a behavior, then the processor simulator does not perform a backdoor memory ' access.
  • a backdoor access can apply to other than a memory simulation. This allows a more efficient simulation for pieces of hardware that may be frequently accessed.
  • the hardware simulation may also provide one or more pointers to the simulation engine.
  • the backdoor access does not use the bus simulation model or the memory (or hardware) simulation model. In this case, the backdoor access . does not trigger the behavior associated with the memory (or hardware) access. In another embodiment, the backdoor access does not use the bus simulation model but does invoke the memory (or hardware) simulation model. In this case, the backdoor access does trigger the behavior associated with the memory (or hardware) access.
  • the user is allowed to select backdoor accesses "on the fly.”
  • a graphical user interface such as a debugging tool, allows the user to specify which simulations may perform backdoor accesses.
  • the user may be allowed to specify under what conditions backdoor accesses are allowed.
  • a user may specify that backdoor accesses are allowed for only instruction fetches.
  • embodiments of the present invention allow selection of backdoor access on a per component basis within a given simulation model.
  • the backdoor access may be specified on a register-by-register basis. The user can modify any of the backdoor access parameters without the need to re-compile the simulation.
  • the software developer may avoid using an interrupt by exploiting the fact that it is known which software is running on both CPU's. For example, if it is known that CPU1 will put a new element in the shared memory every 20 clock cycles, then that knowledge can be exploited in CPU2. If CPU1 is aware that CPU2 exploits that knowledge, then CPU1 can know when it is safe to overwrite the shared memory based on the shared timing knowledge, rather than using an interrupt. [0089] However, the simulation models may be unaware of this timing knowledge. For example, if an interrupt is used, the simulation may have explicit information regarding the interrupt. However, if the aforementioned timing knowledge is used instead of interrupts, the simulation may not contain explicit information about the timing of the shared memory accesses. An embodiment of the present invention prevents possible incorrect simulation results that may occur due to such dependencies that are not explicitly indicated in the simulations.
  • the software developer may program CPU1 to write to shared memory every 20 clock cycles and CPU2 to read the shared memory every 20 clock cycles. However, this timing * information may not be explicitly obtainable from the simulations. If the quantum were set to 100 clock cycles, CPU1 could overwrite the shared memory before CPU2 would read the shared memory (or vice versa). Thus, the simulation results will likely be incorrect.
  • An embodiment of the present invention allows the user to set a maximum value of the quantum. The simulation engine may only dynamically reduce the quantum, in this embodiment. In this case, the quantum might be limited by the user to 20 clock cycles (e.g., the resolution of timing based communication between both CPUs).
  • each autonomous simulation model may have its own quantum.
  • the dynamic quantum may be adapted to a specific simulation, or it may be individually adapted to a plurality of autonomous simulations.
  • Simulation models that are wholly or largely responsive may have their quantum set to the lowest quantum in current use.

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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
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Abstract

L'invention permet d'avoir une vue unifiée de simulations de systèmes de plusieurs ordinateurs, et sur un processus de simulation comportant: une filière de simulation exécutant plusieurs simulations de systèmes d'ordinateurs; ainsi qu'une filière d'assistance au débogage fournissant une vue unifiée des simulations. Pour fournir cette vue unifiée, la filière utilise une interface externe et une interface interne pour chacune des simulations et une interface effectuant des conversions entre l'interface externe et l'interface interne. L'interface externe fournit ainsi une vue unifiée des simulations. Tout en permettant à une seule plate-forme de débogage de gérer et observer les situations.
PCT/US2006/006541 2005-02-25 2006-02-22 Interface de conversion permettant une vue unifiee de simulations de systemes de plusieurs ordinateurs WO2006091785A1 (fr)

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US11/066,841 2005-02-25
US11/066,945 US7742905B2 (en) 2005-02-25 2005-02-25 Method and system for dynamically adjusting speed versus accuracy of computer platform simulation
US11/066,945 2005-02-25
US11/066,841 US7716031B2 (en) 2005-02-25 2005-02-25 Interface converter for unified view of multiple computer system simulations

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