WO2006090328A3 - Multiprocessor system, testing device and method for generating cache coherence testing traffic - Google Patents

Multiprocessor system, testing device and method for generating cache coherence testing traffic Download PDF

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Publication number
WO2006090328A3
WO2006090328A3 PCT/IB2006/050555 IB2006050555W WO2006090328A3 WO 2006090328 A3 WO2006090328 A3 WO 2006090328A3 IB 2006050555 W IB2006050555 W IB 2006050555W WO 2006090328 A3 WO2006090328 A3 WO 2006090328A3
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WO
WIPO (PCT)
Prior art keywords
cache coherence
testing
testing device
traffic
interconnecting means
Prior art date
Application number
PCT/IB2006/050555
Other languages
French (fr)
Other versions
WO2006090328A2 (en
Inventor
Nageswaran Jayram Moorkanikara
Sainath Karlapalem
Andrei S Terechko
Original Assignee
Koninkl Philips Electronics Nv
Nageswaran Jayram Moorkanikara
Sainath Karlapalem
Andrei S Terechko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Nageswaran Jayram Moorkanikara, Sainath Karlapalem, Andrei S Terechko filed Critical Koninkl Philips Electronics Nv
Publication of WO2006090328A2 publication Critical patent/WO2006090328A2/en
Publication of WO2006090328A3 publication Critical patent/WO2006090328A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The present invention relates to a testing device and a method for generating cache coherence testing traffic within a data processing system. It further relates to the data processing system besides such a testing device comprising a plurality of processing units, at least one of which comprises an associated cache memory, a shared memory, and interconnecting means. The testing device is connectable to said interconnecting means and comprises a sensing means operable to retrieve cache coherence requests output by the interconnecting means, a memory operable to store addresses corresponding to said retrieved cache coherence requests, and a traffic generation means operable to output subsequent cache coherence requests based on the stored addresses to the interconnecting means.
PCT/IB2006/050555 2005-02-28 2006-02-21 Multiprocessor system, testing device and method for generating cache coherence testing traffic WO2006090328A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05101499.1 2005-02-28
EP05101499 2005-02-28

Publications (2)

Publication Number Publication Date
WO2006090328A2 WO2006090328A2 (en) 2006-08-31
WO2006090328A3 true WO2006090328A3 (en) 2007-01-04

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Family Applications (1)

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PCT/IB2006/050555 WO2006090328A2 (en) 2005-02-28 2006-02-21 Multiprocessor system, testing device and method for generating cache coherence testing traffic

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WO (1) WO2006090328A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7405773B2 (en) 2018-06-01 2023-12-26 シー－スカイ マイクロシステムズ カンパニー，リミテッド How to verify access to level 2 cache on a multi-core interconnect

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101821717A (en) * 2007-10-18 2010-09-01 Nxp股份有限公司 Circuit and method with cache coherence stress control
US8250311B2 (en) 2008-07-07 2012-08-21 Intel Corporation Satisfying memory ordering requirements between partial reads and non-snoop accesses

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960457A (en) * 1997-05-01 1999-09-28 Advanced Micro Devices, Inc. Cache coherency test system and methodology for testing cache operation in the presence of an external snoop
US20050027897A1 (en) * 2003-07-11 2005-02-03 Fellenser Frederick George Maintenance interface unit for servicing multiprocessor systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960457A (en) * 1997-05-01 1999-09-28 Advanced Micro Devices, Inc. Cache coherency test system and methodology for testing cache operation in the presence of an external snoop
US20050027897A1 (en) * 2003-07-11 2005-02-03 Fellenser Frederick George Maintenance interface unit for servicing multiprocessor systems

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
O'KRAFKA B ET AL: "MPTG: a portable test generator for cache-coherent multiprocessors", COMPUTERS AND COMMUNICATIONS, 1995., CONFERENCE PROCEEDINGS OF THE 1995 IEEE FOURTEENTH ANNUAL INTERNATIONAL PHOENIX CONFERENCE ON SCOTTSDALE, AZ, USA 28-31 MARCH 1995, NEW YORK, NY, USA,IEEE, US, 28 March 1995 (1995-03-28), pages 38 - 44, XP010149410, ISBN: 0-7803-2492-7 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7405773B2 (en) 2018-06-01 2023-12-26 シー－スカイ マイクロシステムズ カンパニー，リミテッド How to verify access to level 2 cache on a multi-core interconnect

Also Published As

Publication number Publication date
WO2006090328A2 (en) 2006-08-31

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