WO2006087507A1

WO2006087507A1 - Digital audio broadcast receiver

Info

Publication number: WO2006087507A1
Application number: PCT/GB2005/050152
Authority: WO
Inventors: Sencan Tuncer; Gwilym Francis Luff; Clive Roland Taylor
Original assignee: Frontier Silicon Limited
Priority date: 2004-09-20
Filing date: 2005-09-12
Publication date: 2006-08-24
Also published as: GB2433658A; GB2433658A8; GB0707576D0

Abstract

This invention relates to a phase locked loop circuit which is particularly suitable for digital audio broadcast (DAB) receiver. A phase locked loop (PLL)(128) for providing a phase locked output signal from a reference signal comprises an input to receive said reference signal; a variable frequency oscillator (132), said oscillator being operable in a selected one of a plurality of frequency bands and having a frequency control input (tune I/P) for controlling a frequency of the oscillator, and a band select input for a band select signal for selecting a said frequency band, and an output for providing said phase locked output signal; and a phase detection system (138), said phase detection system having a first input coupled to said reference signal input, a second input to receive a signal derived from said oscillator output, and an output (139) for providing a frequency control signal to said frequency control input of said oscillator; and wherein said PLL is further configured to adjust a gain of said phase detection system (138) responsive to at least one of said frequency control signal and said band select signal.

Description

PHASE LOCKED LOOP AND METHOD OD CONTROLLING A PHASE LOOCKED LOOP

This invention relates to improved circuits and architectures for digital audio broadcast (DAB) receivers, in particular multiband DAB receivers. We will describe an improved phase locked loop (PLL) circuit that is particularly suitable for use in a frequency synthesiser for such a receiver.

Background information on digital audio broadcast service standards can be found in the EUREKA-147 standard (ETSI Document EN300 401 Vl .3.3 (2001-5); reference may also be made to BS EN 50248.2001. Digital audio broadcast services are currently provided in two frequency bands, 174 - 240 MHz (Band 3 in the UIC) and 1452 - 1492 MHz (L Band) for the rest of the world; it is also useful for a DAB receiver to be capable of receiving conventional FM (Frequency Modulation) broadcasts, in the UK at 88 - 108MHz.

It is desirable to be able to provide a radio receiver circuit which is usable in both the present DAB frequency bands and preferably also for receiving conventional FM broadcasts. Preferably such a radio receiver circuit would be suitable for single chip integration so that a single integrated circuit may be provided for constructing a receiver for use with any of the presently envisaged DAB broadcast standards. In order to achieve this it is desirable to be able to provide a multiple band, tunable DAB receiver which operates over a wide frequency range.

A particular problem which arises in this context is that of providing a suitable local oscillator frequency synthesiser for mixing the received signal down to a first IF (intermediate frequency) of the receiver, because such a frequency synthesiser must be operable over a wide range of references. It would be advantageous to be able to employ a single voltage controlled oscillator (VCO) for such a frequency synthesiser. Generally such a frequency synthesiser is realised using phase locked loop techniques but to cover the desired frequency ranges requires a VCO with a very wide tuning range. This introduces particular difficulties when such a VCO is incorporated into a phase locked look since because of the wide range of the VCO the VCO sensitivity (that is change in output frequency for a given change in control voltage) tends to vary significantly across its frequency range. This, in turn, will change the PLL loop gain, leading to variations in lock time, phase noise, stability and reference-energy suppression performance. One possible solution to this problem is to employ a VCO with multiple, selectable frequency bands, but it has been found in practice that with such an arrangement the VCO sensitivity can also vary significantly with the selected band.

There therefore exists a need for improved phase locked loop techniques suitable for wide band operation and, preferably, on-chip integration with a single voltage controlled oscillator. It is known from US 6,624,674 to adjust a PLL loop filter resistance to reduce variations in the PLL damping factor as the frequency of the PLL changes. It is also known to alter pump current magnitude based upon division factors in a PLL incorporating a phase/frequency detector with a charge pump, as described in US 5,339,050. Again in a PLL incorporating a charge pump it is known to select from a small number of specific pump current values to provide a high current (high loop gain) to acquire lock and reduced current (reduced loop gain) to maintain lock. However none of these prior art techniques solve the aforementioned problems of loop gain variation with VCO tuning voltage and VCO band selection in a multi-band VCO used for facilitating the provision of a wide range of output frequencies.

According to a first aspect of the present invention there is therefore provided a phase locked loop (PLL) for providing a phase locked output signal from a reference signal, said PLL comprising: an input to receive said reference signal; a variable frequency oscillator, said oscillator being operable in a selected one of a plurality of frequency bands and having a frequency control input for controlling a frequency of the oscillator, and a band select input for a band select signal for selecting a said frequency band, and an output for providing said phase locked output signal; and a phase detection system, said phase detection system having a first input coupled to said reference signal input, a second input to receive a signal derived from said oscillator output, and an output for providing a frequency control signal to said frequency control input of said oscillator; and wherein said PLL is further configured to adjust a gain of said phase detection system responsive to at least one of said frequency control signal and said band select signal.

In preferred embodiments the phase detection system gain is responsive to both the frequency control and band select signals. The gain of the phase detection system may be altered by including a controllable gain/attenuation element within the phase locked loop, but preferably a phase detection system incorporating a charge pump is employed and the pump current is adjusted in response to the frequency control and/or band select signals.

In preferred embodiments the phase detection system comprises a phase (and frequency) detector which provides "up" and "down" frequency adjust output signals to the charge pump, which employs the signals to select one or other of a current source and current sink for providing the pump current output. It will therefore be recognised that this pump current output may be either positive or negative.

To adjust the loop gain the current sourced (or sinked) by the charge pump can be adjusted by controlling a respective constant current generator with a current control input. To control the charge pump current in accordance with the selected frequency band of the variable frequency oscillator a similar system can be employed, but preferably a plurality of constant current generators (each comprising a current source and current sink pair) is provided so that one or more of these may be selected responsive to the oscillator band select signal. Conveniently a set of binary weighted constant current generators is provided so that combinations of these may be selected by a binary oscillator band select signal.

The above described phase locked loop can be incorporated into a frequency synthesiser, and preferably the circuit is integrated, together with the variable frequency oscillator, on a single chip. In a related aspect the invention provides a charge pump circuit for a phase locked loop, said phase locked loop including a adjustable frequency oscillator responsive to a frequency adjust signal, said charge pump circuit comprising a substantially constant current generator to provide a charge pump current output; and wherein said substantially constant current generator has a current adjust input for adjusting said charge pump output current, said current adjust input being configured to receive said frequency adjust signal for adjusting said charge pump output current responsive to a frequency adjustment to said oscillator.

As previously mentioned the constant current generator may comprise a pair of adjustable current generators (a current source and a current sink) and/or a plurality of a constant current generators providing different, preferably binary weighted, currents for selection either singularly or in combination in accordance with a selected frequency band of the adjustable frequency oscillator. Preferably the charge pump circuit incorporates feedback from the charge pump output to the current adjust input, to control the charge pump response (and hence the sensitivity of a phase detection system into which it is incorporated) in accordance with the frequency adjust signal (normally a VCO control voltage).

In a corresponding aspect the invention provides a method of controlling a phase locked loop, said phase locked loop comprising an adjustable frequency oscillator and a phase detection system to compare an output of said adjustable frequency oscillator with a reference frequency input and to provide a frequency adjust signal for adjusting said adjustable frequency oscillator responsive to said comparing, a degree of said adjusting being dependent upon a loop gain of said phase locked loop, the method comprising: adjusting said loop gain of said phase locked loop responsive to said frequency adjust signal for said adjustable frequency oscillator.

In a further related aspect the invention provides a phase locked loop (PLL) circuit, the circuit comprising an adjustable frequency oscillator and a phase detection system to compare an output of said adjustable frequency oscillator with a reference frequency input and to provide a frequency adjust signal for adjusting said adjustable frequency oscillator responsive to said comparing, a degree of said adjusting being dependent upon a loop gain of said phase locked loop, and wherein said PLL circuit further comprises a loop gain adjust device to adjust said loop gain of said phase locked loop responsive to said frequency adjust signal for said adjustable frequency oscillator.

These and other aspects of the present invention will now be further described, by way of example only, with reference to the accompanying figures in which:

Figure 1 shows a block diagram of a DAB radio receiver circuit embodying aspects of the present invention;

Figure 2 shows a block diagram of a multi-band voltage controlled oscillator for use in preferred embodiments of the present invention;

Figures 3a and 3b show curves of capacitance against bias voltage for, respectively, a junction varactor, and a MOS varactor;

Figure 4 shows a set of curves of VCO sensitivity (Kvco) against output frequency of the VCO for the VCO of figure 2 when operating in each of its eight frequency bands;

Figures 5a and 5b show, respectively, a block diagram of a divide-by-N phase locked loop (PLL), and linearised model of the PLL of figure 5a;

Figure 6 shows an example of a phase locked loop circuit according to an embodiment of the present invention;

Figure 7 shows an example of a phase detection system incorporating a charge pump according to an embodiment of the present invention;

Figure 8 shows a second example of a phase detection system incorporating a charge pump according to a second embodiment of the present invention; and Figure 9 shows a block diagram of a complete DAB receiver 900 incorporating the radio receiver circuit of Figure 1.

Referring first to figure 1, this shows a block diagram of a radio receiver circuit, up to an IF output stage (IFOUT). This will generally be followed by analogue-to-digital converter (ADC) and digital signal processing (not shown) for final conversion down to base band and demodulation. In the receiver 100 of figure 1 the circuitry enclosed by solid line 102 is preferably provided on an integrated circuit.

The signal paths begin with off-chip band select filters 104a, b, c, for DAB signals in Band 3 and L-band and FM broadcast signals in Band 2; these may receive their inputs from a single, shared antenna, or from multiple antennas (not shown). These band select filters provide an input 108 into an on-chip variable gain low noise amplifier (LNA) 110; typically band selection information from base band processing circuitry determines which RF input is selected by multiplexer 106 for input into this amplifier. The output of LNA 110 is provided to an RF AGC circuit 112, and also to a quadrature down conversion mixer 114a, b, followed by a polyphase filter 116. Receiver 100 operates as a near zero IF receiver and thus the DAB input signal (which has a bandwidth of approximately 1.536MHz) is down converted to a first IF frequency of 1.024MHz; as described in more detail in the applicant's related UK patent application No. ... filed on the same day as this application. A preferred IF frequency plan employs down conversion to a first IF frequency followed by up conversion to a second higher IF frequency, and this is implemented by local oscillator 118 and second quadrature mixers 120, which are followed by low pass filter 122 and variable gain output buffer 124 which provides a differential output (IFOUT) 126. Although not shown as such, for clarity, preferably all the signal paths in integrated circuit 102 are differential, including RF, local oscillator, and EF signals.

A frequency plan for the receiver of figure 1 is shown in table 1 below. This frequency plan demonstrates high-side injection of the first LO (that is, with the local oscillator frequency greater than that of the target RF signal, f_Lo = fβp + fiiO- Low side injection (with the local oscillator frequency less than that of the target RF signal, f_to = f_RF - fjp) is also possible with this architecture. Frequency plan for DAB and FM modes of operation

RF input DAB: 170 - 240 MHz or 1452 - 1492 MHz FM: 8S-IOSMHz,

First local oscillator frequency DAB: RF frequency + 1.024 MHz FM: RF frequency+150 ItHz

First EF frequency DAB: 1.024 MHz; FM: 150IcHz

Second local oscillator frequency DAB: 1.024 MHz; FM: 2.048 MHz

Second IF frequency DAB: 2.048 MHz; FM: 2.198MHz

Table 1

From table 1 it can be seen that the first local oscillator frequency must be controlled over a wide range. In the receiver 100 of figure 1 this first local oscillator is implemented by the circuitry within dashed line 128, this providing a quadrature output 130a, b to respective quadrature down conversion mixers 114a, b. This first oscillator circuit, which embodies aspects of the present invention, is described further below. However, to facilitate understanding of the invention, operation of the receiver of figure 1 will first be briefly outlined.

As previously described, the EF after downconversion is 1.024MHz for the DAB inputs (Band 3, L-Band); I is 150ICHz for the FM input (Band 2). After polyphase filtering the signal is υpconverted to 2.048MHz for DAB and 2.198MHz for FM, and an IF variable gain amplifier and output driver provides a differential ADC drive for a subsequent base-band IC (not shown in figure 1). A PLL with on-chip LC VCO and a post divider generates the first LO signal for all bands and this PLL, the second LO generation and the filter alignment are all referenced to the crystal reference frequency (of 16.384, 24.576 or 32.768MHz)

There are tliree LNA inputs, one for each frequency band. Each LNA has 4OdB of AGC control range, and a PIdB of -ISdBm. Without external AGC components the chip can meet the -25dBm high level input requirements for portable receivers; an off-chip PIN diode attenuator may be used to extend the input range to -15 or -10 dBm. The RF input filters may provide protection for ESD discharges to an external antenna. The IF filters combine the functions of channel selectivity, anti-alias filtering for the baseband ADC and quadrature combining for image rejection. The first IF filter is a four-pole bandpass filter centred at 1 ,024mHz, with 3dB bandwidth of 1.9MHz to 270IcHz. After the quadrature upconversion to the second EF, additional filtering is used to prevent aliasing. This is achieve with the second EF filter, which has an upper frequency of 2.048MHz and a bandwidth of 3.6MHz. A filter alignment circuit may be used to align the centre frequency and bandwidth of all EF filters to the crystal reference frequency. A calibration cycle may be run each time the PLL is re-programmed, or when the PLL or IF circuits are turned on. Periodically, say every half second, an on die temperature sensor may be employed to take a reading and update the filter tuning.

A first AGC loop controls the RF AGC amplifier and the (optional) external PIN diode attenuator to avoid overloading of the RF and IF circuits; this detects signal levels at the first mixer input and at the first IF filter output. The IF AGC amplifier provides the final gain at the second IF. This is preferably controlled by the baseband IC to give a constant input level to the ADC on the baseband chip.

In a preferred implementation the frequency synthesiser includes an integer-N PLL comprising a fully integrated VCO, prescaler, phase detector, charge pump, reference divider and reference prescaler; and the loop filter is external. The reference divider divides down an externally provided reference frequency to a comparison frequency of 256IcHz for all bands. The VCO output is divided by 2 for L-Band, or by 12, 14 or 16 for Band 3 and by 28 or 32 for Band 2. The quadrature output of this programmable divider feeds the quadrature downmixers. This results in a first IF frequency of 1.024MHz for all DAB bands (IF_DΛB). and 150KHz for Band 2 FM mode. The second LO of 1.024MHz (DAB mode) or 2.048MHz (FM mode) for the upconverter is divided down from the reference frequency. This results in a second EF frequency of 2.048MHz for DAB and 2.198MHz for FM mode. The PLL and post-divider provide a channel frequency resolution of 64 KHz for L-band and Band 3, and a 4 KHz resolution for fine tuning in Band 2.

Referring again to figure 1, the local oscillator frequency synthesiser 128 employs an integer-N phase locked loop comprising a voltage controlled oscillator 132 providing an output to a postscaler 134 providing the quadrature outputs 130a,b, and phase locked loop (PLL) divider 136 also coupled to the output of VCO 132 and providing an output to a phase detector 138 comprising a charge pump (not shown in figure 1). Phase detector 138 also receives an input from a crystal oscillator 140 via a reference divider 142 as follows the phase detector 138 provides a charged pump output 139 to an external PLL low pass loop filter 144, the output of which provides a VCO tuning voltage (frequency control signal) to the VCO 132. in preferred arrangements the reference divider divides down a reference frequency from crystal oscillator 140 (which uses an external crystal) to a comparison frequency of 256KHz for all the three bands. A PLL resolution of 0.5 counts allows the VCO to be tuned in 128ICHz steps.

Referring now to the programmable post-divider 134, table 2 below shows the first local oscillator frequencies which are employed to obtain the desired first IF frequencies for DAB and FM modes, with high-side injection (that is with the local oscillator frequency greater than that of the target RF signal).

Table 2

To produce these local oscillator (LO) frequencies using a single integrated VCO, the output frequency of VCO 132 is chosen to be at a higher frequency than the required LO frequencies, and programmable divider 134 reduces the VCO output frequency as needed. As previously described the quadrature output 130 of programmable divider 134 feeds the quadrature downmixers 114.

The output of VCO 132 is divided by 2 for L-band; by 12, 14 or 16 for Band 3; and by 28 or 32 for Band 2. Different division ratios for a single band are thus used to cover sections of the band, thus reducing the VCO tuning range requirements. In this way the VCO 132 need only run from 2.7GHz to 3.15GHz.

Table 3a below shows band breaks selected according to this plan to reduce frequency range requirements. The actual band edges are the band limits that can be achieved when the programmable divider settings are as given in Table 3b (below), with the VCO 132 running from 2.7GHz to 3.15GHz. Table 3b also shows the frequency limits of VCO 132 required to cover all the band breaks (where the LO frequency is achieved by dividing the frequency of VCO 132 with the programmable divider 134). With this plan the PLL and post-divider 134 provide a channel frequency resolution of 64 KHz for L- band and Band 3, and a 4 KHz resolution for fine tuning in Band 2.

Nominal Band Actual Band Edges Edges (MHz) (MHz)

Frequency Bands section lower upper lower upper

L Band 1 band 1452 1492 1348.976 1573.976

Band 3 breaks lower 174 194 167.726 195.851 (nominal) mid 194 224 191.8331 223.976 upper 224 240 223.976 261.476

Band 2 breaks lower 86 97 84.225 98.2875 (nominal) mid 97 108 96.27857 1 12.35

Table 3a

IF

Low IF -1.024 MHz DAB mode -0.15 MI-Iz FM Mode

VCO lower upper

VCO Frequency 2700 3150 MHz

l^sl LO frequency

VCO frequency (MHz) (MHz)

Operation Band Divider Channel Frequency mode section lower upper setting resolution lower upper

L band 1 band 2906.048 2986.048 2 64 kHz 1453.024 1493.024

Band 3 lower 2800.384 3120.384 16 8 kHz (64/8) 175.024 195.024 mid 2730.336 3150.336 14 9.14 kHz (64/7) 195.024 225.024 upper 2700.288 2892.288 12 10.67 kHz (64/6) 225.024 241.024

Band 2 lower 2756.8 3136.768 32 4 kHz (64/16) 86.15 98.024 mid 2720.2 3052,672 28 4.57 IcHz (64/14) 97.15 109.024

Table 3b

Again, the reference to negative low-IF frequencies implies high-side injection but, as previously mentioned, low-side injection (positive low-IF frequencies) can equally well be employed.

It is a design aim of the frequency synthesiser that the VCO 132 covers the frequency range of 2.7GHz to 3.15GHz under a range of temperature and supply voltage conditions, as well as component value variations. For this reason the actual VCO tuning range is chosen to be wider than 2.7 - 3.15GHz.

Figure 2 shows a preferred embodiment of VCO 132, Broadly speaking a symmetric VCO topology is employed, using a pair of cross-coupled MOS for bipolar transistors 146 with inductors 148 in their respective collector (or drain) circuits. Junction (or diode) varactors 150 are connected across inductors 148 to provide an adjustable capacitance controlled by a voltage on tuning voltage input 152. A set of MOS varactors shown inside dashed line 154 is also connected across inductors 148, in parallel with junction varactors 150, to provide band selection. Three pairs of MOS varactors are provided, each controlled by a respective band selection control voltage 156a, b, c, The capacitance presented by the MOS varactors 154 and the junction varactors 150, together with the fixed inductors 148 and fixed capacitors 158, determine the frequency of operation of VCO 132.

Figures 3a and 3b show circuit symbols and graphs of capacitance against bias voltage for a junction varactor and for an MOS varactor respectively. Referring to Figure 3 it can be seen that the MOS varactors 154 are characterized by a rapid change in capacitance with applied voltage, whereas the junction varactor 150 has a more gradual slope. The MOS varactors 154 are biased so that the band-switching control signals 156a-c can switch them between their Cmax and Cmin values. The MOS varactor areas are binary weighted, so three control signals cover eight (2³) frequency ranges. When all the control signals are low the MOS varactors 154 contribute their maximum capacitance. This allows the junction varactor 150 to cover the lowest frequency section of the desired 2.7-3.15GHz range. When all control signals are high the MOS varactors 154 are at their minimum capacitance setting (highest VCO frequency range).

Table 4 (below) shows typical frequency ranges (that is tuning ranges) at which the VCO operates, for a set of band-switching control signal levels. The combination of the tune voltage and the band-switching signals allow this VCO to cover 2.577GHz to 3.705GHz under typical conditions. This range is large enough to ensure that the VCO can tune between 2.7GHz and 3.15GHz under a wide range of operating conditions. The band-switching ranges preferably overlap to avoid dead zones, that is frequency ranges to which the VCO cannot tune.

Table 4

The large tuning range of the VCO, together with the band-switching, causes a large variation of the VCO sensitivity (Kvco)- Here Kvco is the change of the VCO frequency with the tune voltage (vtime); this varies with the band-switching state and with vtune. For a given band-switching state the sensitivity is higher for lower vtune levels, since the junction capacitance varies more rapidly at low bias voltages. For a given vtune, a lower band-switching state will have lower Kvco_> since the total capacitance in the resonator is higher, and a change in the junction varactor capacitance will therefore have less effect.

Figure 4 shows a set of curves of Kvco against frequency for the eight band-switching states. Referring to Figure 4, it can be seen that there is a general trend for the VCO sensitivity to increase as the band select control voltages are altered to move from a low frequency band (state O, curve 402) to a high frequency band (state 7, curve 404). Likewise, referring for example to curve 404, the lower end 406 of this curve corresponds to a tuning voltage of 2.5V whereas the upper end 408 of this curve corresponds to a tuning voltage of 0.2V, from which it can be seen that there is a significant change in VCO sensitivity with VCO tuning voltage. We will next describe techniques which can be employed to address drawbacks associated with this change in VCO sensitivity with selected VCO band, and also with VCO tuning. However it is first useful to briefly review phase lock loop operation.

Referring to figure 5a, this shows a block diagram of a typical integer-N phase locked loop 500. This comprises a phase detector 502 which receives a first input 502a from a reference frequency source and a second input 502b from a divided down output of the phase locked loop. The phase detector 502 provides an output to a loop filter 504, the output of the loop filter providing a control voltage 506 for VCO 508 which provides an output 510 for the phase locked loop circuit, and which also provides an input to a divide-by-N circuit 512 the output of which provides frequency divided input 502b to phase detector 502.

Figure 5b shows a linearised model 550 of the phase detector 500 of figure 5a in which, broadly speaking, like elements are indicated by like reference numerals.

In the model of figure 5b:

θ_reι(s) is the phase of the reference signal; θvco(s) is the phase of the VCO signal; θdi_v(s) is the phase of the divided VCO signal;

K₀ is the VCO sensitivity in radians/second/volt (K_o=2πKvco);

Kψ is the phase detector gain in volts/radian

F(s) is the loop filter transfer function;

N is the PLL divider ratio.

With this model, the transfer function relating θ_reι{s) and θvco(s) is: Further details of this and other PLL models can be found in, for example, Ulrich L. Rohde, David P. Newkirk; "RF/Microwave Circuit design for Wireless Applications", Wiley-Interscience, 2000, pp. 848-876.

From equation 1 it can be seen that the loop gain is dependent on the product of the phase detector gain, the VCO sensitivity and the loop filter transfer function. As previously explained, in the wide-range PLL circuit we describe the variation of the VCO sensitivity with tune voltage and band-switching state is high, and without additional measures this would cause changes in the loop gain. For a loop filter with a given bandwidth, changes in loop gain will lead to variations in lock time, phase noise, stability and reference- energy suppression performance, and it is therefore highly desirable to mitigate these effects.

Preferred embodiments of the techniques we employ to mitigate these effects use a phase detection system incorporating a charge pump, and it is therefore useful to review the operation of such a system.

As is well known to the skilled person, in such a system a phase (and frequency) detector generally comprises a sequential digital circuit which is treated by the edges of the divided down VCO frequency and reference frequency, the phase detector producing an "up" or a "down" output depending upon the relative timing of these edges. These outputs drive a charge pump which delivers a positive or negative (or zero) output current to the PLL loop filter. The loop filter generally comprises a low pass filter such as a series connected resistor and capacitor which converts the pump current to an analogue voltage for tuning the VCO.

Reluming now to Equation 1, the loop dynamics are a function of the product of Kvco and Kψ, and Kψ is proportional to charge pump output current. The inventor has recognised that the desired aim of making the PLL loop gain substantially constant can be achieved by varying the charge pump current with vtune and the band-switching state. Considering first Kvco_> for a given band-switching state, Kvco is approximately inversely proportional to the tune voltage and the charge pump cuiτent should therefore be substantially proportional to the tuning voltage. This can be achieved by feeding back the charge pump output to the input of the charge pump to adjust the pump current. This is schematically illustrated in Figure 6 (in which like elements to those of Figure 1 are shown by like reference numerals), in which phase detector and charge pump 138 has an input to sense vtune, as well as a 256KHz reference frequency input and an input from PLL divider 136.

Figure 7 shows the phase detector and charge pump 138 in more detail. This comprises a phase detector 150 along the lines described above and a charge pump 152 comprising a pair of adjustable constant current generators, a constant current source 154 and a constant current sink 156 driven by respective "up" and "down" signals from phase detector 150 to produce pulses of current as required. Each of current source 154 and current sink 156 has a respective current adjust input, and both these current adjust inputs receive a (scaled) input from an output 158 of the charge pump. In this way the charge pump output varies with output voltage.

In operation the phase-frequency detector 150 compares the PLL divider output to the reference divider output, and, depending on the phase difference, sends an "up" or "down" pulse to enable a selected one of the two current sources of the charge pump. The combined output of the charge pump is connected to the external loop filter (to convert the output current pulse to an output voltage). The voltage at the output is fed back to the current sources and changes their magnitudes, Icp_p and Icp_π.

Referring now to figure 8, this shows a preferred embodiment of charge pump 152 which incorporates adjustment of the charge pump current output with VCO band- switch state. In figure 8 like elements to those of figure 7 are indicated by like reference numerals and thus the charge pump incorporates a pair of current sources 154, 156 as before, with feedback from the charge pump output 158, but additionally a set of tliree further pairs of (adjustable) current sources 154a, b, c; 156a, b, c (also with feedback) is employed to compensate for changes in VCO sensitivity with the selected band. The current sources 154a-c and sinks 156a-c are selected by respective control units 160, 162, which in turn receive inputs from the band-switching control signals V], V₂ and V₃. The current sources/sinks 154a, b, c, 156a, b, c are binary weighted and combined according to the band switching state, together with current generators 154, 156. For the highest band-switching state only current generators 154, 156 contribute to the charge pump output, and the output current is increased, by employing more of the current generators, the lower the band-switching state, to compensate for the reduced VCO sensitivity.

Referring back to figure 6 the operation of the VCO band switching controller 170 will now be described. In preferred embodiments the band-switching controller 170 is implemented using a simple voltage comparator that senses vtune and compares it to upper and lower limits. If vtiine<vtime_mm for longer than a time t(j_ei_ay the band is switched to a lower state; if vtune>vtune_maχ for longer than time t_dci_sy. the band is switched to a higher state. The time t^_eiay is chosen to inhibit oscillation of the synthesizer between states and so that band-switching is not triggered by changes in vtune of short duration.

Figure 9 shows a block diagram of a complete DAB receiver 900 incorporating the radio receiver circuit of figure 1. In Figure 9 the IF output of the receiver circuit of figure 1 is provided to an analogue-to-digital converter 912 for digitisation and subsequent coded orthogonal frequency division multiplexed (COFDM) signal demodulation by COFDM demodulator block 914. The output of demodulator 914 is provided to a DAB protocol stack decoder 916, which in turn provides an MPEG datastream to MPEG audio decoder 918 which provides an audio output to stereo DAC 920 and audio amplifiers and speakers 922. A man machine interface (MMI) 924 interfaces with DAB protocol stack decoder 916 to provide a user keyboard 926 and display 928. These allow a user to interact with and control the receiver via the slave control processor and registers of receiver circuit 100,

Embodiments of the circuits and architectures have been described with particular reference to their application in the front end of a digital audio broadcast (DAB) radio receiver. However the skilled person will appreciate that applications of embodiments of the invention are not limited this and include digital radio broadcast receivers in general, for example DVB (digital video broadcast) and DMB (digital multimedia broadcast) receivers, as well as applications in other types of receiver and outside the field of receivers, for example in frequency synthesisers in general.

No doubt many other effective alternatives will occur to the skilled person and it will be understood that the invention is not limited to the described embodiments but encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims

CLAIMS:

1. A phase locked loop (PLL) for providing a phase locked output signal from a reference signal, said PLL comprising: an input to receive said reference signal; a variable frequency oscillator, said oscillator being operable in a selected one of a plurality of frequency bands and having a frequency control input for controlling a frequency of the oscillator, and a band select input for a band select signal for selecting a said frequency band, and an output for providing said phase locked output signal; and a phase detection system, said phase detection system having a first input coupled to said reference signal input, a second input to receive a signal derived from said oscillator output, and an output for providing a frequency control signal to said frequency control input of said oscillator; and wherein said PLL is further configured to adjust a gain of said phase detection system responsive to at least one of said frequency control signal and said band select signal.

2. A PLL as claimed in claim 1 wherein said phase detection system gain is responsive to both said frequency control signal and said band select signal.

3. A PLL as claimed in claim 1 or 2 wherein said phase detection system comprises a charge pump, wherein said phase detection system output comprises a charge pump current output, and wherein said PLL is configured to adjust said charge pump current output responsive to at least one of said frequency control signal and said band select signal.

4. A PLL as claimed in claim 3 wherein said charge pump comprises at least one controllable substantially constant current generator with a current control input, and wherein said phase detection system includes a feedback path from said phase detection system output to said current control input.

5. A PLL as claimed in claim 3 or 4 wherein said charge pump comprises a plurality of substantially constant current generators, wherein said charge pump has a current generator select input configured to receive said oscillator band select signal, and wherein said charge pump is configured to select at least one of said plurality of substantially constant current generators for providing said charge pump current output responsive to said oscillator band select signal.

6. A PLL as claimed in claim 5 wherein said plurality of substantially constant current generators are configured to provide a set of binary weighted currents, wherein said band select signal comprises a binary signal, and wherein said charge pump is configured to select a combination of said binary weighted currents from said current generators responsive to said binary band select signal.

7. A frequency synthesiser including the PLL of any one of claims 1 to 6.

8. A charge pump circuit for a phase locked loop, said phase locked loop including a adjustable frequency oscillator responsive to a frequency adjust signal, said charge pump circuit comprising a substantially constant current generator to provide a charge pump current output; and wherein said substantially constant current generator has a current adjust input for adjusting said charge pump output current, said current adjust input being configured to receive said frequency adjust signal for adjusting said charge pump output current responsive to a frequency adjustment to said oscillator.

9. A single integrated circuit incorporating the PLL, frequency synthesiser, or charge pump circuit of any preceding claim.

10. A method of controlling a phase locked loop, said phase locked loop comprising an adjustable frequency oscillator and a phase detection system to compare an output of said adjustable frequency oscillator with a reference frequency input and to provide a frequency adjust signal for adjusting said adjustable frequency oscillator responsive to said comparing, a degree of said adjusting being dependent upon a loop gain of said phase locked loop, the method comprising: adjusting said loop gain of said phase locked loop responsive to said frequency adjust signal for said adjustable frequency oscillator.

11. A method as claimed in claim 10 wherein said adjustable frequency oscillator comprises a voltage controlled oscillator (VCO), wherein said frequency adjust signal comprises a VCO tuning voltage, and wherein said gain adjusting comprises adjusting said loop gain responsive to said VCO tuning voltage.

12. A method as claimed in claim 10 or 11 wherein said adjustable frequency oscillator comprises a multi-band adjustable frequency oscillator, and wherein said gain adjusting comprises adjusting said loop gain responsive to a selected frequency band for said oscillator.

13. A method as claimed in claim 10, 11 or 12 wherein said phase detection system includes a charge pump, and wherein said loop gain adjusting comprises adjusting an output current of said charge pump.

14. A phase locked loop (PLL) circuit, the circuit comprising an adjustable frequency oscillator and a phase detection system to compare an output of said adjustable frequency oscillator with a reference frequency input and to provide a frequency adjust signal for adjusting said adjustable frequency oscillator responsive to said comparing, a degree of said adjusting being dependent upon a loop gain of said phase locked loop, and wherein said PLL circuit further comprises: a loop gain adjust device to adjust said loop gain of said phase locked loop responsive to said frequency adjust signal for said adjustable frequency oscillator.