WO2006082554A3 - Systeme de traitement de donnees comprenant une unite memoire cache - Google Patents

Systeme de traitement de donnees comprenant une unite memoire cache Download PDF

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Publication number
WO2006082554A3
WO2006082554A3 PCT/IB2006/050319 IB2006050319W WO2006082554A3 WO 2006082554 A3 WO2006082554 A3 WO 2006082554A3 IB 2006050319 W IB2006050319 W IB 2006050319W WO 2006082554 A3 WO2006082554 A3 WO 2006082554A3
Authority
WO
WIPO (PCT)
Prior art keywords
cache
sets
data processing
processing system
cache unit
Prior art date
Application number
PCT/IB2006/050319
Other languages
English (en)
Other versions
WO2006082554A2 (fr
Inventor
Eijndhoven Josephus T J Van
Paul Stravers
Anca M Molnos
Original Assignee
Koninkl Philips Electronics Nv
Eijndhoven Josephus T J Van
Paul Stravers
Anca M Molnos
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Eijndhoven Josephus T J Van, Paul Stravers, Anca M Molnos filed Critical Koninkl Philips Electronics Nv
Publication of WO2006082554A2 publication Critical patent/WO2006082554A2/fr
Publication of WO2006082554A3 publication Critical patent/WO2006082554A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

La présente invention se rapporte à un procédé de partitionnement de mémoires caches, qui est mis en oeuvre sur des ensembles de mémoires caches. Comme les mémoires caches comportent généralement de nombreux ensembles (plusieurs centaines par exemple), le partitionnement des ensembles peut fournir la granularité requise pour commander de nombreux objets individuels. Le problème des caches classiques réside dans le fait que les ensembles sont sélectionnés par adressage direct. Ladite sélection doit être unique et uniforme, faute de quoi les divers processus ne peuvent accéder aux données partagées des uns et des autres. La solution selon l'invention fait appel à une table de consultation qui peut contenir une fonction de sélection d'ensembles générique, qui est intégrée à proximité de la mémoire cache elle-même afin de fournir un mappage global unique partagé entre tous les processus et processeurs, et qui peut fonctionner à la vitesse de la mémoire cache elle-même.
PCT/IB2006/050319 2005-02-02 2006-01-30 Systeme de traitement de donnees comprenant une unite memoire cache WO2006082554A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP05100705.2 2005-02-02
EP05100705 2005-02-02
EP05104652.2 2005-05-31
EP05104652 2005-05-31

Publications (2)

Publication Number Publication Date
WO2006082554A2 WO2006082554A2 (fr) 2006-08-10
WO2006082554A3 true WO2006082554A3 (fr) 2006-10-12

Family

ID=36602455

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/050319 WO2006082554A2 (fr) 2005-02-02 2006-01-30 Systeme de traitement de donnees comprenant une unite memoire cache

Country Status (1)

Country Link
WO (1) WO2006082554A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8095736B2 (en) 2008-02-25 2012-01-10 Telefonaktiebolaget Lm Ericsson (Publ) Methods and systems for dynamic cache partitioning for distributed applications operating on multiprocessor architectures
US8543769B2 (en) 2009-07-27 2013-09-24 International Business Machines Corporation Fine grained cache allocation
US8745618B2 (en) * 2009-08-25 2014-06-03 International Business Machines Corporation Cache partitioning with a partition table to effect allocation of ways and rows of the cache to virtual machine in virtualized environments
CN102323909B (zh) * 2011-09-13 2014-03-19 北京北大众志微系统科技有限责任公司 实现使用大容量高速缓存的内存管理方法及装置
WO2023130316A1 (fr) * 2022-01-06 2023-07-13 中国科学院计算技术研究所 Procédé et système de division dynamique de cache prenant en compte aussi bien la qualité de service qu'un taux d'utilisation

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5584014A (en) * 1994-12-20 1996-12-10 Sun Microsystems, Inc. Apparatus and method to preserve data in a set associative memory device
US20020002657A1 (en) * 1997-01-30 2002-01-03 Sgs-Thomson Microelectronics Limited Cache system for concurrent processes
US20020174301A1 (en) * 2001-05-17 2002-11-21 Conway Patrick N. Method and system for logical partitioning of cache memory structures in a partitioned computer system
US6493800B1 (en) * 1999-03-31 2002-12-10 International Business Machines Corporation Method and system for dynamically partitioning a shared cache
US20030196041A1 (en) * 1997-01-30 2003-10-16 Stmicroelectronics Limited Cache system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5584014A (en) * 1994-12-20 1996-12-10 Sun Microsystems, Inc. Apparatus and method to preserve data in a set associative memory device
US20020002657A1 (en) * 1997-01-30 2002-01-03 Sgs-Thomson Microelectronics Limited Cache system for concurrent processes
US20030196041A1 (en) * 1997-01-30 2003-10-16 Stmicroelectronics Limited Cache system
US6493800B1 (en) * 1999-03-31 2002-12-10 International Business Machines Corporation Method and system for dynamically partitioning a shared cache
US20020174301A1 (en) * 2001-05-17 2002-11-21 Conway Patrick N. Method and system for logical partitioning of cache memory structures in a partitioned computer system

Also Published As

Publication number Publication date
WO2006082554A2 (fr) 2006-08-10

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