WO2006081094A2 - Microcontroleur deterministe - Google Patents

Microcontroleur deterministe Download PDF

Info

Publication number
WO2006081094A2
WO2006081094A2 PCT/US2006/001575 US2006001575W WO2006081094A2 WO 2006081094 A2 WO2006081094 A2 WO 2006081094A2 US 2006001575 W US2006001575 W US 2006001575W WO 2006081094 A2 WO2006081094 A2 WO 2006081094A2
Authority
WO
WIPO (PCT)
Prior art keywords
microcontroller
accordance
processor unit
central processor
context
Prior art date
Application number
PCT/US2006/001575
Other languages
English (en)
Other versions
WO2006081094A3 (fr
Inventor
Andrew David Alsup
Original Assignee
Innovasic, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/259,420 external-priority patent/US7516311B2/en
Priority claimed from US11/259,755 external-priority patent/US20060168421A1/en
Priority claimed from US11/258,822 external-priority patent/US7562207B2/en
Priority claimed from US11/259,741 external-priority patent/US20060168420A1/en
Application filed by Innovasic, Inc. filed Critical Innovasic, Inc.
Publication of WO2006081094A2 publication Critical patent/WO2006081094A2/fr
Publication of WO2006081094A3 publication Critical patent/WO2006081094A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers

Definitions

  • the present invention pertains to microcontrollers and microprocessors.
  • microcontrollers typically target the consumer and automotive markets and additionally sell the same microcontrollers to the industrial markets.
  • a wide variety of product families are offered, each of which offers multiple products differentiated with specific feature sets.
  • RTOS vendors provide support, keeping the RTOS updated with new capabilities and fixing bugs etc.
  • RTOS vendors provide methods for enabling real-time and safety-critical functions to be performed, the efficiency and determinism of these functions is impacted because the software developer has no direct control over code execution and must rely on the RTOS to manage multi-threaded context switches and interrupts.
  • Typical applications also require multi-threaded real time processing to handle various control and communications functions. These applications require a microprocessor to execute several hundreds of task switches per second and many concurrent threads. This places an enormous amount of overhead burden on the microprocessor and increases firmware development schedule and cost.
  • the RTOS grants each task a time slot on the microprocessor.
  • a running task, "X” sometimes needs to be suspended temporarily so that another task, "Y”, can be run for a time, after which task "X" is resumed.
  • This suspension function is referred to as context switching.
  • context switching is performed by the RTOS saving the context of the task in the processor's memory at a predefined location.
  • the context of a task denotes its state: all the information required to resume the task at the point where it was interrupted.
  • context includes the contents of the processor's registers, the data in the memory on which the task is operating, and information regarding the current state of execution of the task, such as the program counter.
  • Software context switching presents functional and operational limitations. Reconfigurable hardware requires special handling. Both the software states and also the hardware states of the same task must be represented consistently.
  • determinism In the context of the present invention, determinism pertains to time. A system that is "deterministic" is one in which every time a sequence of events is to occur, then the time that it takes to perform that sequence of events will always be the same or the variation in time will not be significant.
  • a microcontroller that includes "hardware contexts” and in which context management is provided as hardware in the microcontroller. This enables time critical and safety- critical functions to be coded and run directly in one or more "hardware contexts" without any RTOS involvement and, at the same time, allowing an RTOS to run in a separate hardware context with application software supporting the higher level functions.
  • a deterministic cached memory architecture is provided in a microprocessor that is purely deterministic in that every time a particular piece of code is executed, it will execute in the same period of time.
  • the loading of cache is under software control. Chunks of cache are allocated to specific blocks of code such as interrupt handlers and the highest rate tasks. In a simpler implementation, all cache is pre-allocated.
  • allocation of cache is primarily for instruction cache, allocation of cache may also be applied to data.
  • FIG. 1 is a block diagram of an embodiment of a microcontroller in accordance with the principles of the invention.
  • FIG. 2 illustrates a portion of the CPU of the microcontroller of FIG. 1 in greater detail;
  • FIG. 3 is illustrates a portion of the CPU of the microcontroller of FIG. 1 in greater detail
  • FIG. 4 illustrates the context manager portion of FIG. 1 in greater detail
  • FIG. 5 illustrates a context timer module
  • FIG. 6 illustrates a portion of the memory protection unit of FIG. 1 in greater detail
  • FIGS. 7 and 7 A illustrates the user programmable cache of FIG. 1 in greater detail
  • FIG. 8 illustrates the organization of a the cache SRAM module of FIG. 7
  • FIG. 9 illustrates the input and outputs of the cache programmable cache of
  • FIG. 7
  • FIG. 10 is a block diagram of a universal input/output controller of FIG. 1;
  • the present invention is directed to providing a microcontroller and a microprocessor that has the advantages of high-end machine but with less complexity, both in hardware and in software.
  • the microcontroller and microprocessor of the present invention are particularly advantageously utilized for application to embedded systems of the types involving control problems, where consistent execution times and latency are often more important than raw throughput.
  • a "deterministic microprocessor" is provided.
  • the deterministic microprocessor and microcontroller of the invention are designed to provide rapid interrupt response with minimal variation in response time and fixed execution time for any set of instructions.
  • the microprocessor of the present invention provides a deterministic response to asynchronous events, i.e., the response to external events occurs within a narrow window of time.
  • the microprocessor and microcontroller of the present invention provides short instruction execution times, with interrupts enabled via hardware contexts (software in other arrangements typically disables interrupts when working on certain shared structures), and limited overhead for storing registers and performing other related tasks before working on the interrupt.
  • One microcontroller in accordance with the principles of the invention is a real-time microcontroller in which critical timing parameters including context switching and interrupt latency are precisely predictable for real time tasks.
  • the architecture of a microcontroller in accordance with the present invention provides good throughput with high determinism.
  • a microcontroller in accordance with the invention provides: fast context switching; deterministic caching; and a deterministic memory protection unit.
  • multiple register banks are utilized to speed up a context switch, hi the architecture of the system of the invention a pointer is changed to the set associated with that event, i.e. a different set is utilized for each set of interrupt sources, software interrupt, etc.
  • the system of the invention provides space and time partitioning to guarantee that one part of the software running on a system can not cause problems in another, higher criticality, part of the system.
  • One deterministic feature is that every instruction in the deterministic architecture of the present invention takes a fixed period of time, regardless of its inputs. For example, in the microprocessor and microcontroller in accordance with the principles of the invention every shift takes the same period of time, regardless of the number of bit positions the shift is moving.
  • each universal I/O controller is configurable to support various communication protocols across multiple platforms.
  • Each I/O controller is a RISC engine which can be programmed to become any peripheral.
  • Microcode which configures each UIC into a desired peripheral is programmed by application code.
  • peripherals such as Ethernet, UART, HDLC, Smart GPIO, CAN and other Bus Interfaces.
  • the specific functionality for each universal I/O controller is selectable.
  • a first microcontroller in accordance with the invention may be configured to have 2 CANS and an Ethernet.
  • the same type of microcontroller maybe configured with 1 UART, 1 Ethernet, and an HDLC.
  • the present invention includes hardware support for firmware debug through a set of features that allows faster and less intrusive debug of embedded software.
  • FIG. 1 illustrates a deterministic microcontroller 1 comprising a microcontroller IA in accordance with the principles of the invention.
  • Every instruction in the deterministic architecture of the present invention takes a fixed period of time, regardless of its inputs.
  • every shift takes the same period of time, regardless of the number of bit positions the shift is moving.
  • a shift instruction takes a varying amount of time based on how much of a shift is being performed. For example, one prior microprocessor architecture takes 2 clock cycles for a single-bit shift, 3 clock cycles for a 2-bit shift, and so on up to 31 clock cycles for a 30-bit shift.
  • Another example of a deterministic feature of the invention is a multiply instruction, hi microcontroller 1 and microprocessor IA in accordance with the invention, multiply takes the same number of clocks regardless of operands.
  • Microcontroller 1 is formed as a single integrated circuit shown in FIG. V and includes a deterministic microprocessor or hardware kernel IA, programmable universal I/O controllers that are configurable to support various communication protocols across multiple platforms and a debug feature.
  • HARDWARE KERNEL HARDWARE KERNEL
  • Microcontroller 1 includes a 32 bit deterministic CPU 103, a context manager 105 that provides five hardware controlled independent contexts, a 32 kbyte user programmable cache 127, a user programmable memory protection unit 129, a priority resolver 109, DMA controller 113, interrupt control 111, system timers 107, and a debug engine 145, all of which are interconnected via an internal bus interface 119.
  • Microcontroller 1 provides the user with a microprocessor that: has extraordinary interrupt response (low latency) for a small number of sources; provides memory and throughput isolation of different contexts with little or no software overhead for context switching; and supports standard operating systems, tools, and libraries already in existence for the CPU32 family of parts.
  • Microcontroller 1 supports existing RTOS kernels within the hardware kernel. It provides a platform that can execute existing software along with support for the additional features we provide. Hardware kernel IA provides functionality that replaces parts of a traditional real time operating system (RTOS).
  • RTOS real time operating system
  • a context is an operating environment for a thread of software execution.
  • Each context includes user registers, i.e., data registers and address registers; a status register; a program counter; a system stack pointer; a vector base register; and other registers.
  • This set of registers is the register set that would be copied to memory when changing contexts on a typical microprocessor.
  • the present invention provides a plurality of sets of these registers as hardware 251.
  • microprocessor IA makes context switches that occur, for example, on an interrupt event, much faster and more dete ⁇ ninistically than a typical microprocessor.
  • a further advantage of providing a plurality of hardware contexts via plurality of sets of registers 251 is that tasks may be automated without software intervention.
  • the Memory Protection Unit 129 shown in FIG. 1 loads a new set of rules whenever contexts change.
  • the DMA 129 may be enabled or disabled on the CPU bus based on context priority.
  • microcontroller 1 has 5 hardware contexts as provided by the 5 sets of registers 251 shown in FIG. 2. However, it will be appreciated by those skilled in the art that more or less hardware contexts may be provided. One context is considered to be a master context. All other contexts are equal and subordinate.
  • the determination of which context is currently active is made in hardware.
  • Each context has two registers that enter into this determination: a context priority register and a context ready status register.
  • the hardware kernel selects for execution the context that currently has the highest priority and is ready to execute.
  • the Context Priority Register is a three-bit register that allows priorities from 0-7, with 7 being highest priority (to be compatible with standard interrupt priority on the CPU32 architecture).
  • the Context Ready Status Register has one of the following states: Halted — context will not execute until software has moved it to another state. Waiting ⁇ context is waiting to be made ready (e.g. by an interrupt) Ready -- context is ready to execute
  • Hardware kernel IA also includes a Current Context Register which indicates the context currently selected for execution, as well as the Previous Context Register which indicates which context was running previously (this is used by the master context when a fatal fault is detected in another context, allowing it to know which context caused the fault). [0056] Hardware kernel IA determines which context is currently ready and has the highest priority, if it is not the currently executing context then a context change is performed to bring it into execution.
  • Context ready status transitions are caused by: interrupts; fatal faults (e.g. a nested bus fault will halt the faulting context); STOP, LPSTOP, RESET, SLEEP, TRAPX; and context timeouts.
  • CPU 103 will stop fetching instructions and reduce power consumption until an event occurs to place a context in the ready state. If all contexts are in the halted state then the processor is effectively hung and will wait for an external reset.
  • Each hardware context consists of a corresponding one set of the following registers, identified collectively in the diagram of instruction execution unit 201 of FIG. 2 as registers 251:
  • Registers 251 includes 5 copies of this set of registers, corresponding to the 5 contexts in microcontroller 1. Hardware determines which of the contexts has the highest priority and is currently ready to run, then switches control to that context. [0061]
  • the MOVEM register flag register stores information to resume MOVEM instructions.
  • the MOVEM instruction includes a 16-bit word that indicates which of the 16 user registers (D0-D7, A0-A7) are to be load or written out. This word is saved as part of the context to allow the instruction to be interrupted.
  • Contexts have programmable priority with respect to each other.
  • a context priority register is used to program context priorities.
  • a context ready status register is provided for each context. While not actually a part of the context, i.e., it isn't swapped out as contexts are switched, all copies are always active, a copy of this register is provided for each context.
  • a Context Timer Register monitors execution time of the associated context. If that time exceeds the value in the Max time register then the context is halted and a fault generated to the master context.
  • the timer can also be placed in a mode to support a time-sliced execution mode in a given context.
  • a Context Mode Register determines the interrupt mode of the associated context.
  • the interrupt mode is one of a standard mode, vectored mode or single threaded mode:
  • the standard mode operates such that when an interrupt comes in it pushes the current PC and status register on the stack, goes to supervisor mode, fetches a vector, and begins executing the interrupt service routine. Interrupts can be nested when in this mode.
  • the vectored mode is a much faster interrupt approach. When an interrupt comes in the associated vector is fetched and execution begins, nothing is saved to the stack. When the routine completes and executes a SLEEP instruction, it simply puts the context into wait mode. This mode does not support nested interrupts, although faults operate just as in standard mode.
  • the single-threaded mode is the fastest interrupt approach. When an interrupt comes in the thread is made ready and begins execution at the current program counter (e.g. you could have a task that loops back on itself). No distinction is made between interrupt sources. This mode does not support nested interrupts (although faults operate just as in standard mode).
  • the execution unit includes a prefetch module 301 shown in FIG. 3 and instruction execution unit 201 shown in FIG. 2.
  • the Execution unit portion of CPU 101 receives and decodes instructions and sends them to ALU 205.
  • the Execution unit also initiates storing of the instruction result and generates control addresses for branches.
  • Data from the bus interface unit 119 of FIG. 1 is inputted to a ping pong set of registers 303, 305, 307, 309.
  • the initial execution cycle bypasses the ping pong set of registers 303, 305, 307, 309 directly to the instruction execution unit 201.
  • Instruction execution unit 309 decodes the op-code, mode, data or address registers, and extension words. Instruction execution unit 309 flows data and data instruction information into ALU 205. The inputs dictate which context the execution unit is handling and which are pending. If a change of context is pending, the execution unit finishes its current execution before switching contexts.
  • context manager 105 utilizes multiple register banks to maintain context.
  • the program counter PC and status register SR are saved to the stack (along with some stack frame control words), the program counter is loaded from a vector, the supervisor bit in the status register SR is set and execution begins in the switched-to-context
  • Hardware kernel IA determines which context executes on CPU 103 and controls switching from one context to another. The determination regarding which context should be made current is made as follows:
  • context 0 i.e., the master context
  • context 0 is always the highest priority context.
  • next active context is different from the current active context then the current context will be frozen, i.e., current instruction is finished or interrupted and state cleaned up, then the next active context will be made active, i.e., next active context's register set will be enabled and execution begun within that context.
  • Each of the five hardware contexts has a priority associated with it. Each context also has linked interrupts. Priority of any given context can be changed at run time.
  • the hardware resources in the illustrative embodiment that are utilizable by microcontroller 1 are: CPU - Fast Context Switch; CPU - Deterministic MPU; CPU - Deterministic Cache; CPU - Single Priority Model; and CPU - Context Timers for Time Partitioning. Each resource is described below.
  • CPU - Fast Context Switch- Microcontroller 1 has the ability to switch from one context to another context within a single bus cycle after the current instruction has been completed.
  • CPU - Deterministic MPU- Memory Protection Unit (MPU) 129 shown of FIG. 1 provides 16 Memory Control Blocks 601 as shown in FIG. 6.
  • Each block 601 has an associated register 603 that defines the starting point, size and attributes of the memory range defined by that block.
  • each hardware context has an associated MPU allocation register that identifies which blocks are active for the corresponding context.
  • Multiple controls can be placed on a single address range, so for example one block can be set up allowing read/write access to some range for context 2 while another block allows read-only access to the same range for context 3.
  • CPU - Deterministic Cache- Microcontroller 1 contains a Deterministic Cache or user programmable cache 127 shown in FIGS. 7, 7 A, 8, and 9 the size of which is preferably at least 8K x 32.
  • the loading of cache 127 is under software control.
  • Cache 127 is separated into 16 partitions.
  • CPU - Single Priority Model- Microcontroller 1 has a single priority model for interrupts and other threads of control. This single priority model is extendable to include other processes such as DMA via DMA channels 113. Although DMA does not require a context as such, it may be assigned a priority on the same scale as the tasks. Thus if a task of lower or equal priority is executing, the DMA will be active; if a higher priority task is executing, the DMA will be halted. If there are multiple DMA channels then they will behave toward each other based on the priority as well. If one DMA has higher priority than the other, then it will run exclusive of the other until it is complete. If two DMAs have the same priority then they share the bus.
  • CPU - Context Timers for Time Partitioning One concern in critical systems such as mission-critical and safety-critical systems or the like is to ensure that a failure in one task does not impact others.
  • Microcontroller 1 assures this through the use of time and space partitioning. Space partitioning is accomplished through the use of MPU 129. Time partitioning usually requires either a high frequency timer interrupt or a highly programmable timer and a lot of software overhead.
  • Microcontroller 1 provides time partitioning via context timer module 501 shown in FIG. 5. Each context is assigned a jmax execution register 503. When the task is active, register 503 is compared by a comparator 507 to a task timer 505.
  • CPU - Context-Aware H/W Breakpoints & Watchpoints The hardware breakpoints and watchpoints are context-specific. This enables breaks on a location when a particular thread is active and the hardware would only interrupt execution when the address matched and the thread matched. This also is extended to support thread-aware watchpoints as well (provide a way to indicate read, write and optionally a value for a given address).
  • Interrupts are assigned to a particular context and prioritized. Interrupt priority is a "second level" of priority and is distinct from context priority. An interrupt's priority is compared to the context's status register and determination is made to either process the interrupt or to continue "normal" processing of the context.
  • Interrupt sources have a two-fold association with priorities. First they each have a register associating them with a specific context. The associated context is the one that is interrupted when the condition occurs. Thus the priority of a context also applies to the interrupts assigned to it. The second layer of priority is the model found in the CPU32 architecture. Eight interrupt priority levels (7-0, with 7 being highest) are available to interrupt sources (with a level 7 interrupt being non-maskable). The interrupt priority level found in the status register of each context determines whether the context is interrupted (if currently ready) or is moved to the ready state (if currently waiting).
  • Each context has a priority associated with it.
  • a separate priority register is provided as a part of the context.
  • Each context also has a ready flag. The hardware detects any change in the state of ready flags. At the time of such a change the highest priority, active, task would be selected for execution.
  • the ready flags are set by linking an interrupt source to a given context. That is, the 'priority' register normally associated with an interrupt actually refers to a context. When the interrupt event occurs it sets the ready flag for the associated context. Each interrupt points to a given context. Multiple interrupts can point to a given context.
  • Microcontroller 1 provides the following modes for interaction of interrupts and contexts:
  • Dedicated context mode The context is dedicated to the interrupt(s). When the interrupt comes in, if the task is busy, the interrupt is held off until the task goes inactive. If the task is inactive the interrupt comes in immediately thereby activating the task. The task (context) begins execution based on where its program counter is operating. There is no delay and nothing goes to the stack.
  • Vectored context mode The context is dedicated to a set of interrupts. When the interrupt comes in, if the task is busy, the interrupt is held off until the task goes inactive. If the task is inactive the interrupt comes in activating the task. The vector associated with the interrupt source is fetched from memory and execution begins at that location. None is preserved of the context.
  • Standard Interrupt mode This is interrupt processing as on traditional processors.
  • the associated context's execution is interrupted if it is active. Context is placed on the stack (Program Counter and Status Register). The associated vector is fetched and execution begins in the interrupt handler.
  • a separate priority register is provided rather than simply using the context ID so that priority of a given task can be changed at runtime. There are various reasons for doing this in an embedded system, e.g., resource deadlock (priority inheritance), or because of a re-tasking of the processor. A rule is established to handle the case where multiple tasks are ready and have the same priority. [0097] Certain operations are limited to a master context of the processor. Operations that fall into this category include:
  • Supervisor modes are implemented in the hardware executive by limiting these operations to context 0. A corollary to this is that all fatal/critical faults are handled by context 0.
  • microcontroller 1 has just been reset.
  • the hardware begins execution at a reset vector, running in context zero.
  • the software sets up all other contexts, DMA channels, interrupts, etc., then sets context zero's entry point to a fault handler, sets the appropriate ready flags on the other contexts and put itself to sleep.
  • context zero can address the context registers of the other tasks which is helpful for debugger development as well.
  • the hardware context described above includes some timing capability.
  • the microcontroller 1 has a timer 107 that executes continuously. Each time there is a context switch the value of timer 107 is added to a register associated with the context of the task being exited and the timer is cleared. Thus the register associated with each task has elapsed execution time for that task.
  • Software executing in context 0 maintains statistics, e.g., average and worst case frame times, and clear the counters on some major or task-specific frame boundaries.
  • Faulted Context Register which is a single register used to identify the lower level context executing when an exception occurs
  • Context Control Registers which include a register for each context used to specify the context's mode, priority and state;
  • Context Timer Registers which provide a register for each context used to measure its execution time
  • Context Timer Clear Register which is a single register used to clear the timers of selected contexts
  • Context Timer Enable Register which is a single register used to enable the timers of selected contexts
  • Context Max Time Registers which include a register for each context used to specify the maximum time it can "own” the CPU.
  • Microcontroller 1 is provided with a deterministic cache.
  • the deterministic cache is a high-speed memoiy that is loaded with critical code sections under programmer control to increase the execution speed of the associated code.
  • the deterministic cache includes logic to allow the address of each block to be modified by the programmer to overlay slow external memory for critical blocks of code and data.
  • cache is under software control. Cache portions are allocated to specific blocks of code (typically interrupt handlers, highest rate tasks, etc.). Any portions of the cache not so allocated could operate as typical prior art cache, or for a simpler implementation, just require that all cache be pre-allocated.
  • a deterministic cache comprising a set of blocks of memory 701 and associated address translation logic 703. Part of the address in block 703 is decoded to detect a hit on a particular address block. The lower bits of the address are used to address the block.
  • a RAM 900 is arranged into a number of blocks 901. Each block 901 can be independently remapped in the memory map (i.e. assigned a new address).
  • RAM 900 in the illustrative embodiment, has the following characteristics:
  • Each control register 903 manages a 'page' of 2 Kbytes
  • Microcontroller 1 further includes a plurality of universal I/O controllers 135, 137, 139, 141 identified as UIC 0, UIC 1, UIC 2 and UIC 3.
  • Each universal I/O controller 135, 137, 139, 141 is configurable to support various communication protocols across multiple platforms.
  • each universal I/O controller 135, 137, 139, 141 provides the ability to match specific applications with a single microcontroller chip.
  • I/O- Each peripheral including a UIC must have the ability to have its clock switched off through software.
  • the I/O architecture of microcontroller 1 in the illustrative embodiment supports 6 high-speed transfers simultaneously.
  • microcontroller 1 also supports Ethernet message filtering. This is not meant to specifically exclude filtering for other protocols.
  • Microcontroller 1 has both a 256-location, 48-bit full address filter and standard hash filtering. The type of filtering is selected under CPU control, by application code.
  • Microcontroller 1 is able to handle all I/O on a message basis rather than a byte-by-byte basis for the purpose of reducing the processing needs of the CPU. Microcontroller 1, under application control, may also get messages on a byte-by-byte basis.
  • CPU DMA 113 provides direct memory access capability to/from Dual Port RAM Frame Buffers and bus interface 119.
  • a peripheral DMA block provides direct memory data transfer capability from the transmit or receive Frame Buffers of any on chip peripheral to or from the CPU RAM.
  • PeripheralDma is responsible for automatically transferring data to/from the UICs.
  • This block generates all control signals for the Frame Buffers including the cpu side address, peripheral side address, lane selection, and write enable strobes. This operation is transparent as far as the cpu is concerned.
  • a "deterministic microcontroller” in which a deterministic microprocessor is coupled with a set of integrated peripherals.
  • the integration is such that peripheral activity does not negatively impact the deterministic properties of the microprocessor.
  • the relationship between external bus and context management unit is a matter of priority.
  • the external bus has a pair of arbitration signals used to allow another device to take over the bus and read/write to external memory.
  • a priority is assigned to this external interface.
  • An external bus priority register includes bits that are used to assign the priority that the external bus master has relative to internal microcontroller resources, i.e., the plurality of hardware contexts and the CPU DMA controller.
  • the external bus priority register is writeable only from the master context.

Abstract

L'invention concerne un microcontrôleur déterministe. Le microcontrôleur peut être commuté sur divers contextes. Une pluralité d'ensembles de registres matériels est fournie. Une pluralité correspondante de contextes matériels pour le microcontrôleur est fournie par la pluralité d'ensembles de registres matériels. Un gestionnaire de contextes contrôle la sélection des registres matériels de sorte que les contextes sont modifiés à l'intérieur d'un cycle de bus et une pluralité de contextes matériels sont fournis. Le microncontrôleur comprend une pluralité de blocs de mémoires caches formés sur le même circuit intégré qu'une unité centrale à microprocesseur.
PCT/US2006/001575 2005-01-27 2006-01-18 Microcontroleur deterministe WO2006081094A2 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US64813805P 2005-01-27 2005-01-27
US60/648,138 2005-01-27
US11/259,420 US7516311B2 (en) 2005-01-27 2005-10-26 Deterministic microcontroller context arrangement
US11/259,755 US20060168421A1 (en) 2005-01-27 2005-10-26 Method of providing microcontroller cache memory
US11/259,755 2005-10-26
US11/259,420 2005-10-26
US11/258,822 US7562207B2 (en) 2005-01-27 2005-10-26 Deterministic microcontroller with context manager
US11/258,822 2005-10-26
US11/259,741 US20060168420A1 (en) 2005-01-27 2005-10-26 Microcontroller cache memory
US11/259,741 2005-10-26

Publications (2)

Publication Number Publication Date
WO2006081094A2 true WO2006081094A2 (fr) 2006-08-03
WO2006081094A3 WO2006081094A3 (fr) 2009-04-09

Family

ID=36740953

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2006/001573 WO2006081092A2 (fr) 2005-01-27 2006-01-18 Microcontroleur deterministe a interface d'entree/sortie configurable
PCT/US2006/001574 WO2006081093A2 (fr) 2005-01-27 2006-01-18 Produit standard specifique d'une application configurable a interface e/s configurable
PCT/US2006/001575 WO2006081094A2 (fr) 2005-01-27 2006-01-18 Microcontroleur deterministe

Family Applications Before (2)

Application Number Title Priority Date Filing Date
PCT/US2006/001573 WO2006081092A2 (fr) 2005-01-27 2006-01-18 Microcontroleur deterministe a interface d'entree/sortie configurable
PCT/US2006/001574 WO2006081093A2 (fr) 2005-01-27 2006-01-18 Produit standard specifique d'une application configurable a interface e/s configurable

Country Status (1)

Country Link
WO (3) WO2006081092A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019009870A1 (fr) * 2017-07-01 2019-01-10 Intel Corporation Sauvegarde de contexte à taille d'état de sauvegarde variable
US10877756B2 (en) 2017-03-20 2020-12-29 Intel Corporation Systems, methods, and apparatuses for tile diagonal
CN112860444A (zh) * 2021-04-26 2021-05-28 腾讯科技（深圳）有限公司 内存调用信息的确定方法和装置、存储介质及电子设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426769A (en) * 1993-08-26 1995-06-20 Metalink Corp. System and method for producing input/output expansion for single chip microcomputers
US6389449B1 (en) * 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305446A (en) * 1990-09-28 1994-04-19 Texas Instruments Incorporated Processing devices with improved addressing capabilities, systems and methods
US5758188A (en) * 1995-11-21 1998-05-26 Quantum Corporation Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal
US5949994A (en) * 1997-02-12 1999-09-07 The Dow Chemical Company Dedicated context-cycling computer with timed context
US6553487B1 (en) * 2000-01-07 2003-04-22 Motorola, Inc. Device and method for performing high-speed low overhead context switch
US6401154B1 (en) * 2000-05-05 2002-06-04 Advanced Micro Devices, Inc. Flexible architecture for an embedded interrupt controller
US20030195989A1 (en) * 2001-07-02 2003-10-16 Globespan Virata Incorporated Communications system using rings architecture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426769A (en) * 1993-08-26 1995-06-20 Metalink Corp. System and method for producing input/output expansion for single chip microcomputers
US6389449B1 (en) * 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HENNESSY ET AL.: 'Computer Organization and Design The Hardware/Software Interface', 1998 pages 638 - 641 *
INTEL.: 'Intel Architecture Software Developer's Manual' BASIC ARCHITECTURE vol. 1, 1999, pages 3-5 - 3-14 *

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11567765B2 (en) 2017-03-20 2023-01-31 Intel Corporation Systems, methods, and apparatuses for tile load
US11288068B2 (en) 2017-03-20 2022-03-29 Intel Corporation Systems, methods, and apparatus for matrix move
US11977886B2 (en) 2017-03-20 2024-05-07 Intel Corporation Systems, methods, and apparatuses for tile store
US11080048B2 (en) 2017-03-20 2021-08-03 Intel Corporation Systems, methods, and apparatus for tile configuration
US11847452B2 (en) 2017-03-20 2023-12-19 Intel Corporation Systems, methods, and apparatus for tile configuration
US11163565B2 (en) 2017-03-20 2021-11-02 Intel Corporation Systems, methods, and apparatuses for dot production operations
US10877756B2 (en) 2017-03-20 2020-12-29 Intel Corporation Systems, methods, and apparatuses for tile diagonal
US11200055B2 (en) 2017-03-20 2021-12-14 Intel Corporation Systems, methods, and apparatuses for matrix add, subtract, and multiply
US11086623B2 (en) 2017-03-20 2021-08-10 Intel Corporation Systems, methods, and apparatuses for tile matrix multiplication and accumulation
US11288069B2 (en) 2017-03-20 2022-03-29 Intel Corporation Systems, methods, and apparatuses for tile store
US11263008B2 (en) 2017-03-20 2022-03-01 Intel Corporation Systems, methods, and apparatuses for tile broadcast
US11360770B2 (en) 2017-03-20 2022-06-14 Intel Corporation Systems, methods, and apparatuses for zeroing a matrix
US11714642B2 (en) 2017-03-20 2023-08-01 Intel Corporation Systems, methods, and apparatuses for tile store
WO2019009870A1 (fr) * 2017-07-01 2019-01-10 Intel Corporation Sauvegarde de contexte à taille d'état de sauvegarde variable
US11275588B2 (en) 2017-07-01 2022-03-15 Intel Corporation Context save with variable save state size
CN112860444A (zh) * 2021-04-26 2021-05-28 腾讯科技（深圳）有限公司 内存调用信息的确定方法和装置、存储介质及电子设备

Also Published As

Publication number Publication date
WO2006081092A3 (fr) 2007-10-25
WO2006081092A2 (fr) 2006-08-03
WO2006081094A3 (fr) 2009-04-09
WO2006081093A3 (fr) 2007-05-24
WO2006081093A2 (fr) 2006-08-03

Similar Documents

Publication Publication Date Title
US7406550B2 (en) Deterministic microcontroller with configurable input/output interface
US10379887B2 (en) Performance-imbalance-monitoring processor features
US7526579B2 (en) Configurable input/output interface for an application specific product
US6587937B1 (en) Multiple virtual machine system with efficient cache memory design
US10387191B2 (en) Task processor
EP0794492B1 (fr) Exécution répartie de commandes à mode inadapté dans des systèmes multiprocesseurs
US8234430B2 (en) Apparatus and method with controlled switch method
EP1573532B1 (fr) Architecture permettant de prendre en charge de multiples contextes d'execution en simultanee sur un processeur
US6944850B2 (en) Hop method for stepping parallel hardware threads
US20140115594A1 (en) Mechanism to schedule threads on os-sequestered sequencers without operating system intervention
US20040205747A1 (en) Breakpoint for parallel hardware threads in multithreaded processor
KR102187912B1 (ko) 인터럽트들의 세트들을 구성하는 장치 및 방법
WO2008141063A2 (fr) Circuits, systèmes et procédés liés à une interruption
IL134823A (en) Method and device for selecting an event in a multi-process processor
US7516311B2 (en) Deterministic microcontroller context arrangement
US7818558B2 (en) Method and apparatus for EFI BIOS time-slicing at OS runtime
US7562207B2 (en) Deterministic microcontroller with context manager
US7680967B2 (en) Configurable application specific standard product with configurable I/O
WO2006081094A2 (fr) Microcontroleur deterministe
US9946665B2 (en) Fetch less instruction processing (FLIP) computer architecture for central processing units (CPU)
US20060168420A1 (en) Microcontroller cache memory
US8424013B1 (en) Methods and systems for handling interrupts across software instances and context switching between instances having interrupt service routine registered to handle the interrupt
US20060168421A1 (en) Method of providing microcontroller cache memory
CN108845969B (zh) 适用于不完全对称多处理微控制器的操作控制方法及操作系统
Balas et al. CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase

Ref document number: 06718627

Country of ref document: EP

Kind code of ref document: A2