WO2006076276A2

WO2006076276A2 - Configurable dedicated logic cells in programmable logic and routing blocks with dedicated lines and local connections

Info

Publication number: WO2006076276A2
Application number: PCT/US2006/000640
Authority: WO
Inventors: Hare K. Verma; Ashok Vittal; Ravi Sunkavalli; Chandra Mulpuri; Sudip Nag; Conrad Kong; Bo Hu; Manoj Gunwani; Elliott Delaye
Original assignee: Velogix, Inc.
Priority date: 2005-01-14
Filing date: 2006-01-10
Publication date: 2006-07-20
Also published as: EP2052459A2; WO2006076276A3

Abstract

A programmable logic structure is disclosed that has a set of dedicated lines (212, 222) which extends internally throughout different dedicated logic cells (210, 260) within a logic and routing block, extends from a previous logic routing block (260) to the present logic and routing block, or extends from the present logic and routing block to the next logic and routing block (270). One set of dedicated lines (212) from a first logic and routing block can be stitched to another set of dedicated lines of a second logic and routing block for extending the reach as well as bypassing a logic and routing block, or bypassing a dedicated logic cell in the same logic and routing block. The dedicated lines between logic and routing blocks allow a logic and routing block to receive more inputs from its own switch box or to drive more outputs than provided by the logic and routing block as specified by a given function.

Description

Configurable Dedicated Logic Cells in Programmable Logic and Routing Blocks with

Dedicated Lines and Local Connections

BACKGROUND OF THE INVENTION

Field of Invention

[0001] The present invention relates generally to integrated circuits (ICs) such as field programmable gate arrays (FPGAs), and more particularly to enhance connections between functional blocks in programmable logic devices as well as structures and functionalities in a dedicated logic circuit in the field programmable gate arrays.

Description of Related Art

[0002] Field programmable gate arrays are often selected by design engineers to provide a flexible approach in programming and re-programming integrated circuits in order to accommodate a system specification, correct errors in the system, or make improvements to the system by reprogramming the FPGA. One conventional field programmable gate array architecture is implemented using groups of look-up tables and programmable interconnect circuits. While the look-up tables and sequential elements are connected to each other, the connections to the groups of look-up tables typically originate from a switchbox located in each group of the look-up table. A hierarchical interconnect structure connects to elements in a look-up table through a switchbox, thereby serving as the primary source of connecting look-up tables from one logic block to another logic block. The inputs to the look-up tables are therefore generated primarily from the switchbox. The look-up table outputs are directly fed to other look-up tables as well as the elements within the look-up tables, but the connections to other look-up tables' inputs are made through the switchbox. [0003] In another conventional structure, a majority of the inputs required for performing all functionality of configurable logic blocks are typically restricted to inputs associated with a particular configurable logic block, other than through the use of the switch box. The same is true for outputs of a particular configurable logic block which are restricted to within the configurable logic block other than through the use of the switch box. [0004] A key building block in a programmable logic circuit is the design of a configurable logic block. Accordingly, it is therefore desirable to design a programmable logic structure employing configurable logic blocks with a set of logic functions to provide more programmable features. It is also desirable to design a programmable logic structure that enhances the connectivity of inputs and outputs in a programmable logic and routing module without boundary limitations.

SUMMARY OF THE INVENTION

[0005] The present invention describes a programmable logic structure, in a first aspect of the invention, that has a set of dedicated lines which extends internally throughout different dedicated logic cells within a logic and routing block (LRB)₅ extends from a previous logic routing block to the present logic and routing block, or extends from the present logic and routing block to the next logic and routing block. One set of dedicated lines from a first logic and routing block can be stitched to another set of dedicated lines of a second logic and routing block for extending the reach as well as bypassing a logic and routing block, or bypassing a dedicated logic cell in the same logic and routing block. The dedicated lines between logic and routing blocks allow a logic and routing block to receive more inputs from its own switch box or to drive more outputs than provided by the logic and routing block as specified by a given function.

[0006] In a second aspect of the invention, a programmable logic structure employs input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L + 1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect. In one embodiment, the term "point-to-point connection" means a connection from an output of a first LRC to an input of a second LRC.

[0007] In a third aspect of the invention, a dedicated logic cell in a programmable logic structure is constructed with the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-l multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

[0008] In addition, the present invention describes logic circuits for the functional components in the dedicated logic cell. In one embodiment of the invention, a configurable logic function comprises a plurality of look-up tables coupled to a multiplexer with configurable bits that is capable to perform as a four 4-input look-up table or a one 6- input look-up table, and a 4-to-l multiplexer function. In an alternative embodiment of the invention, a sequential logic function comprises one or more multiplexers coupled to a configurable register that is capable to perform one of the following functions, a positive latch, a negative latch, a rising edge triggered flop, or a fallen edge triggered flop in combination with one of the following control signals, a loadable register signal, a synchronous clear signal, a synchronous set signal, and a data enable signal. In another embodiment of the invention, a dedicated logic function comprises a plurality of multiplexers for selecting between different functional operations, such as an adder function, an accumulator function, or a shift data function, with selecting signals connected to the plurality of multiplexer that either remain static or dynamic configurable to achieve an arithmetic logic unit functionality. Alternatively, the dedicated logic function can be implemented to operate as a propagate and generate logic to perform the function of a look- ahead sum or as a priority multiplexer. In a further embodiment of the invention, a control logic function comprises a plurality of multiplexers with pre-calculated results for minimizing the delay produced from a lower dedicate logic function to an upper dedicated logic function.

[0009] Advantageously, the present invention provides a design for signals to cross a logic and routing block boundary. In addition, the present invention advantageously allows signals to skip a particular logic and routing block so that inputs and outputs need not be in contiguous locations. Furthermore, the present invention advantageously allows the creation of large wide logic structures in which functional blocks (e.g. function generators, multiplexers, wide gates, and wide multiplexers) with different inputs but common control signals in producing the benefits of not having to use a switch box in order to distribute control signals to all of the functional blocks in a given structure, thereby significantly reduces the burden on the switch box to distribute high fanout control and data lines in a programmable logic device.

[0010] The present invention further advantageously provides direct point-to-point connections between logic and routing cells from one dedicated logic cell to another dedicated logic cell. As a result, the present invention avoids delays that typically occur in routing connections through a switch box, multiplexers, and lines. The present invention further advantageously provides a symmetric structure in a programmable logic circuit in order to obtain local connections by placing elements, e.g. LRCs, at a location for making local connections.

[0011] Other structures and methods are disclosed in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims. These and other embodiments, features, aspects, and advantages of the invention will become better understood with regard to the following description, appended claims and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is a logic diagram illustrating a partial dedicated logic cell employing one or more dedicated lines in a logic and routing block in accordance with the present invention.

[0013] FIG. 2 is an architectural diagram illustrating a logic and routing block having multiple dedicated logic cells in a logic and routing block in accordance with the present invention.

[0014] FIG. 3 is a logic diagram illustrating a dedicated logic cell employing eight dedicated lines in accordance with the present invention.

[0015] FIG. 4 is a logic diagram illustrating the first implementation of a dedicated logic cell that operates as an 8-input function generator in accordance with the present invention.

[0016] FIG. 5 is a logic diagram illustrating the second implementation of a dedicated logic cell that serves as a 7-input function generator in accordance with the present invention.

[0017] FIG. 6 is a logic diagram illustrating the third implementation of a dedicated logic cell employing four 2:1 multiplexers with a common select line in accordance with the present invention.

[0018] FIG. 7 is a logic diagram illustrating the fourth implementation of using eight dedicated lines in large multiplexers in accordance with the present invention.

[0019] FIG. 8 is shown a logic diagram illustrating the fifth implementation of using dedicated lines as control lines in a configurable sequential circuit in accordance with the present invention.

[0020] FIG. 9 is a logic diagram illustrating the sixth implementation of a programmable logic circuit that shared dedicated lines as control lines among multiple macro blocks in accordance with the present invention.

[0021] FIG. 10 is a flow diagram illustrating the process of operating one or more dedicated lines in a logic and routing block in accordance with the present invention.

[0022] FIG. 11 is a logic diagram illustrating a dedicated logic structure in a two multiplexers scheme employing a first logic and routing cell for port A and a second logic and routing cell for port B architectural diagram illustrating a logic and routing block having multiplex dedicated logic cells in accordance with the present invention. [0023] FIG. 12 is a logic diagram illustrating a programmable logic chip constructed multiple levels of dedicated logic cells in accordance with the present invention.

[0024] FIG. 13 is a block diagram illustrating an example in performing a logic operation in a single column of dedicated logic cells in accordance with the present invention.

[0025] FIG. 14 is a logic diagram illustrating a first example of a programmable logic circuit employing local connections between different levels of dedicated logic cells in accordance with the present invention.

[0026] FIG. 15 is a logic diagram illustrating a programmable logic circuit with a set of offset parameters for feeding the OLRC multiplexer in the level L to the ILRC multiplexer in the level L+l in accordance with the present invention.

[0027] FIG. 16 is a logic diagram illustrating a second example of a programmable logic circuit employing local connections between different levels of dedicated logic cells in accordance with the present invention.

[0028] FIG. 17 is an architectural diagram illustrating a programmable logic circuit with stitchings between output OLRC multiplexers in accordance with the present invention.

[0029] FIG. 18 is a block diagram illustrating a programmable logic circuit with two dedicated logic cells from the OLRC at level -L to the ILRC at the ate level 0 in accordance with the present invention.

[0030] FIG. 19 is a block diagram illustrating a programmable logic circuit with local connections for performing a logic operation of A + B + C in accordance with the present invention.

[0031] FIG. 20 is a block diagram illustrating a programmable logic circuit with local connections for fan out, a horizontal offset for a local connection from one column to another column, and a vertical offset for a local connection from one row to another row in accordance with the present invention.

[0032] FIG. 21 A is a block diagram illustrating a programmable logic circuit that employs inverting buffers or non-inverting buffers in accordance with the present invention;

FIG. 2 IB is a logic diagram illustrating an inverter buffer in accordance with the present invention, while FIG. 21C is a logic diagram illustrating a non-inverter buffer in accordance with the present invention. [0033] FIG. 22 is a flow diagram illustrating the process for programming a programmable logic circuit with local connections between dedicated logic cells in accordance with the present invention.

[0034] FIG. 23 is an architectural diagram illustrating a pair of dedicated logic cells comprising of four types of components: a configurable logic function or a look-up table, a dedicated logic function, a sequential logic function, and a control logic function in accordance with the present invention.

[0035] FIG. 24 is a logic diagram illustrating the configurable logic function (LL structure) in the dedicated logic cell in accordance with the present invention. [0036] FIG. 25 is a logic diagram illustrating the sequential logic function (LS structure) in the dedicated logic cell in accordance with the present invention.

[0037] FIG. 26 is logic diagram illustrating the dedicated logic function (LD structure) in the dedicated logic cell in accordance with the present invention.

[0038] FIG. 27 is a logic circuit illustrating an alternative embodiment of the dedicated logic function that operates as a propagate/generate logic to perform the function of a look- ahead sum or as a priority multiplexer in accordance with the present invention. [0039] FIG. 28 is a logic diagram illustrating an example of a priority multiplexer as described with respect to the dedicated logic cell as shown in FIG. 10 for use in a carry- ahead carry generation scheme in accordance with the present invention. [0040] FIG. 29 is state diagram illustrating of the control logic function (LC structure) in the dedicated logic cell in accordance with the present invention.

[0041] FIG. 30 is logic diagram illustrating an example of a control logic function in accordance with the present invention.

[0042] FIG. 31 is a logic circuit illustrating a first embodiment of the dedicated logic cell implemented as a four 2-input function employing configurable logic functions and a dedicated logic function in accordance with the present invention.

[0043] FIG. 32 is a logic circuit illustrating a second embodiment of the dedicated logic cell implemented as a four 2:1 multiplexer employing configurable logic functions and a dedicated logic function in accordance with the present invention.

[0044] FIG. 33 is a block diagram illustrating a third embodiment of the dedicated logic cell implemented as a two 6-input functions of configurable logic functions with separate inputs having a first configurable logic function and a second configurable logic function in accordance with the present invention.

[0045] FIG. 34 is a logic diagram illustrating a fourth embodiment of the dedicated logic cell implemented as a shift register which is capable of performing a loadable, resettable, or clearable function by using a combination of a configurable logic function and sequential logic functions in accordance with the present invention.

[0046] FIG. 35 is a logic diagram illustrating a fifth embodiment of the dedicated logic cell implemented as an accumulator by employing configurable logic functions, a dedicate logic function, and sequential logic functions in accordance with the present invention.

[0047] FIG. 36 is a flow diagram illustrating a method for programming configuration bits for configuring one or more programmable function generators in accordance with the present invention.

[0048] Reference symbols or names are used in the Figures to indicate certain components, aspects or features therein, with reference symbols common to more than one

Figure indicating like components, aspects or features shown therein.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0049] Referring now to FIG. 1, there is shown a logic diagram illustrating a partial dedicated logic cell 100 employing the use of one or more dedicated lines 110 for connections between logic and routing blocks (LRBs), or connections from one dedicated logic cell (DLC) to another dedicated logic cell. The one or more dedicated lines 110 enter the partial dedicated logic cell 100 in a present logic and routing block through a control input line 111. The first multiplexer 120 has a first input connected to the control input 111 for receiving the one or more dedicated lines 110, a second input connected to line inputs 115 from a look-up table, a third input connected to a Vdd 121, and a fourth input connected a ground 122, and an output 127 connected to an adjacent dedicated logic cell in the same logic and routing block. Configurable select lines 125 allows selection from one of the four inputs 110, 115, 121, or 122 in the first multiplexer 120 for generating the output 127 to the adjacent dedicated logic cell in the same logic and routing block. The second multiplexer 130 has a first input connected to a control input 111 for receiving the one or more dedicated lines 110, a second input connected to line inputs 115 from the look-up table, a third input connected to a Vdd 131, and a fourth input connected a ground 132, and an output 137 connected to the next logic and routing block (or the next dedicated logic cell.) Configurable select lines 135 allow selection from one of the four inputs, 111, 115, 131, or 132 in the second multiplexer 130 to the next logic and routing block. [0050] The logic and routing blocks that provide the additional inputs need not be adjacent to the current logic and routing block where the function is implemented. The one or more dedicated lines can be used either as data or control signals. By deploying the one or more dedicated lines, the connectivity of a logic and routing block for enabling input and output connections can be made seamlessly irrespective of a logic and routing block boundary 140. The one or more dedicated lines 110 connect between logic and routing blocks that allow a logic and routing block to receive inputs from other logic and routing blocks when a given function implemented in the logic and routing block requires more inputs than provided by the switchbox 250 in the logic and routing block. The one or more dedicated lines 110 also allow the logic and routing block to drive more outputs than provided by the present logic and routing block.

[0051] In this embodiment, the partial dedicated logic cell 100 employs eight dedicated lines 110 for each pair of dedicated logic cells. The eight dedicated lines 110 can be used as either data or control signal lines for various modes of operation. The eight dedicated lines are fed by eight outputs of a dedicated logic cell (not shown) or from a previous set of dedicated lines (not shown). Each dedicated line in the eight dedicated lines 110 can be tied to a high or low voltage. The eight dedicated lines 110 are fed to functional blocks to enable creation of larger functional blocks than permissible from a switch box, as shown in FIG. 2. For example, six and seven inputs general purpose function generators (i.e., look-up tables or "LUTs") and 8-input limited function generators are possible by using the dedicated input lines to provide inputs from other logic and routing blocks.

[0052] In FIG. 2, there is shown an architectural diagram illustrating a logic and routing block 200 comprising a first dedicated logic cell (DLC 0) 210, a second dedicated logic cell (DLC 1) 220, a third dedicated logic cell (DLC 2) 230, a fourth dedicated logic cell (DLC 3) 240 and a switch box 250 for providing programmable switch matrices. A set of dedicated lines is used to interconnect between adjacent dedicated logic cells, either for connects to adjacent dedicated logic cells within the logic and routing block, adjacent dedicated logic cells between the logic and routing block 200 and a previous logic and routing block, or connecting to adjacent dedicated logic cells between the logic routing block 200 and a next logic and routing block. A first set of eight dedicated lines 211 is connected from a previous dedicated logic cell 260 (not shown) to the first dedicated logic cell 210. A second set of eight dedicated lines 212 is connected from the first dedicated logic cell DLCO 210 to the second dedicated cell DLCl 220. A third set of dedicated line 213 is connected from the second dedicated cell 220 to the next dedicated local cell 270 (not shown). A fourth set of eight dedicated lines 221 is connected from the previous dedicated logic cell 260 (not shown) to the third dedicated logic cell 230. A fifth set of eight dedicated lines 222 is connected from the third dedicated logic cell 230 to the fourth dedicated logic cell 240. A sixth set of eight dedicated lines 223 is connected from the fourth dedicated logic cell 240 to the next dedicated logic cell 270 (not shown). The switchbox 250 functions as a source for feeding control of data signals to any one of the dedicated lines 211, 212, 213, 221, 222, or 223. While the first set of eight dedicated lines 211 and the fourth set of eight dedicated lines 221 are connected from the previous logic and cell block 260, (not shown) the third set of eight dedicated lines 213 and the sixth set of eight dedicated lines 223 are connected to the next logic and cell block 270 (not shown).

[0053] The one ore more dedicated line can be driven by the previous corresponding one or more dedicated lines as well as driving the next corresponding one or more dedicated lines, which would extend the distance of the dedicated lines. In effect, one set of dedicated lines can be connected ("stitched") to another set of dedicated lines, as may be called for by a particular programmable logic device, for concatenating different sets of dedicated lines together that extend across different logic and routing blocks.

[0054] In FIG. 3, there is shown a logic diagram illustrating the first implementation of a dedicated logic cell 300 with eight dedicated lines 310-317. The dedicated logic cell 300 comprises a first set of function generators, a first function generator (FG) 320, a second function generator 322, a third function generator 324, and a fourth function generator 326 where each function generator having four inputs for receiving A[O] 301, A[I] 302, A[2] 303, and A[3] 304 from the switch box 250. The dedicated logic cell 300 comprises a second set of function generators, a fifth function generator 330, a sixth function generator 332, a seventh function generator 334, and an eighth function generator 336 where each function generator having four inputs for receiving B[O] 305, B[I] 306, B[2] 307, and B[3] 308 from the switch box 250. A first multiplexer 340 has a first input connected to an output of the first function generator 320, a second input connected to the eighth dedicated line C7 317, a third input connected to a Vdd, a fourth input connected to a ground, and an output connected to the next DLC. A second multiplexer 341 has a first input connected to an output of the second function generator 322, a second input connected to the seventh dedicated line C6 316, a third input connected to a Vdd, a fourth input connected to a ground, and an output connected to the next DLC. A third multiplexer 342 has a first input connected to an output of the third function generator 324, a second input connected to the fifth dedicated line C5 315, a third input connected to a ground, a fourth input connected to a Vdd, and an output connected to the next DLC. A fourth multiplexer 343 has a first input connected to an output of the fourth function generator 326, a second input connected to the fifth dedicated line C4 314, a third input connected to a Vdd, a fourth input connected to a ground, and an output to the next DLC. A fifth multiplexer 344 has a first input connected to an output of the fifth function generator 330, a second input connected to the fourth dedicated line C3 313, a third input connected to a Vdd, a fourth input connected to a ground, and an output connected to the next DLC. A sixth multiplexer 345 has a first input connected to an output of the sixth function generator 332, a second input connected to the third dedicated line C2 312, a third input connected to a Vdd, a fourth input connected to a ground, and an output connected to the next DLC. A seventh multiplexer 346 has a first input connected to an output of the seventh function generator 334, a second input connected to the second dedicated line Cl 311, a third input connected to a Vdd, a fourth input connected to a ground, and an output connected to the next DLC. An eighth multiplexer 347 has a first input connected to an output of the eighth function generator 336, a second input connected to the first dedicated line CO 310, a third input connected to a Vdd, a fourth input connected to a ground, and an output connected to the next DLC.

[0055] A corresponding set of multiplexers are connected to the respective one of the multiplexers 340-347 for generating outputs to logic and routing blocks. A ninth multiplexer 350 has a first input connected to the output of the first function generator 320, a second input connected to the eighth dedicated line C7 317, a third input connected to a Vdd, a fourth input connected to a ground, and an output for connecting to a logic and routing block. A tenth multiplexer 351 has a first input connected to the output of the second function generator 322, a second input connected to the seventh dedicated line C6 316, a third input connected to a Vdd, a fourth input connected to a ground, and an output for connecting to the logic and routing block. An eleventh multiplexer 352 has a first input connected to the output of the third function generator 324, a second input connected to the sixth dedicated line C5 315, a third input connected to a Vdd, a fourth input connected to a ground, and an output for connecting to the logic and routing block. A twelfth multiplexer 353 has a first input connected to the output of the fourth function generator 326, a second input connected to the fifth dedicated line C4 314, a third input connected to a Vdd, a fourth input connected to a ground, and an output for connecting to the logic and routing block. A thirteenth multiplexer 354 has a first input connected to the output of the fifth function generator 330, a second input connected to the fourth dedicated line C3 313, a third input connected to a Vdd, a fourth input connected to a ground, and an output for connecting to the logic and routing block. A fourteenth multiplexer 355 has a first input connected to the output of the sixth function generator 332, a second input connected to the third dedicated line C2 312, a third input connected to a Vdd, a fourth input connected to a ground, and an output for connecting to the logic and routing block. A fifteenth multiplexer 356 has a first input connected to the output of the seventh function generator 334, a second input connected to the second dedicated line Cl 311, a third input connected to a Vdd, a fourth input connected to a ground, and an output for connecting to the logic and routing block. A sixteenth multiplexer 357 has a first input connected to the output of the eighth function generator 336, a second input connected to the first dedicated line CO 310, a third input connected to a Vdd, a fourth input connected to a ground, and an output for connecting to the logic and routing block.

[0056] The following diagrams, FIGS. 4 through 9, show the different applications of adopting the use of the one or more dedicated lines. Turning now to FIG. 4, there is shown a logic diagram illustrating the first implementation of a dedicated logic cell 400 that operates as a 7-input function generator, which is equivalent to two 6-input look-up tables. The dedicated logic cell 400 employs dedicated lines CO 410, Cl 411, C2 412, and C3 413 the function as select lines to 4:1 multiplexers 430 and 440. If the eight inputs are referred to as I[0:7], the first four inputs I[0:3] are supplied by either A[0:3] 401-404 or B[0:3] 405-408, the fifth and sixth inputs are generated from CO 412 and C1411, and the sixth and seventh inputs are generated from C2412 and C3412. A first 6-input look-up table in the logic dedicated cell 400 comprises a first function generator 420, a second function generator 422, a third function generator 424, and a fourth function generator 426 that have outputs feeding into inputs of the 4:1 multiplexer 430. Each of the first, second, third and fourth function generators 420, 422, 424, and 426 have four inputs for receiving the incoming signals A[0:3] 401-404. The dedicated lines C2 412 and C3 413 function as select lines to the 4:1 multiplexer 430 for selecting one of the inputs from either the first, second, third, or fourth function generator 420, 422, 424, 426, as well as generating an output signal of OUTO 435. A second 6-input look-up table in the logic dedicated cell 400 comprises a fifth function generator 430, a sixth function generator 432, a seventh function generator 434, and an eighth function generator 436 that have outputs feeding into inputs of the 4:1 multiplexer 440. Each of the first, second, third and fourth function generators 430, 432, 434, and 436 have four inputs for receiving the incoming signals B[0:3] 405-408. The dedicated lines CO 410 and Cl 411 function as select lines to the 4:1 multiplexer 440 for selecting one of the inputs from either the fifth, sixth, seventh, or eighth function generator 430, 432, 434, 436, and generating an output signal of OUTl 445.

[0057] In FIG. 5, there is shown a logic diagram illustrating the second implementation of a dedicated logic cell 500 that serves as a 7-input function generator. If the seven inputs are referred to as I[0:6], the first four inputs I[0:3] are supplied by either A[0:3] 501-504 or B[0:3] 505-508, the fifth input I[4] is generated from either a configurable select line CO 510 or C2 512, the sixth input I[5] is generated from either a configurable select line Cl 511 or C3 513, and the seventh input I[6] is supplied by a configurable select line C4 514. The dedicated logic cell 500 comprises a first set of function generators having a first function generator 520, a second function generator 522, a third function generator 524, and a fourth function generator 526 where each function generator has four inputs for receiving A[0:3] 501-504 and an output connected to a 4:1 multiplexer 540. The dedicated logic cell 500 comprises a second set of function generators having a fifth function generator 530, a sixth function generator 532, a seventh function generator 534, and an eighth function generator 536 where each function generator has four inputs for receiving B[0:3] 505-508 and an output connected to the 4:1 multiplexer 550. A third multiplexer 560 has a first input connected to the output of the first 4:1 multiplexer 540, a second input connected to the output of the second 4:1 multiplexer 550, and a third input connected to the dedicated line C4 514 and an output 570.

[0058] FIG. 6 shows a logic diagram illustrating the third implementation of a dedicated logic cell 600 employing four 2:1 multiplexers with a common select line. A dedicated line 610 CO functions as a common select line that runs through all four 2:1 multiplexers 640, 642, 644 and 646. The dedicated logic cell 600 comprises a first set of function generators having a first function generator 620, a second function generator 622, a third function generator 624, and a fourth function generator 626 where each function generator has four inputs for receiving A[0:3] 601-604. The dedicated logic cell 600 comprises a second set of function generators having a fifth function generator 630, a sixth function generator 632, a seventh function generator 634, and an eighth function generator 636 where each function generator has four inputs for receiving B[0:3] 605-608. A first 2:1 multiplexer 640 has a first input for receiving the A[O] 601 and a second input for receiving the B[O] 605, and generating an OUT[O] 650. A second 2:1 multiplexer 642 has a first input for receiving the A[I] 602 and a second input for receiving the B[I] 606, and generating an OUT[I] 652. A third 2:1 multiplexer 644 has a first input for receiving the A[2] 603 and a second input for receiving the B [2] 607, and generating an out[2] 654. A fourth 2:1 multiplexer 646 has a first input for receiving the A[3] 604 and a second input for receiving the B[3] 607, and generating an OUT[3] 656.

[0059] FIG. 7 is a logic diagram illustrating the fourth implementation of using eight dedicated lines in large multiplexers circuit 700. The eight dedicated lines, CO 710, Cl 711, C2 712, C3 713, C4 714, C5 715, C6 716, and C7 717, serve as select lines or control lines for multiplexers 720, 730, 740, and 750. The first multiplexer 720 has first inputs for receiving A[0:3] 701-704 and second inputs for receiving B[0:3] 705-708. The second multiplexer 730 has first inputs for receiving A[0:3] 701-704 and second inputs for receiving B[0:3] 705-708. The dedicated lines CO 710, Cl 711, and C2 712 function as select lines SO, Sl, and S2, respectively, for both the first and second multiplexers 720 and 730. The three select lines SO, Sl, and S3 provide the capability to the first and second multiplexers 720 and 730 to function as 8:1 multiplexers, where one of the eight inputs will be selected for sending to the output. Two multiplexer decode logics 730 and 740 operate to decode the inputs C3 713, C4 714, C5 715, C6 716, and Cl 111. The dedicated lines C3

713, C4 714, C5 715, C6 716, C7 717 function as select lines S3, S4, S5, S6, S7, respectively, for both the two multiplexer decode logics 730 and 740. A first chaining logic 760 has a first input connected to the output of the first 8:1 multiplexer 720, a second input connected to a previous multiplexer chaining multiplexer (not shown), a third input connected to the output of the first multiplexer decode logic 740, and an output. A second chaining logic 770 has a first input connected to the output of the second 8:1 multiplexer 730, a second input connected to the output of the first multiplexer chaining logic 760, a third input connected to the output of the second multiplexer decode logic 750, and an output. The combination of the eight dedicated lines, CO 710, Cl 711, C2 712, C3 713, C4

714, C5 715, C6 716, and C7 717, provide 256 inputs into the circuit 700 that function as a 256:1 multiplexer.

[0060] In FIG. 8, there is shown a logic diagram illustrating the fifth implementation of using dedicated lines as control lines in a configurable sequential circuit 800. A set of dedicated lines CO 810, Cl 811, C2 812, and C3 813, provide control signals to a set of sequential elements sharing the same set of controls signals that includes a reset (RST) signal, a clear (CLR) signal, a load enable (LDEN) signal, and a clock enable (CE) signal. In this embodiment, the configurable sequential circuit 800 comprises a first configurable sequential element 820, a second configurable sequential element 830, a third configurable sequential element 840, a fourth configurable sequential element 850, a fifth configurable sequential element 860, a sixth configurable sequential element 870, a seventh configurable sequential element 880, and an eight configurable sequential element 890. The first dedicated line CO 810 functions as a reset (RST) line, the second dedicated line Cl 811 functions as a clear (CLR) line, the third dedicated line C2 812 functions as a load enable (LDEN) line, and the dedicated line C3 813 functions as a clocking enable (CE) line. A clock signal 815 is also fed into each of the configurable sequential elements, 820, 830, 840, 850, 860, 870, 880 and 890.

[0061] The first configurable sequential element 820 has a first input for receiving IN[O], a second input for receiving a load data LD[O], and an output for generating an OUT[O]. When the LDEN signal 812 is asserted, the LD[O] line is active to load the data IN[O] into the first configurable sequential element 820 and generating the data to the OUT[O]. The second configurable sequential element 830 has a first input for receiving IN[I], a second input for receiving a load data LD[I], and an output for generating an OUT[I]. When the LDEN signal 812 is asserted, the LD[I] line is active to load the data IN[I] into the second configurable sequential element 830 and generating the data to the OUT[I]. The third configurable sequential element 840 has a first input for receiving IN[2], a second input for receiving a load data LD[2], and an output for generating an OUT[2]. When the LDEN signal 812 is asserted, the LD[2] line is active to load the data IN[2] into the third configurable sequential element 840 and generating the data to the 0UT[2]. The fourth configurable sequential element 850 has a first input for receiving IN[3], a second input for receiving a load data LD[3], and an output for generating an OUT[3]. When the LDEN signal is asserted, the LD[3] signal 812 is active to load the data HST[3] into the fourth configurable sequential element 850 and generating the data to the OUT[3]. The fifth configurable sequential element 860 has a first input for receiving DSf[4], a second input for receiving a load data LD[4], and an output for generating an OUT[4]. When the LDEN signal 812 is asserted, the LD [4] line is active to load the data IN[4] into the fifth configurable sequential element 860 and generating the data to the 0UT[4]. The sixth configurable sequential element 870 has a first input for receiving IN[5], a second input for receiving a load data LD [5], and an output for generating an OUT[5]. When the LDEN signal 812 is asserted, the LD[5] line is active to load the data IN[5] into the sixth configurable sequential element 870 and generating the data to the OUT[5]. The seventh configurable sequential element 880 has a first input for receiving IN[6], a second input for receiving a load data LD[6], and an output for generating an OUT[6]. When the LDEN signal 812 is asserted, the LD [6] line is active to load the data IN[6] into the seventh configurable sequential element 880 and generating the data to the OUT[6]. The eighth configurable sequential element 890 has a first input for receiving IN[7], a second input for receiving a load data LD[7], and an output for generating an OUT[7]. When the LDEN signal 812 is asserted, the LD [7] line is active to load the data IN[7] into the eighth configurable sequential element 890 and generating the data to the OUT[7]. [0062] FIG. 9 is a logic diagram illustrating the sixth implementation of a programmable logic circuit 900 that shares dedicated lines as control lines among multiple macro blocks. A set of eight dedicated lines CO 910, Cl 911, C2 912, C3 913, C4 914, C5 915, C6 916, C7 917, operate as control lines for larger functional macro blocks such as memory, multiplier and other such macro blocks such that a set of logic and routing blocks provide inputs, outputs and control signals. The eight dedicated lines CO 910, Cl 911, C2 912, C3 913, C4 914, C5 915, C6 916, C7 917 serve as common control signals that are shared among a first macro block 920 and a second macro block 930. The eight dedicated lines C0-C7 910-917 are connected to the first macro block 920 through a first dedicated logic cell 940, and is connected to the second macro block 930 through a third dedicated logic cell 960. The eight dedicated lines C0-C7 910-917 are connected to the first dedicated logic cell 940, a second dedicated logic cell 950, the third dedicated logic cell 960, and a fourth dedicated logic cell 970.

[0063] FIG. 10 is a flow diagram illustrating the process of programming a programmable logic circuit having at least one or more dedicated lines in a logic and routing block 200. At step 1010, the process 1000 reads a particular programmable logic design selected by a user. The process 1000 identifies logic structures for implementation of the selected design at step 1020. In a programmable logic circuit, a first dedicated logic cell in a first LRB receives a first set of dedicated lines at step 1030. Depending on the logic functions to be implemented, there are several options in connecting the first set of dedicated lines in the first dedicated logic cell in the first LRB. With a first option at step 1040, the first set of dedicated lines in the first dedicated logic cell in the first LRB are connected to a second dedicated logic cell in the same LRB. With a second option at step 1050, the first set of dedicated lines in the first dedicated logic cell in the first LRB are connected to a second LRB. With a third option at step 1060, the first set of dedicated logic cell in the first logic cell in the first LRB is stitched to a second set of dedicated lines for connection to a LRB that is either adjacent to the first LRB, or skip over an adjacent LRB to a non-contiguous LRB relative to the first LRB.

[0064] In FIG. 11, there is shown a logic diagram illustrating a dedicated logic structure 1100 in a two multiplexers scheme employing a first logic and routing cell (LRC) 1120 for port A and a second logic and routing cell 1170 for port B, a set of ILRC multiplexers 1105 connected to inputs of the first and second LRCs 1120 and 1170, and a set of OLRC multiplexers 1107 connected to outputs of the first and second LRCs 1120 and 1170. The first logic and routing cell 1120 for port A comprises four look-up tables (or functional generators, FGs) 1130, 11311, 1134, and 1136, a dedicated logic cell 1137, and two configurable registers 1138 and 1139. The first logic and routing cell 1120 couples between four ILRC multiplexers 1110, 1112, 1114, and 1116, and two OLRC multiplexers 1150 and 1152. The first ILRC multiplexer 1110 feeds into the first look-up table 1130, the second ILRC multiplexer 1112 feeds into the second look-up table 1132, the third ILRC multiplexer 1114 feeds into the third look-up table 1134, and the fourth ILRC multiplexer 1116 feeds into the fourth look-up table 1136. The four look-up tables 1130, 1132, 1134, and 1136 are coupled to the dedicated logic cell 1137. The dedicated logic cell 1137 is configurable to perform selected functionalities depending on a product specification. The first OLRC multiplexer 50 selects between a first input generated from the dedicated logic cell 1137 or the second input generated from the first configurable register 1138 in generating an output. The second OLRC multiplexer 1152 selects between a first input generated from the dedicated logic cell 1137 or the second input generated from the second configurable register 1139 in generating an output.

[0065] The second logic and routing cell 1170 for port B comprises four look-up tables (or functional generators, FGs) 1180, 1182, 1184, and 1186, a dedicated logic cell 1187, and two configurable registers 1188 and 1189. The second logic and routing cell 1170 couples between four ILRC multiplexers 1160, 1162, 1164, and 1166, and two OLRC multiplexers 1190 and 1192. The first ILRC multiplexer 1160 feeds into the first look-up table 1180, the second ILRC multiplexer 1162 feeds into the second look-up table 1182, the third ILRC multiplexer 1164 feeds into the third look-up table 1184, and the fourth ILRC input multiplexer 1166 feeds into the fourth look-up table 1186. The four look-up tables 1180, 1182, 1184, and 1186 are coupled to the dedicated logic cell 1187. The dedicated logic cell 1187 is configurable to perform selected functionalities depending on a product specification. The first OLRC multiplexer 1190 selects between a first input generated from the dedicated logic cell 1187 or the second input generated from the first configurable register 1188 in generating an output. The second OLRC multiplexers 1192 select between a first input generated from the dedicated logic cell 1187 or the second input generated from the second configurable register 1189 in generating an output.

[0066] One of ordinary skill in the art should recognize that FIG. 11 is intended as one embodiment such that other variations or modifications can be practiced without departing from the spirits of the present invention, e.g. a different number of E-RC multiplexers rather than four, or a different number of OLRC multiplexers rather than two. [0067] In FIG. 12, there is shown a logic diagram illustrating a programmable logic chip 1200 constructed with multiple levels (or columns) of DLCs 1220, 1240, 1260, and 1280. One column of dedicated logic cell comprises a plurality of dedicated logic cells and connection lines to implement a logic function, such as an adder, a subtractor, an add- subtractor with add-sub control, an accumulator, registers, and multiplexers. [0068] The programmable logic chip 1200 comprises a first logic and routing block 1202, a second logic and routing block 1204, a third logic and routing block 1206, a fourth logic and routing block 1208, a fifth logic and routing block 1210, and a sixth logic and routing block 1212. Each of the logic and routing block comprises four dedicated logic cells arranged in a square format. The first logic and routing block 1202 comprises a first dedicated logic cell 1221, a second dedicated logic cell 1222, a third dedicated logic cell 1241, and a fourth dedicated logic cell 1242. Each dedicated logic cell comprises two logic and routing cells. The first dedicated logic cell 1221 has a first logic and routing cell 1221- 1 and a second logic and routing cell 1221-2, the second dedicated logic cell 1222 has a first logic and routing cell 1222-1 and a second logic and routing cell 1222-2, the third dedicated logic cell 1241 has a first logic and routing cell 1241-1 and a second logic and routing cell 1241-2, and the fourth dedicated logic cell 1242 has a first logic and routing cell 1242-1 and a second logic and routing cell 1242-2.

[0069] The second logic and routing block 1204 comprises a first dedicated logic cell 1223, a second dedicated logic cell 1224, a third dedicated logic cell 1243, and a fourth dedicated logic cell 1244. The first dedicated logic cell 1223 has a first logic and routing cell 1223-1 and a second logic and routing cell 1223-2, the second dedicated logic cell 1224 has a first logic and routing cell 1224-1 and a second logic and routing cell 1224-2, the third dedicated logic cell 1243 has a first logic and routing cell 1243-1 and a second logic and routing cell 1243-2, and the fourth dedicated logic cell 1244 has a first logic and routing cell 1244-1 and a second logic and routing cell 1244-2.

[0070] The third logic and routing block 1206 comprises a first dedicated logic cell 1225, a second dedicated logic cell 1226, a third dedicated logic cell 1245, and a fourth dedicated logic cell 1246. The first dedicated logic cell 1225 has a first logic and routing cell 1225-1 and a second logic and routing cell 1225-2, the second dedicated logic cell 1226 has a first logic and routing cell 1226-1 and a second logic and routing cell 1226-2, the third dedicated logic cell 1245 has a first logic and routing cell 1245-1 and a second logic and routing cell 1245-2, and the fourth dedicated logic cell 1246 has a first logic and routing cell 1246-1 and a second logic and routing cell 1246-2.

[00711 The fourth logic and routing block 1208 comprises a first dedicated logic cell 1261, a second dedicated logic cell 1262, a third dedicated logic cell 1281, and a fourth dedicated logic cell 1282. The first dedicated logic cell 1261 has a first logic and routing cell 1261-1 and a second logic and routing cell 1261-2, the second dedicated logic cell 1262 has a first logic and routing cell 1262-1 and a second logic and routing cell 1262-2, the third dedicated logic cell 1281 has a first logic and routing cell 1281-1 and a second logic and routing cell 1281-2, and the fourth dedicated logic cell 1282 has a first logic and routing cell 1282-1 and a second logic and routing cell 1282-2.

[0072] The fourth logic and routing block 1210 comprises a first dedicated logic cell 1261, a second dedicated logic cell 1262, a third dedicated logic cell 1283, and a fourth dedicated logic cell 1284. The first dedicated logic cell 1263 has a first logic and routing cell 1263-1 and a second logic and routing cell 1263-2, the second dedicated logic cell 1264 has a first logic and routing cell 1264-1 and a second logic and routing cell 1264-2, the third dedicated logic cell 1283 has a first logic and routing cell 1283-1 and a second logic and routing cell 1283-2, and the fourth dedicated logic cell 1284 has a first logic and routing cell 1284-1 and a second logic and routing cell 1284-2.

[0073] The sixth logic and routing block 1212 comprises a first dedicated logic cell 1265, a second dedicated logic cell 1266, a third dedicated logic cell 1285, and a fourth dedicated logic cell 1286. The first dedicated logic cell 1265 has a first logic and routing cell 1265-1 and a second logic and routing cell 1265-2, the second dedicated logic cell 1266 has a first logic and routing cell 1266-1 and a second logic and routing cell 1266-2, the third dedicated logic cell 1285 has a first logic and routing cell 1285-1 and a second logic and routing cell 1285-2, and the fourth dedicated logic cell 1286 has a first logic and routing cell 1286-1 and a second logic and routing cell 1286-2.

[0074] The first column (or level 0) of logic and routing block 1220 comprises the first dedicated logic cell 1221, the second dedicated logic cell 1222, the third dedicated logic cell 1223, the fourth dedicated logic cell 1224, the fifth dedicated logic cell 1225, and the sixth dedicated logic cell 1226. The second column (or level 1) of logic and routing block 1240 is positioned adjacent to the right side of the first column of logic and routing block 1220. The second column of logic and routing block 1240 comprises the first dedicated logic cell 1241, the second dedicated logic cell 1242, the third dedicated logic cell 1243, the fourth dedicated logic cell 1244, the fifth dedicated logic cell 1245, and the sixth dedicated logic cell 1246. The third column (or level 2) of logic and routing block 1260 is positioned adjacent to the right side of the second column of logic and routing block 1240. The third column of logic and routing block 1260 comprises the first dedicated logic cell 1261, the second dedicated logic cell 1262, the third dedicated logic cell 1263, the fourth dedicated logic cell 1264, the fifth dedicated logic cell 1265, and the sixth dedicated logic cell 1266. The fourth column (or level 3) of logic and routing block 1280 is positioned adjacent to the right side of the third column of logic and routing block 1260. The fourth column of logic and routing block 1280 comprises the first dedicated logic cell 1281, the second dedicated logic cell 1282, a third dedicated logic cell 1283, the fourth dedicated logic cell 1284, the fifth dedicated logic cell 1285, and the sixth dedicated logic cell 1286.

[0075] In FIG. 13, there is shown a block diagram illustrating an example in performing a logic operation in a single column of dedicated logic cells 1300. The single column of dedicated logic cells 1300 comprises a first dedicated logic cell 1310 having a first LRC 1311 and a second LRC 1312, a second dedicated logic cell 1320 having a first LRC 1321 and a second LRC 1322, a third dedicated logic cell 1330 having a first LRC 1331 and a second LRC 1332, and a fourth dedicated logic cell 1340 having a first LRC 1341 and a second LRC 1342. A first set of inputs, X[3:0], X[7:4], X[l l:8], and X[15:12] are fed into ports A in the first dedicated logic cell 1310, a second dedicated logic cell 1320, a third dedicated logic cell 1330, and a fourth dedicated logic cell 1340, respectively. A second set of inputs, Y[3:0], Y[7:4], Y[ll:8], and Y[15:12] are fed into ports B in the first dedicated logic cell 1310, a second dedicated logic cell 1320, a third dedicated logic cell 1330, and a fourth dedicated logic cell 1340, respectively. The single column of dedicated logic cells 1300 performs a logic operation for the A and B inputs, represented as A (dlcop) B, where the symbol "dlcop" denotes a DLC operation. Examples of the DLC operation include addition (A + B), subtraction (A- B), multiplication (A * B), division (A / B), NOR A, NOR B, or other type of logic operations. The single column of dedicated logic cells 1300 couples to a set of ELRC multiplexers 1350 at the inputs and couples to a set of OLRC multiplexers 1360 at the outputs.

[0076] In FIG. 14, there is shown a logic diagram illustrating a first example of a programmable logic circuit 1400 employing local connections between different levels of DLCs. In this example, the programmable logic circuit 1400 has local connections from a level L 1410 to a level L+ 1 1420 connection. The level L 1410 represents a first column of DLCs 1420, 1422, 1424, and 1426, where each DLC contains two LRCs. The level L 1450 represents a second column of DLCs 1460, 1462, 1464, and 1466, where each DLC contains two LRCs. The level L 1410 has a set of OLRCs 1430 connected to a set of DLRC 1470 in the level L + 1.

[0077] The programmable logic circuit 1400 has a set of offset parameters as show in FIG. 14 for feeding the OLRC multiplexer 1430 in the level L 1410 into the DLRC multiplexer 1470 in the level L + 1 1420. The DLRC 1470 in the level L + 1 1420 comprises a first E,RC multiplexer 1510, a second DLRC multiplexer 1512, a third DLRC multiplexer 1514, and a fourth DLRC multiplexer 1516, where all four of the DLRC multiplexers 1510, 1512, 1514, and 1516 are coupled to a logic and routing cell 1520. The first DLRC multiplexer 1510 has an offset of (ΔX, ΔY) = (-1, 0), the second DLRC multiplexer 1512 has an offset of (ΔX, ΔY) = (-1, 1), the third DLRC multiplexer 1514 has an offset of (ΔX, ΔY) = (-1, -1), and the fourth ILRC multiplexer 1516 has an offset of (ΔX, ΔY) = (-1, 1). The configuration of the local connections for the first, second, third, and fourth DLRC multiplexers 1510, 1512, 1514, and 1516 are shown in FIG. 15, e.g. a diagonal connection line 1440 connects between a port A in level L 1410 to a port B in level L + 1 1420, and a diagonal connection line 1442 connects between a port B 1410 in level L to a port A in level L + 1 1420.

[0078] Referring now to FIG. 16, there is shown a logic diagram illustrating a second example of a programmable logic circuit 1600 employing local connections between different levels of DLCs. The programmable logic circuit 1600 comprises a first input logic and routing cell multiplexer 1610, a second input logic and routing cell multiplexer 1620, a third input logic and routing cell multiplexer 1630, and a fourth input logic and routing cell multiplexer 1640, where all four of the input and logic and routing cell multiplexers 1610, 1620, 1630, and 1640 are coupled to logic and routing cell 1650. The first ELRC multiplexer 1610 has an offset of (ΔX, ΔY) = (-1, O)₅ the second ILRC multiplexer 1620 has an offset of (ΔX, ΔY) = (-1, 1), the third ELRC multiplexer 1630 has an offset of (ΔX, ΔY) = (-1, -1), and the fourth ILRC multiplexer 1640 has an offset of (ΔX, ΔY) = (-1, 2). One of skill in the art should recognize that the programmable logic circuit 1600 illustrates that local connections can be made from any level of DLCs or any offset from the current LRC. For example, the input logic and routing cell multiplexer 1640 has a fourth input that is generated from an offset of (-3, 1) 1642 that represents a feedback connection. [0079] Referring now to FIG. 17, there is shown an architectural diagram illustrating a programmable logic circuit 1700 with stitchings between output logic and routing cells. When a first OLRC does not have a connection an ELRC, the first OLRC may be able to stitch to a second OLRC for making a local connection to the ILRC. The programmable logic circuit 1700 has a first OLRC 1710 with stitchings from the top, the bottom, the left, and the right side relative to the first OLRC 1710. The first OLRC 1710 has a first input connected to a second OLRC 1720, a second input connected to a third OLRC 1730, a third input connected to a fourth OLRC 1740, and a fourth input connected to a fifth OLRC 1750. When the first OLRC 1710 serves as reference point, the relative positions of the other OLRCs are as follows: the second OLRC 1720 has an offset of (+2, 0) that stitches to the first OLRC 1710; the third OLRC 1730 has an offset of (-2, 0) that stitches to the first OLRC 1710, the fourth OLRC 1740 has an offset of (+2, 0) that stitches to the first OLRC 1710, and the fifth OLRC 1750 has an offset of (-2, 0) that stitches to the first OLRC 1710. The configuration in the programmable logic circuit 1700 allows lines from other levels to connect from one OLRC to a ILRC through another OLRC. The local connections can be made from any levels including horizontal levels and vertical levels. [0080] In FIG. 18, there is shown a block diagram illustrating a programmable logic circuit 1800 with two DLCs so that outputs (OLRC) from a first DLC 1810 at level -L makes local connections to inputs (ELRC) in a second DLC 1820 at level 0. The first DLC 1810 in the level -L 1810 comprises a port A 1820 and a port B 1830 where the port A 1820 has YO 1822 and Yl 1824 outputs, and the port B 1830 has YO 1832 and Yl 1834 outputs. The second DLC 1850 in the level 0 1850 comprises the port A 1860 and the port B 1870 where the port A 1860 has an input AO 1862, an input Al 1864, an input A2 1866, and an input A3 1868, while the port B 1870 has an input BO 1872, an input Bl 1874, an input B2 1876, and an input B3 1878. The local connections between the first DLC 1810 and the second DLC 1820 are made as follows: AO - Y 0 (-L, 0), Al - Yl (-L, 0), A2 - YO (-L, 1), A3 - Yl (-L, 1), BO - YO (-L, 0), Bl - Yl (-L, 0), B2 - YO (-L, -1), and B3 - Yl (- L, -1).

[0081] FIG. 19 is a block diagram illustrating a programmable logic circuit 1900 with local connections for performing a logic operation of A + B + C. The programmable logic circuit 1900 comprises a first column of DLC 1910 and a second column of DLC 1920. The first column of DLC 1900 receives a first input A 1912 and a second input B 1914 to perform a logic operation of A + B. The second column of DLC 1920 receives an input C 1922 and outputs from the first column of DLC 1910 to perform the logic operation of A + B + C to generate an output 130 ofA + B + C. One of skill in the art should recognize that the columns of DLCs can be altered to perform other type of logical operations, such as add, subtract, and multiply. The number of inputs can be represented generally by the symbol n, where n can be either 1, 2, 3, 4, other any other integer number to suit a particular product design.

[0082] Turning now to FIG. 20, there is shown a block diagram illustrating a programmable logic circuit 2000 with local connections for fan out, a horizontal offset for a local connection from one column to another column, and a vertical offset for a local connection from one row to another row. The programmable logic circuit 2000 comprises a plurality of horizontal columns: a level or column L, a column L + 1, a column L + 2, and a plurality of vertical rows: a row M, a row M + 1, a row M + 2, a row M + 3, and a row M + 4. There are three types of local connections that are shown in this embodiment where an OLRC 2020 serves as a reference point. First, designated as A connection that shows fan out local connections, the OLRC 2020 in the column L makes point-to-point local connections from the OLRC 2020 in the row M/the column L to several ILRCs in the row M/column L + 1, i.e. an ELRC 2030, an ILRC 2032, and an ILRC 2036 in the column L + 1. Second, designed as B connection that shows a horizontal offset, the OLRC 2020 makes a point-to-point local connection from the OLRC 2020 in the row M/the column L to an DLRC 2050 in the column L + 2. Third, designated as C connection that shows a vertical offset, the OLRC 2020 makes a point-to-point local connection to an ILRC 2056 in the row M + 3/the column L + 2.

[0083] In FIG. 21A, there is shown a block diagram illustrating a programmable logic circuit 2100 that employs inverting buffers or non-inverting buffers. An inverter buffer is represented by an inverter, as shown in FIG. 2 IB, while a non-inverting buffer is represented by an inverter but without the inverting node, as shown in FIG. 21C. The OLRC 2120 is again used as a reference point. The OLCR 2120 makes a local connection to an ILRC 2150 through a buffer 2120, which can be either an inverting buffer or a non-inverting buffer. One of ordinary skill in the art should recognize that other variations of buffering a local connection can be practiced without departing from the spirits of the present invention. [0084] FIG. 22 is a flow diagram illustrating the process 2200 for programming a programmable logic circuit with local connections between dedicated logic cells. At step 2210, the process 2200 synthesizes or reads a particular product design. The process 2200 creates a dedicated logic cells structure suitable for the selected product design at step 2220. At step 2230, the process 2200 identifies the critical path of the dedicated logic cells structure. Local connections between the dedicated logic cells can be made using various methods. In one method at step 2240, local connections are made between the dedicated logic cells for the critical path by connecting an OLRC multiplexer in a first dedicated logic cell at a first level to an ILRC multiplexer in a second dedicated logic cell at a second level. In another method at step 2250, where there are no direct connection from one OLRC to an ILRC, local connections are made between dedicated logic cells for critical path by stitching a second OLRC multiplexer feeding into a first input of a first OLRC multiplexer. The first OLRC multiplexer and the second OLRC multiplexer can reside in the same level of DLC or from another level of DLC. Additional stitching can be made from other OLRC multiplexers feeding into inputs of the first OLRC multiplexers in a first DLC as described at step 2260.

[0085] FIG. 23 is an architectural diagram illustrating a pair of dedicated logic cells 2300 comprising of four types of components: a configurable logic function or a look-up table (LL), a dedicated logic function (LD), a sequential logic function (LS), and a control logic function (LC). A first dedicated logic cell DCLO 2310 has a first LRC 2320 and a second LRC 2330 where the first LRC 2320 comprises a first configurable logic function 2322, a dedicated logic function 2324, a sequential logic function 2326, while the second LRC 2330 comprises a second configurable logic function 2332, and a sequential logic function 2336. A second dedicated logic cell DCLl 2350 has a first LRC 2360 and a second LRC 2370 where the first LRC 2360 comprises a first configurable logic function 2362, a dedicated logic function 2364, a sequential logic function 2366, while the second LRC 2370 comprises a second configurable logic function 2372, a control logic function 2374, and a sequential logic function 2376. A logic function can be implemented by using one or more dedicated logic cells in which a selected combination of logic circuits (i.e. a configurable logic function, a dedicated logic function, a sequential logic function, and/or a control logic function) are configured to perform that function.

[0086] Turning now to FIG. 24, there is shown a logic diagram illustrating the configurable logic function (LL structure) circuit 522 in the dedicated logic cell 500. The configurable logic function circuit 522 is designed to perform one of the following functions: (1) a four 4-input look-up table, (2) a one 6-input look-up table, or (3) a 4-to-l multiplexer. In the first function that operates as the four 4-input look-up table, the dedicated logic cell 2400 has four look-up tables, a first look-up table 2410, a second lookup table 2420, a third look-up table 2430, and a fourth look-up table 2440. Each of the first, second, third, and fourth look-up tables 2410, 2420, 2430, and 2440 has inputs for receiving four inputs of 10, II, 12, and 13 to constitute a total of six inputs. In the second function that operates as one 6-input look-up table, a fifth input 14 from a multiplexer 2450 and a sixth input 15 from a multiplexer 2460 are added to the four inputs of 10, II, 12, and 13. In the third function that operates as a 4-to-l multiplexer, a multiplexer 2470 receives a first input from an output Y4(0) of the first look-up table 2410, a second input from an output Y4(l) of the second look-up table 2420, a third input from an output Y4(2) of the third look-up table 2430, and a fourth input from an output Y4(3) of the fourth look-up table 2440. Two select lines of SO and Sl in the multiplexer 2470 select from among one of the four inputs, Y4(0), Y4(l), Y4(2), and Y4(3) to generate an output Y6.

[0087] In FIG. 25, there is shown a logic diagram illustrating the sequential logic function circuit 526 (LS structure) in the dedicated logic cell 500. The sequential logic function circuit 526 comprises a 4-to-l multiplexer 2510, a 2-to-l multiplexer 2520, and a configurable flop 2530. The 4-to-l multiplexer 2510 has a first input 000 connected a data input (DIN) 2502, a second input 001 connected to a load data (LDDATA) 2504, a third input connected to a Vcc 2506, and a fourth input connected to a ground 2508. [0088] The dedicated logic cell 2500 has four control signals, a loadable (LD) register signal 2514, a synchronous clear signal (CLR) 2516, a synchronous SET signal 2518, and a data enable (DEN) 2522. The configurable flop 2530 can be configured to function either as a latch, a positive latch, a negative latch, a rising edge triggered flop, or a fallen edge triggered flop. As a whole, the sequential logic function circuit 2326 provides the flexibility to build a register (i.e., configured as one of the logic circuits, as a latch, a positive latch, a negative latch, a rising edge triggered flop, or a fallen edge triggered flop) with any combination of the four control signals, the loadable register signal 2514, the synchronous clear signal 2516, the synchronous SET signal 2518, and the data enable signal 2522. For example, the sequential logic circuit 2326 can be configured as a loadable rising edge triggered flop with an asynchronous clear signal.

[0089] Optionally, the four control signals, the loadable register signal 2514, the synchronous clear signal 2516, the synchronous SET signal 2518, and the data enable 2522 can be driven by dedicated lines.

[0090] FIG. 26 is shown a logic diagram illustrating the dedicated logic function circuit 524 (LD structure) in the dedicated logic cell 2300. The dedicated logic function circuit 2324 comprises a first multiplexer 2610, a second multiplexer 2620, and a third multiplexer 2630. The first multiplexer 2610 has a first input 2612 encoded as 00 for receiving A signals, a second input 2614 encoded as 01 for receiving a 6-input look-up table, a third input 2616 encoded as 10 for receiving an arithmetic function, an adder function, or an accumulator function, and a fourth input 2618 encoded as 11 for receiving a multiplication function. The second multiplexer 2620 has a first input 2622 encoded as 00 for receiving a 6-input look-up table, a second input 2624 encoded as 01 for receiving B signals, a third input 2626 encoded as 10 for receiving a 2-inρut look-up table 2612 which further receives inputs of A signals and B signals, and a fourth input 2628 encoded as 11 for receiving a shift data.

[0091] The third multiplexer 2630 has a first input connected to an output of the first multiplexer 2610, a second input connected to an output of the second multiplexer 2620, and an output 2636. A pair of multiplexer select lines, DLCOPl 2642 and DLCOP2 2644, is connected to both the first multiplexer 2610 and the second multiplexer 2620. In the first multiplexer 2610, the DLCOPl 2642 and the second DLCOP2 2644 select between the first input 2612, the second input 2614, the third input 2616, or the fourth input 2618 for generating to the output 2619. In the second multiplexer 2620, the DLCOPl 2642 and the second DLCOP2 2644 selects between the first input 2622, the second input 2624, the third input 2626, or the fourth input 2628 for generating to the output 2629. A multiplexer select line DLCOPO 2640 is connected to the third multiplexer 2630 for selecting between the first input 2632 or the second input 2634 for generating to the output 2636. [0092] The dedicated logic function circuit 2600 is capable of selecting between different operations that are available which feed into the first multiplexer 2610 and the second multiplexer 2620. For example, the dedicated logic function circuit 2600 can select to perform an adder function and a shift function. By selecting a desirable function, the dedicated logic function circuit 2600 can be used to build an arithmetic unit. [0093] Optionally, the three multiplexer select lines, the DLCOPO 2640, the DLCOPl 2642, and the DLCOP2 2644, can be driven from dedicated lines. The DLCOPO 2640, the DLCOPl 2642, and the DLCOP2 2644 can either be static or dynamically configurable, which configures the dedicated logic function circuit 2600 into an arithmetic logic unit (ALU) functionality.

[0094] Turning now to FIG. 27, there is shown an alternative embodiment illustrating a logic diagram of a dedicated logic function circuit 2700 that operates as a propagate/generate logic to perform the function of a look-ahead sum or as a priority multiplexer. The dedicated logic function circuit 2700 has a first input for receiving A 2702 from a configurable logic function (LL) and a second input for receiving B 2704 from a configurable logic function (LL). Each of the incoming signals A 2702 and B 2704 is a 4-bit wide signal. The dedicated logic function circuit 2700 comprises a configurable propagate function circuit 2706, a configurable generate function circuit 2708, and a look-ahead sum generator 2750. The configurable propagate function circuit 2706 has an OR gate 2710, an inverter 2730, and a multiplexer 2740, while the configurable generate function circuit 2708 has an AND gate 2720. The input A 2702 is fed into the OR gate 2710 and the AND gate 2720. The input B 2702 is fed into the AND gate 2720 and the inverter 2730. The multiplexer 2740 has a first input connected to an output of the OR gate 2710 and a second input connected to an output of the inverter 2730. A configurable bit (or select line), Arith or Priority Mux 2742, selects between the first input or the second input of the multiplexer 2740 and generates an output p[3:0] 2744. The AND gate 2720 generates an output, g[3:0] 2722. The look-ahead sum generator 2750 has a first input connected to the p[3:0] 2744 output from the multiplexer 2740, and a second input connected to the g[3:0] 2722 output from the AND gate 2720, with a carry-in signal 2752 and a carry-out signal 2754. [0095] When the dedicated logic function circuit 2700 operates as a sum circuit, the logic equation is represented as follows (note that the sum is generated from Cin): p = a θ b g = a « b

[0096] When the dedicated logic function circuit 2700 operates as a priority multiplexer, the logic equation is represented as follows (note that the carry-out is mux-out). p = a g = a * b

[0097] The equation for the configurable generate carry out is shown as follows: configurable generate carry out = g[3] + p[3] g[2] + p[3] g[2] g[l] + p[3] [g2] g[l] g[0] + p[3] p[2] p[l] p[0] in Cin.

[0098] A sample priority multiplexer 2800 as described with respect to the dedicated logic function circuit 2700 is shown in FIG. 28 for use in a carry-ahead generation scheme. The priority multiplexer 2800 comprises a first multiplexer 2810, a second multiplexer 2820, a third multiplexer 2830, and a fourth multiplexer 2840. A first select line SO 2816 in the first multiplexer 2810 selects between a first input 2812 or a second input 10 2814 for generating an output 2818. A second select line Sl 2826 in the second multiplexer 2820 selects between a first input 2822 or a second input Il 2824 for generating an output 2828. A third select line S2 2836 in the third multiplexer 2830 selects between a first input 2832 or a second input 12 2834 for generating an output 2838. A fourth select line S3 2846 in the fourth multiplexer 2840 selects between a first input 2842 or a second input 13 2844 for generating an output 2848. As a command enters into the priority multiplexer 2800, the first select line SO in the first multiplexer 2810 selects whether or not to execute the command. The remaining multiplexers 2820, 2830, and 2840 perform similar functions as the signal propagates through the priority multiplexer 2800. One application in the use of the priority multiplexer 2800 is for arbitration of multiple requests. [0099] Turning now to FIG. 29, there is shown a state diagram 2900 illustrating a logic diagram of a control logic function circuit (LC structure) 2934 in the dedicate logic cell 2900. A control logic function 2910 obtains data-in from a lower control logic function (or a lower DLC) 2920 through dedicated lines 2925 and sends data-out to an upper control logic function (or an upper DLC) 2930. One functional objective of the control logic function circuit 534 is to minimize the delay from the lower LC 2920 to the upper LC 2930. To minimize the delay, the LC 2910 performs a carry look-ahead for various functions including arithmetic/priority multiplexer, a multiplexer, and a 2-input function. Table 1 below provides a chart of DLC carry signals for the different logic operations.

DLC Carry Signals

where Y<4> represents the ZL<0> output of DLCl, and I<4> represents the input to DLCl.

The control logic function 2910 sends control signals 2965 to a sequential logic function 2960. In addition, the control logic function 2910 has a bi-directional communication, signal paths 2941 and 2942, with a dedicate logic function 2940. A set of dedicated lines are connected from the signal path 2941 to a dedicated logic function 2950, which in turn has a signal path 2951 to the control logic function 2910.

An example of a control logic function circuit 3000 is described in FIG. 30. In this example, there are four types of operations: an arithmetic operation - A, a multiplexer - M₅ a shift - S, and a look-up table - L. The control logic function circuit 3000 comprises a first multiplexer 3010, a second multiplexer 3020, and a third multiplexer 3030. The third multiplexer 3030 has a first input coupled to an output of the first multiplexer 3010 and a second input coupled to an output of the second multiplexer 3020, an output 3040, and a carry-select signal 3035. If the data-in from a lower LC to L(O) 3011 is 0 in the first multiplexer3010 , the result is pre-calculated, or if the data-in from the lower LC to L(I) 3021 is 1 in the second multiplexer 3020, the result is pre-calculated. If the data-in from a lower LC to S(O) 3012 is 0 in the first multiplexer3010 , the result is pre-calculated, or if the data-in from the lower LC to S(I) 3022 is 1 in the second multiplexer 3020, the result is pre- calculated. If the data-in from a lower LC to M(O) 3013 is 0 in the first multiplexer3010 , the result is pre-calculated, or if the data-in from the lower LC to M(I) 3023 is 1 in the second multiplexer 3020, the result is pre-calculated. If the data-in from a lower LC to A(O) 3014 is 0 in the first multiplexer3010 , the result is pre-calculated, or if the data-in from the lower LC to A(I) 3024 is 1 in the second multiplexer 3020, the result is pre-calculated. The term to "pre-calculate the result" means to pre-calculate the result of what would be for data out, whether case if the data-in is either 0 or if the data-out is 1.

[00100] The LC 2910 sends signals through dedicated control lines 2945 to a dedicated logic cell 2940 and a dedicated logic cell 2950. The LC 2910 also sends controls 2965, such as data enable DEN, to a sequential logic cell 2960.

[00101] The collection of a configurable logic function (LL), a sequential logic function (LS), and a control logic function (LC) provides fundamental building blocks to design different programmable functionalities. Some of which are illustrated below. [00102] Referring now to FIG. 31, there is shown a logic circuit illustrating one implementation of a dedicated logic cell 3100 implemented as a 4 2-input function employing configurable logic functions and dedicated logic functions. The dedicated logic cell 3100 is capable of performing a variety of function, including an AND function, an OR function, an XOR function, and any 2-input function. The dedicated logic cell 3100 comprises a first configurable logic function (LL) 3110 for receiving inputs IA <3:0> 3102, a second configurable logic function (LL) 3120 for receiving inputs IB <3:0> 3104, and a portion of a dedicated logic function (LD) 3130. The first configurable logic function 3110 has a first look-up table 3112, a second look-up table 3114, a third look-up table 3116, and a fourth look-up table 3118. The second configurable logic function 3120 has a first look-up table 3122, a second look-up table 3124, a third look-up table 3126, and a fourth look-up table 3128. The portion of a dedicated logic function (LD) 3130 comprises a first 2-input look-up table 3132, a second 2-input look-up table 3134, a third 2-input look-up table 3136, and a fourth 2-input look-up table 3138. The first 2-input look-up table 3132 has a first input connected to the first look-up table 3112 in the first configurable logic function 3110, a second input connected to the first look-up table 3122 in the second configurable logic function 3120, and generating an output Y<0> 3140. The second 2-input look-up table 3134 has a first input connected to the second look-up table 3124 in the first configurable logic function 3110, a second input connected to the second look-up table 3124 in the second configurable logic function 3120, and generating an output Y<0> 3142. The third 2-input look-up table 3136 has a first input connected to the third look-up table 3126 in the first configurable logic function 3110, a second input connected to the third look-up table 3126 in the second configurable logic function 3120, and generating an output Y<2> 3144. The fourth 2-input look-up table 3138 has a first input connected to the fourth look-up table 3128 in the first configurable logic function 3110, a second input connected to the third look-up table 3126 in the second configurable logic function 3120, and generating an output Y<3> 3146.

[00103] In FIG. 32, there is shown a logic circuit illustrating another implementation of a dedicated logic cell 3200 implemented as a 4 2:1 multiplexer employing configurable logic functions and dedicated logic functions. The dedicated logic cell 3200 comprises a first configurable logic function (LL) 3210 for receiving inputs IA <3:0> 3202, a second configurable logic function (LL) 3220 for receiving inputs IB <3:0> 3204, and a dedicated logic function (LD) 3230. The first configurable logic function 3210 has a first look-up table 3212, a second look-up table 3214, a third look-up table 3216, and a fourth look-up table 3218. The second configurable logic function 3220 has a first look-up table 3222, a second look-up table 3224, a third look-up table 3226, and a fourth look-up table 3228. The dedicated logic function 3230 comprises a first multiplexer 3232, a second multiplexer 3234, a third multiplexer 3236, and a fourth multiplexer 3238. The first 2:1 multiplexer 3232 has a first input connected to the first look-up table 3212 in the first configurable logic function 3210, a second input connected to the first look-up table 3222 in the second configurable logic function 3220, and generating an output Y<0> 3240, with a select line SO 3231 generated from a dedicated line. The second 2:1 multiplexer 3234 has a first input connected to the second look-up table 3224 in the first configurable logic function 3210, a second input connected to the second look-up table 3224 in the second configurable logic function 3220, and generating an output Y<0> 3242, with the select line SO 3231 generated from a dedicated line. The multiplexer 3236 has a first input connected to the third look-up table 3226 in the first configurable logic function 3210, a second input connected to the third look-up table 3226 in the second configurable logic function 3220, and generating an output Y<2> 3244, with the select line SO 3231 generated from a dedicated line. The fourth multiplexer 3238 has a first input connected to the fourth look-up table 3228 in the first configurable logic function 3210, a second input connected to the third look-up table 3226 in the second configurable logic function 3220, and generating an output Y<3> 3246, with the select line SO 3231 generated from a dedicated line.

[00104] FIG. 33 is a block diagram illustrating 2 6-input functions of configurable logic functions 3300 with separate inputs having a first configurable logic function 3310 and a second configurable logic function 3320. A first set of dedicated lines 3330 from a DLC below are routed to the first configurable logic function 3310 and the second configurable logic function 3320. The first configurable logic function 3310 receives inputs A 3305 while the second configurable logic function 3320 receives inputs B 3315. [00105] In FIG. 34, there is shown a logic diagram illustrating a shift register 3400 which is capable to perform a loadable, resettable, or clearable function by using a combination of a configurable logic function 3410 and sequential logic functions 3420 and 3430. The configurable logic function 3410 has an input and an output, where the output of the configurable logic function 3410 is coupled to a first sequential logic circuit 3420 and a second sequential logic circuit 3430. The first sequential logic circuit 3420 generates a first register data output 3422, and the second sequential logic circuit 3430 generates a second register data output 3432.

[00106] FIG. 35 is a logic diagram illustrating an accumulator 3500 by employing configuration logic functions, a dedicate logic function, and sequential logic functions. The accumulator 3500 comprises a first configurable logic function 3510, a second configurable logic function 3520, a dedicated logic function 3530, a first sequential logic function 3540, and a second sequential logic function 3550. The first configurable logic function 3510 is coupled to a dedicated logic function 3530, which is in turn coupled to the first sequential logic function 3540 and the second sequential logic function 3550. The second configurable logic function 3520 is coupled to both the first sequential logic function 3540 and the second sequential logic function 3550.

[00107] FIG. 36 is a flow diagram 3600 illustrating a method for programming configuration bits for configuring one or more programmable function generators. At step 3610, a digital logic circuit is designed using Register Transfer Level (RTL) function description. At step 3620, the process 3600 synthesizes the circuit design to create a logical netlist. At step 3630, the process 3600 performs placement and route on the physical design of the logic circuit. At step 3640, the process 3600 programs or writes configuration bits into the configurable memory cells for selectors. At step 3650, the process 3600 writes into configurable memory cells in the programmable function generator for configuring memory cells to configure the programmable function generator as a combinational logic function generator, a sequential logic function generator, or a routing generator. At step 3660, the selector selects from one of its inputs depending on what has been written into the memory cells. At step 3670, the programmable function generator functions as a combinational logic function generator, a sequential logic function generator, or a routing function generator depending on the inputs from selector blocks as well as the global control signals. [00108] A software program or computer-implemented-method may be used for generating values for a plurality of configuration memory bits or cells in a function generator; and responsive to the values in the plurality of configuration memory cells, generating any functionality for a combinational function, a sequential function (including flip-flops and latches) or a routing function. For example, a multiplexer output in a configurable propagate function circuit can be selected by a design software dependent on user application. In another example, first and second logic and routing cells are configured through the automatic software generation of configuration bits to produce a desirable dedicated logic cell structure. Furthermore, the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function can be configured automatically by software programming of configuration bits and can be detected from a user design Verilog file.

[00109] Those skilled in the art can now appreciate from the foregoing description that the broad techniques of the embodiments of the present invention can be implemented in a variety of forms. Therefore, while the embodiments of this invention have been described in connection with particular examples thereof, the true scope of the embodiments of the invention should not be so limited since other modifications, whether explicitly provided for by the specification or implied by the specification, will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.

Claims

CLAIMS WE CLAIM:

1. A programmable logic structure, comprising: a first logic and routing block; a second logic and routing block; and first one or more dedicated lines extending through the first logic and routing block and the second logic and routing block.

2. The programmable logic structure of Claim 1, wherein the first logic and routing block having a first dedicated logic cell comprises: a first multiplexer having a first input connected to the one or more dedicated lines and a second input connected to a look-up table, the first multiplexer having at least one configurable lines for selecting from one of the two inputs and generating an output connected to a second dedicated logic cell in the first logic and routing block; and a second multiplexer having a first input connected to the one or more dedicated lines and a second input connected to the look-up table, the second multiplexer having at least one configurable lines for selecting from one of the two inputs and generating an output connected to the second logic and routing block.

3. The programmable logic structure of Claim 2, wherein the first logic and routing block having the first dedicated logic cell comprises: the first multiplexer having a third input connected to a Vdd, and a fourth input connected to a ground; and the second multiplexer having a third input connected to a Vdd, and a fourth input connected to a ground.

4. The programmable logic structure of Claim 1, wherein the first logic and routing block comprises: a first dedicated logic cell; a second dedicated logic cell, the first one or more dedicated lines connecting through the first dedicated logic cell and the second dedicated logic cell; a third dedicated logic cell; a fourth dedicated logic cell, second one or more dedicated lines connecting through the third dedicated logic cell and the fourth dedicated logic cell; and a switch box connected to the first, second, third, and fourth dedicated logic cells, the first one or more dedicated lines, and the second one or more dedicated lines.

5. The programmable logic structure of Claim 1, wherein the logic and routing block having a dedicated logic cell comprises: a first function generator having an input for receiving an input signal and an output; a first multiplexer having a first input connected to the output of the first function generator, a second input connected to a first dedicated line, and an output connected to a next dedicated logic cell; and a second multiplexer having an input for connecting to the output of the first function generator, a second input for connecting to the first dedicated line, and an output connected to the logic and routing block.

6. The programmable logic structure of Claim 1, wherein the logic and routing block having a dedicated logic cell comprises: a first function generator having inputs for receiving a plurality of input signals and an output; a second function generator having inputs for receiving the plurality of input signals and an output; a third function generator having inputs for receiving the plurality of input signals and an output; a fourth function generator having inputs for receiving the plurality of input signals and an output; and a 4:1 multiplexer having a first input connected to the output of the first function generator, a second input connected to the output of the second function generator, a third input connected to the output of the third function generator, a fourth input connected to the fourth function generator, a first select line feeding from a first dedicated line in the one or more dedicated lines, a second select line feeding from a second dedicated line in the one or more dedicated lines and an output, wherein the first and second select lines selecting from one of the four inputs in the 4: 1 multiplexer for generating an output signal to the output.

7. The programmable logic structure of Claim 1, wherein the logic and routing block having a dedicated logic cell comprises: a first function generator having inputs for receiving a first set of input signals and an output; a second function generator having inputs for receiving a second set of input signals and an output; a first 2:1 multiplexer having a first input for connecting to the output of the first function generator, a second input for connecting to the output of the second function generator, a first select line feeding from a first dedicated line in the one or more dedicated lines, and an output;

a third function generator having inputs for receiving the first set of input signals and an output; a fourth function generator having inputs for receiving the second set of input signals and an output; and a second 2:1 multiplexer having a first input for connecting to the output of the third function generator, a second input for connecting to the output of the fourth function generator, the first select line feeding from a first dedicated line in the one or more dedicated lines connecting to both the first multiplexer and the second multiplexer such that the first and second multiplexers share the common select line.

8. The programmable logic structure of Claim 1 , wherein the logic and routing block having a dedicated logic cell comprises: a 8:1 multiplexer having first inputs for receiving a first plurality of input signals, second inputs for receiving a second plurality of input signals, at least one dedicated lines in the one more dedicated lines functioning as select lines for the 8:1 multiplexer, and an output; a multiplexer decode logic having inputs for receiving at least one dedicated lines in the one or more dedicated lines and an output; and a multiplexer chaining logic having a first input for connecting to the output of the 8:1 multiplexer, a second input, and a third input for connecting to the output of the multiplexer decode logic.

9. The programmable logic structure of Claim 1, wherein the logic and routing block having a configurable sequential circuit comprises a first sequential circuit having an input for receiving a load data signal, a second input for receiving data, a first select input for connecting to a first dedicated line that functions as a reset line, a second select input for connecting to a second dedicated line that functions as a clear line, a third select input for connecting to a third dedicated line that functions as a clock enable line, a fourth select input for connecting to a fourth dedicated line that functions as an enable line, and an output.

10. The programmable logic structure of Claim I₅ wherein the logic and routing block comprises: a first dedicated logic cell having inputs for receiving the one or more dedicated lines, first outputs and second outputs; and a macro block having inputs connected to the outputs of the first dedicated logic cell; wherein the one or more dedicated lines connecting to first outputs in the first dedicated logic cell to a next dedicated logic cell, the one or more dedicated lines connecting to second outputs in the first dedicated logic cell to the inputs of the macro block.

11. The programmable logic structure of Claim 1, further comprising second one more dedicated lines that is stitched to the first one or more dedicated lines.

12. The programmable logic structure of Claim 1, further comprising a third logic and routing block such that first one or more dedicated lines connecting through the first logic and routing block, bypassing the second logic and routing block, and connecting through the third logic and routing block.

13. The programmable logic structure of Claim 1, wherein the one or more dedicated lines are used for data communication.

14. The programmable logic structure of Claim 1, wherein the one or more dedicated lines are used for the transferring one or more control signals.

15. A programmable logic structure, comprising: a first logic and routing block, comprising: a first dedicated logic cell; and a second dedicated logic cell, coupled to the first dedicated logic cell; first one or more dedicated lines extending through the first dedicated logic cell and the second dedicated logic cell.

16. The programmable logic structure of Claim 15, wherein the first dedicated logic cell comprises: a first function generator having an input for receiving an input signal and an output; a first multiplexer having a first input connected to the output of the first function generator, a second input connected to a first dedicated line, and an output connected to a next dedicated logic cell; and a second multiplexer having an input for connecting to the output of the first function generator, a second input for connecting to the first dedicated line, and an output connected to the logic and routing block.

17. The programmable logic structure of Claim 15, wherein the first dedicated logic cell comprises: a first function generator having inputs for receiving a plurality of input signals and an output; a second function generator having inputs for receiving the plurality of input signals and an output; a third function generator having inputs for receiving the plurality of input signals and an output; a fourth function generator having inputs for receiving the plurality of input signals and an output; and a 4:1 multiplexer having a first input connected to the output of the first function generator, a second input connected to the output of the second function generator, a third input connected to the output of the third function generator, a fourth input connected to the fourth function generator, a first select line feeding from a first dedicated line in the one or more dedicated lines, a second select line feeding from a second dedicated line in the one or more dedicated lines and an output, wherein the first and second select lines selecting from one of the four inputs in the 4:1 multiplexer for generating an output signal to the output.

18. The programmable logic structure of Claim 15, wherein the first dedicated logic cell comprises: a first function generator having inputs for receiving a first set of input signals and an output; a second function generator having inputs for receiving a second set of input signals and an output; a first 2:1 multiplexer having a first input for connecting to the output of the first function generator, a second input for connecting to the output of the second function generator, a first select line feeding from a first dedicated line in the one or more dedicated lines, and an output;

19. The programmable logic structure of Claim 15, wherein the first dedicated logic cell comprises: a 8:1 multiplexer having first inputs for receiving a first plurality of input signals, second inputs for receiving a second plurality of input signals, at least one dedicated lines in the one more dedicated lines functioning as select lines for the 8:1 multiplexer, and an output; a multiplexer decode logic having inputs for receiving at least one dedicated lines in the one or more dedicated lines and an output; and a multiplexer chaining logic having a first input for connecting to the output of the 8:1 multiplexer, a second input, and a third input for connecting to the output of the multiplexer decode logic.

20. A method for programming a programming logic circuit, comprising: receiving a first set of dedicated lines in a first dedicated logic cell in a first logic and routing block; and connecting the first set of dedicated lines beyond the first dedicated logic cell to a second location.

21. The method of Claim 20, wherein the second location comprises a second dedicated logic cell in the first LRB.

22. The method of Claim 20, wherein the second location comprises a second logic and routing block.

23. The method of Claim 20, wherein the second location comprises a second logic and routing block that is non-contiguous to the first logic and routing block such that a second set of dedicated lines are stitched to the first set of dedicated lines for skipping over an adjacent logic and routing block to the second logic and routing block.

24. A programmable logic structure for point-to-point local connections, comprising an output logic and routing cell multiplexer in a first means at a first level; and a first input logic and routing cell multiplexer in a second means at a second level, the output logic and routing cell multiplexer in the first means at the first level coupled to the first input logic and routing multiplexer cell in the second means at the second level for point-to-point connection.

25. The programmable logic structure of Claim 24, wherein the first level to the second level point-to-point connection comprises L to L + 1 point-to-point connection.

26. The programmable logic structure of Claim 24, wherein the first level to the second level point-to-point connection comprises L to L — n, where n is a positive integer number.

27. The programmable logic structure of Claim 24, wherein the first level to the second level point-to-point connection comprises L to L + n that denotes a horizontal offset, where n is a positive integer number.

28. The programmable logic structure of Claim 24, wherein the first level to the second level point-to-point connection comprises M to M + n that denotes a vertical offset, where n is a positive integer number.

29. The programmable logic structure of Claim 24, wherein the programmable logic structure produces fan out point-to-point connections by coupling the output logic and routing cell multiplexer commonly to the first input logic and routing cell multiplexer and a second input logic and routing cell multiplexer.

30. The programmable logic structure of Claim 24, further comprises a buffer that couples between the output logic and routing cell multiplexer in the first means at the first level and the first input logic and routing cell multiplexer in the second means in the second level, the buffer comprising an inverter buffer or a non-inverting buffer.

31. The programmable logic structure of Claim 24, wherein the first means comprises a logic and routing block.

32. The programmable logic structure of Claim 24, wherein the firs means comprises a dedicated logic cell.

33. A programmable logic structure for stitching connection, comprising: a first output logic and routing cell (OLRC) in a first dedicated logic cell having a reference point, the first OLRC having a first input; and a second OLRC in a second dedicated logic cell having a first offset relative to the reference point, the second OLRC having an output connected to the first input in the first OLRC to form a local interconnect.

34. The programmable logic structure of Claim 33, wherein the second dedicated logic cell is the same dedicated logic cell as the first dedicated logic cell, the second OLRC located at a position that is above the first OLRC.

35. The programmable logic structure of Claim 33, wherein the second dedicated logic cell is the same dedicated logic cell as the first dedicated logic cell, the second OLRC located at a position that is below the first OLRC.

36. The programmable logic structure of Claim 33, wherein the second dedicated logic cell is as a different logic cell than from the first dedicated logic cell, the second OLRC located a position that is to the left of the first OLRC.

37. The programmable logic structure of Claim 33, wherein the second dedicated logic cell is as a different logic cell than from the first dedicated logic cell, the second OLRC located a position that is to the right of the first OLRC.

38. The programmable logic structure of Claim 33, wherein the first OLRC comprises a second input, a third input, and a fourth input.

39. The programmable logic structure of Claim 33, further comprising a third OLRC connected to the second input of the first OLRC, the third OLRC having a second offset relative to the reference point of the first OLRC.

40. A method for programming a programmable logic circuit, comprising: providing a first dedicated logic cell having an output logic and routing cell

(OLRC); providing a second dedicate logic cell having an input logic and routing cell (ILRC); and locally connecting the OLRC in the first dedicated logic cell to the ILRC in the second dedicated logic cell.

41. A method for programming a programmable logic circuit, comprising: providing a first dedicated logic cell having an output logic and routing cell

(OLRC) multiplexer, the OLRC multiplexer having a first input; and stitching a second OLRC multiplexer to the first input of the first OLRC multiplexer through a local connection.

42. The method of Claim 41, further comprising stitching a third OLRC multiplexer to a second input of the first OLRC multiplexer through a local connection.

43. The method of Claim 42, wherein the first OLRC multiplexer and the second OLRC multiplexer reside in the same level of dedicated logic cells.

44. The method of Claim 43, wherein the first OLRC multiplexer resides in a different level of dedicated logic cells than the second OLRC multiplexer.

45. A dedicated logic cell, comprising: in a first logic and routing cell, comprising a first configurable logic function (LL) having at least one input and at least one output; a dedicated logic function (LD) having at least one input and at least one output, the at least one input of the dedicated logic function coupled to the at least one output of the first configurable logic function; and a first sequential logic function (LS) having at least one input and at least one output, the least one input of the first sequential logic function coupled to the at least one output of the dedicated logic function.

46. The dedicated logic cell of Claim 45, further comprising: in a second logic and routing cell, coupled to the first logic and routing cell, comprising: a second configurable logic function (LL) having at least one input and at least one output; a control logic function (LC) having at least one input and at least one output, the at least one input of the control logic function coupled to the at least one output of the second configurable logic function; and a second sequential logic function (LS) having at least one input and at least one output, the least one input of the second sequential logic function coupled to the at least one output of the control logic function.

47. A dedicated logic cell in a configurable logic function (LL) structure, comprising: a first look-up table having a plurality of inputs for receiving a set of inputs and at least one output; a second look-up table having a plurality of inputs for receiving the set of inputs and at least one output; a third look-up table having at least one input and at least one output; a fourth-look-up table having at least one input and at least one output; and a 4-to-l multiplexer having a first input coupled to the at least one output of the first look-up table, a second input coupled to the least one output of the second look-up table, a third input coupled to the least one output of the third look-up table, a fourth input coupled to the at lest one output of the fourth look-up table, a first select pin or a fifth input pin, a second select pin or a sixth input pin, and an output.

48. The dedicated logic cell of Claim 47, wherein the 4-to-l multiplexer comprises a first select pin and a second select pin, thereby configuring the configurable logic function structure to a 6-input look-up table.

49. The dedicated logic cell of Claim 47, wherein the 4-to-l multiplexer comprises a fifth input pin and a sixth input, thereby configuring the configurable logic function structure to a 4-to-l multiplexer.

50. The dedicated logic cell of Claim 47, wherein each of the first, second, third, and fourth look-up table is a four-input function.

51. A dedicated logic cell in a dedicated logic function (LD) structure, comprising: a first multiplexer having a first input for receiving a first operation, a second input for receiving a second operation, a select input line, and an output; and a second multiplexer having one or more inputs for receiving one or more operations, a first select input line, a second select input line, and an output coupled to the first input of the first multiplexer; and a third multiplexer having one or more inputs for receiving one or more operations, a first select input line, a second select input line, and an output coupled to the second input of the first multiplexer.

52. The dedicated logic cell of Claim 51, further comprising a first select signal generated to the select input line in the first multiplexer, a second select signal generated to the first select input line in the second multiplexer and the first select input line in the third multiplexer, and a third select signal generated to the second input line in the second multiplexer and the second select input line in the third multiplexer.

53. The dedicated logic cell of Claim 52, wherein the first, second, third select signals are set during configuration.

54. The dedicated logic cell of Claim 52, wherein the first, second, third select signals are dynamically adjustable during operation.

55. The dedicated logic cell of Claim 52, wherein the one or more operations comprise an arithmetic operation, an add operation, a subtraction operation, an addsub operation with dynamic control, a multiply operation, a divide operation, an accumulator operation, a five- input look-up table, an eight-input function, and a six-input look-up table.

56. The dedicated logic cell of Claim 52, wherein the one or more operations comprise a shift operation, a two-input look-up table, and a 6-input operation.

57. The dedicated logic cell of Claim 52, wherein the dedicated logic cell operates as an arithmetic logic unit.

58. A programmable logic circuit, comprising: a configurable propagate function circuit for receiving a first input a, a second input b, and for generating an output p; and a configurable generate function circuit, coupled to the configurable propagate function circuit, for receiving a first input a, a second input b, and generating an output g.

59. The circuit of Claim 58, further comprising a look-ahead sum generator having a first input coupled to the configurable propagate function circuit, a second input coupled to the configurable generate function circuit, and an output.

60. The circuit of Claim 58, wherein the configurable propagate function circuit and the configurable generate function circuit are configured to perform a sum function.

61. The circuit of Claim 58, wherein the configurable propagate function circuit and the configurable generate function circuit are configured to perform a priority encoding function.

62. The circuit of Claim 60, wherein the sum function is implemented with the following mathematical representation: p = a θ b g = a • b.

63. The circuit of Claim 61, wherein the priority encoding function is implemented with the following mathematical representation: p = a g = a • b.

64. The circuit of Claim 58, wherein the configurable propagate function circuit comprises: an AND gate having inputs for receiving b and an output; an inverter having inputs for receiving a and an output; and a multiplexer having a first input coupled to the output of the AND gate, a second input coupled to the output of the inverter, and an output for generate p.

65. The circuit of Claim 64, wherein the multiplexer output is selected by a design software dependent on user application.

66. The circuit of Claim 58, wherein the configurable propagate function circuit and the configurable generate function circuit performs a specified logic function to execute a carry look-ahead operation.

67. The circuit of Claim 62, wherein the parameter p =1 and the parameter g = a • b.

68. The circuit of Claim 58, wherein the configurable propagate function circuit and the configurable generate function circuit are coupled to a control logic function in creating longer chains for priority multiplexers.

69. The circuit of Claim 58, wherein the configurable generate function circuit comprises an AND gate having a first input for receiving a, a second input for receiving b, and an output for generating g.

70. A dedicated logic cell, comprising: in a first logic and routing cell, comprising a first configurable logic function (LL) having at least one input and at least one output; a control logic function (LC) having at least one input and at least one output, the at least one input of the control logic function coupled to the at least one output of the first configurable logic function; and a first sequential logic function (LS) having at least one input and at least one output, the least one input of the first sequential logic function coupled to the at least one output of the dedicated logic function.

71. The dedicated logic cell of Claim 70, further comprising: in a second logic and routing cell, coupled to the first logic and routing cell, comprising: a second configurable logic function (LL) having at least one input and at least one output; a dedicated logic function (LD) having at least one input and at least one output, the at least one input of the dedicated logic function coupled to the at least one output of the second configurable logic function; and a second sequential logic function (LS) having at least one input and at least one output, the least one input of the second sequential logic function coupled to the at least one output of the control logic function.

72. A dedicated logic cell in a sequential logic function (LS) structure, comprising: a circuit having an output for providing a control signal; and a configurable register having an input for receiving the control signal and an output.

73. The dedicated logic cell of Claim 72, wherein the control signal is driving from a dedicated line.

74. The dedicated logic cell of Claim 73, wherein the control signal comprises one of the following signals: a loadable register signal, a synchronous clear signal, a synchronous SET signal, and a load enable signal.

75. The dedicated logic cell of Claim 72, wherein the configurable register can be configured to function as a positive latch, a negative latch, a rising edge triggered flow, or a fallen edge triggered flop.

76. A dedicated logic cell in a configurable logic function (LC), comprising: a first control logic function having a first input and a first output; a second (lower) control logic function having an input and an output, the output of the second control logic function coupled to the first input of the first control logic function through at least one dedicated line; and a third (upper) control logic function having an input and an output, the first output of the first control logic function coupled to the input of the third control logic function.

77. The dedicated logic cell of Claim 76, wherein the first control logic function further comprises a second output for generating one or more control signals to a sequential logic function.

78. The dedicated logic cell of Claim 76, wherein the first control logic function comprises a third output that couples to an input in a dedicated logic function through one or more dedicated control lines.

79. The dedicated logic cell of Claim 76, wherein the first control logic function further comprises a second input for coupling to an that couples to an output in the dedicated logic function.

80. The dedicated logic cell of Claim 76, wherein the one or more dedicated control lines are unique within a logic and routing block.

81. The dedicated logic cell of Claim 76, wherein the one or more dedicated control lines are shared among a plurality of logic and routing blocks.

82. The dedicated logic cell of Claim 76, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function performs an N-input accumulator with loadable data, addsub control, synchronous clear, synchronous set, asynchronous clear, and data enable.

83. The dedicated logic cell of Claim 76, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function performs an N-input addsub comprising an addsub control, a synchronous clear, a synchronous set, an asynchronous clear, or a data enable.

84. The dedicated logic cell of Claim 76, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function performs an N-stage priority multiplexer.

85. The dedicated logic cell of Claim 76, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function performs an N-input gates including ATSED, OR, XOR, or XNOR operation.

86. The dedicated logic cell of Claim 76, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function performs an N-input addsub with a constant value with loadable data, addsub control, synchronous clear, synchronous set, asynchronous clear, and data enable.

87. The dedicated logic cell of Claim 76, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function are connected together through local lines.

88. The dedicated logic cell of Claim 76, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function can be automatically configured by software.

89. The dedicated logic cell of Claim 88, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function is automatically configured by software and is detected from a user design.

90. The dedicated logic cell of Claim 76, wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function performs an N-input accumulator with loadable data, addsub control, synchronous clear, synchronous set, asynchronous clear, and data enable.

91. The dedicated logic cell of Claim 76, wherein the first and second logic and routing cells are configured through the automatic software generation of configuration bits to produce a desirable dedicated logic cell structure.