WO2006067899A1 - Diversity receiver - Google Patents

Diversity receiver Download PDF

Info

Publication number
WO2006067899A1
WO2006067899A1 PCT/JP2005/017058 JP2005017058W WO2006067899A1 WO 2006067899 A1 WO2006067899 A1 WO 2006067899A1 JP 2005017058 W JP2005017058 W JP 2005017058W WO 2006067899 A1 WO2006067899 A1 WO 2006067899A1
Authority
WO
WIPO (PCT)
Prior art keywords
gain
level
signal
control voltage
branch
Prior art date
Application number
PCT/JP2005/017058
Other languages
French (fr)
Japanese (ja)
Inventor
Ryohei Nishizaki
Tadashi Sakaguchi
Mitsuhiro Shimozawa
Original Assignee
Mitsubishi Denki Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Denki Kabushiki Kaisha filed Critical Mitsubishi Denki Kabushiki Kaisha
Publication of WO2006067899A1 publication Critical patent/WO2006067899A1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/02Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/08Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station

Definitions

  • the present invention relates to a diversity receiver, and more particularly to a diversity receiver that can be used in a mobile body such as a vehicle and can improve a signal-to-noise ratio (SZN ratio) after reception signal synthesis.
  • SZN ratio signal-to-noise ratio
  • a diversity receiver is provided with a plurality of antennas, and the received signals received by these antennas are combined in the baseband! / Speak.
  • a combining method in the diversity receiver for example, an equal gain combining method for combining a plurality of received signals with a constant power in a baseband band and a signal-to-noise ratio (SZN ratio) in a plurality of received signals
  • SZN ratio signal-to-noise ratio
  • first and second bases receive signals received by first and second receiving antennas by first and second receivers, respectively.
  • the first and second receiver noise components are extracted by the first and second band-pass filters as the band signal, and the first and second noise components are extracted. Is synthesized.
  • the synthesized noise component is amplified by the common amplifier, and the first and second noise components are gain-controlled by the first and second auxiliary amplifiers using the automatic control gain voltage of the common amplifier, A DC voltage proportional to the logarithm of the output of the first and second auxiliary amplifiers is generated by the first and second control voltage generators and given to the first and second maximum ratio combining control circuits, respectively.
  • ratio synthesis is performed (for example, see Patent Document 1).
  • Patent Document 1 Japanese Patent Application Laid-Open No. 63-1222 (pages 3 to 4, Fig. 1)
  • the SZN ratio after combining the received signals can be improved.
  • the problem is that the signal level and noise level must be detected for each antenna, and as a result, the control for synthesizing the received signal with force will become complicated if the circuit configuration becomes complicated. there were.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a diversity receiving apparatus that has a simple circuit configuration and can maintain a good SZN ratio after synthesis. .
  • a diversity receiving apparatus includes branches corresponding to a plurality of antennas arranged spatially separated from each other, and synthesizes and outputs received signals received for each branch.
  • the diversity receiving apparatus combines the level-adjusted output signal with a level-adjusted output signal by setting the noise level in the received signal received for each branch to the same level between the branches, and the synthesized signal by combining the level-adjusted output signal.
  • a synthesizing means is included in the received signal received for each branch.
  • the noise level (noise floor level) of the received signal is set to the same level between the branches to obtain a level-adjusted output signal. Since it is configured to synthesize these level-adjusted output signals, the signal-to-noise ratio (SZN ratio) after synthesis can be improved, and an excellent reception state can be maintained.
  • SZN ratio signal-to-noise ratio
  • FIG. 1 is a block diagram showing an example of a diversity receiver according to Embodiment 1 of the present invention.
  • FIG. 2 is a flowchart for explaining the operation of the diversity receiver shown in FIG.
  • FIG. 4 is a diagram showing control voltage characteristics.
  • FIG. 4 is a diagram showing the control voltage attenuation (gain) characteristics of the RF AGC used in the diversity receiver shown in FIG.
  • FIG. 5 is a diagram showing a gain characteristic of a control voltage of IF AGC used in the diversity receiver shown in FIG. 1.
  • FIG. 6 is a diagram for explaining the IF AGC output in branch A shown in FIG. 1.
  • (a) is a diagram showing the RF input level
  • (b) is a diagram showing the RF AGC output level
  • (c) is a diagram. It is a figure which shows IF AGC output level.
  • FIG. 7 is a diagram for explaining the IFAGC output in branch B shown in FIG. 1.
  • (a) is a diagram showing the RF input level
  • (b) is a diagram showing the RF AGC output level
  • (c) is an IF It is a figure which shows an AGC output level.
  • FIG. 8 is a diagram showing a combined output level after combining the IF output levels shown in FIGS. 6 (c) and 7 (c).
  • FIG. 4C is a diagram showing a combined output level after combining.
  • FIG. 10 is a diagram for explaining an example of the SZN ratio in the diversity receiver shown in FIG. 1.
  • (a) shows the IFAGC output level in branch A
  • (b) shows the IFAGC output level in branch B.
  • FIG. 4C is a diagram showing a combined output level after combining.
  • FIG. 5C is a diagram showing a combined output level after combining.
  • FIG. 12 is a diagram for explaining another example of the SZN ratio in the diversity receiver shown in FIG. 1.
  • (a) is a diagram showing an IFAGC output level in branch A
  • (b) is a branch.
  • Fig. 7 is a diagram showing the IFAGC output level in B
  • (c) is a diagram showing the synthesized output level after synthesis.
  • FIG. 14 is a diagram showing control voltage attenuation (gain) characteristics of the RF AGC used in the diversity receiver shown in FIG. 13.
  • FIG. 15 is a diagram showing a control voltage-gain characteristic of IF AGC used in the diversity receiver shown in FIG. 13.
  • FIG. 16 is a block diagram showing an example of a diversity receiver according to Embodiment 3 of the present invention.
  • FIG. 17 is a block diagram showing a configuration of a computing unit (CPU) shown in FIG.
  • FIG. 18 is a diagram showing RF input level-control voltage characteristics of a level detector used in the diversity receiver shown in FIG. 16.
  • FIG. 19 is a diagram showing control voltage attenuation (gain) characteristics of the RF AGC used in the diversity receiver shown in FIG. 16.
  • FIG. 20 is a diagram showing a control voltage-gain characteristic of IF AGC used in the diversity receiver shown in FIG.
  • FIG. 21 is a flowchart for explaining the operation of the diversity receiver shown in FIG.
  • FIG. 22 is a block diagram showing an example of a control system used in a diversity receiver according to Embodiment 4 of the present invention.
  • FIG. 23 is a diagram showing an example of a data table stored in the information storage unit shown in FIG.
  • FIG. 24 is a flowchart for explaining the operation of the control system shown in FIG.
  • the illustrated diversity receiver 10 is described as being mounted on a moving body such as a vehicle and receiving AM radio broadcast waves and FM radio broadcast waves (hereinafter simply referred to as broadcast waves). However, the same applies to receivers that receive digital broadcast waves. Can be applied.
  • the receiving device 10 has a plurality of receiving antennas (two in the illustrated example) 11 and 12, and these receiving antennas 11 and 12 are arranged spatially separated from each other (hereinafter referred to as receiving antenna 11). This system is sometimes called branch A, and the system of receiving antenna 12 is called branch B).
  • RF automatic gain control circuit (RF AGC: first gain adjusting means) 21, RF circuit 22 (RF circuit 22 is amplifier 22a and Z up-converter 22b), distributor 23, intermediate frequency (IF) circuit 24 (IF circuit 24 has filter 24a, amplifier 24b, and down / up converter 24c), IF AGC (Second gain adjusting means) 25 and a level detector (level detector) 26 are provided.
  • RF AGC first gain adjusting means
  • RF circuit 22 is amplifier 22a and Z up-converter 22b
  • distributor 23 intermediate frequency (IF) circuit 24
  • IF circuit 24 has filter 24a, amplifier 24b, and down / up converter 24c
  • IF AGC Second gain adjusting means
  • level detector level detector
  • RF AGC31 RF circuit 32 (RF circuit 32 includes amplifier 32a and down / up converter 32b), distribution corresponding to antenna 12, that is, corresponding to branch B 33, IF circuit 34 (IF circuit 34 has a filter 34a, an amplifier 34b, and a down-Z up-converter 34c), an IF AGC 35, and a level detector 36.
  • IF AGCs 25 and 35 are connected to an IF synthesizer (synthesizing means) 41, and IF AGCs 25 and 35 are connected to a phase difference detector (phase difference detecting means) 42, and the phase difference detector 42 is a phase difference detector 42.
  • the phase shifter 43 Connected to the phase shifter (phase adjusting means) 43, and the phase shifter 43 adjusts the down Z up converter 34c as will be described later (the phase shifter 43 may adjust the down Z up converter 24c).
  • Distributors 23 and 33 are connected to level detectors 26 and 36, respectively.
  • RF AG C21 adjusts the signal level of the received signal in accordance with the first control voltage given from the level detector 26 (the first gain adjusted signal (step ST2)).
  • the output of RF AG C21 is amplified and down (up) converted in RF circuit 22 (step ST3) and then distributed by distributor 23 (step ST4) to level detector 26 and IF circuit 24, respectively. Given.
  • the level detector 26 detects the signal level as the first RF input level according to the output of the RF circuit 22 (hereinafter referred to as the first RF output), and according to the first RF input level.
  • a first control voltage (signal level control voltage) is generated (step ST5), and the first control voltage is applied to RF AGC21 and IF AGC25.
  • the first RF output is filtered and then amplified, further down (up) converted (step ST6), and used as the first IF signal, and this first IF signal is sent to the IF AGC25. give.
  • IF AGC 25 adjusts the signal level of the first IF signal in accordance with the first control voltage (the first gain-adjusted signal (that is, the level-adjusted signal) (step ST7)).
  • RF AGC 31 is supplied from level detector 36. Adjust the signal level of the received signal according to the control voltage of 2 (the first gain adjusted signal (step ST9)). The output of the RF AGC 31 is amplified and down (up) converted in the RF circuit 32 (step ST10), then distributed by the distributor 33 (step ST11), and supplied to the level detector 36 and the IF circuit 34, respectively. .
  • the level detector 36 detects the signal level as the second RF input level according to the output of the RF circuit 32 (hereinafter referred to as the second RF output), and according to the second RF input level.
  • a second control voltage (signal level control voltage) is generated (step ST12), and the second control voltage is applied to RF AGC31 and IF AGC35.
  • the second RF output is filtered and then amplified, further down (up) converted (step ST13), and used as the second IF signal, which is supplied to the IF AGC 35. .
  • IF AGC 35 adjusts the signal level of the second IF signal in accordance with the second control voltage (the second gain-adjusted signal (that is, the level-adjusted signal) (step ST14)).
  • the first and second IF signals are supplied to an IF synthesizer 41 and also to a phase difference detector 42.
  • the phase difference detector 42 detects the phase difference between the first and second IF signals, generates a phase control voltage corresponding to the phase difference (step ST15), and applies this phase control voltage to the phase shifter 43.
  • Phase shifter 43 controls the phase of the input signal from the local oscillator input to down-Z upconverter 34c (step ST16), and aligns the phase of the second IF signal to the order of the first IF signal.
  • IF synthesizer 41 synthesizes the first and second IF signals (signal level synthesis: step ST17) and outputs an IF synthesized signal (step ST18).
  • the output from the IF synthesizer 41 is given to a demodulation circuit (not shown) at the subsequent stage, and after being demodulated here, an acoustic signal is outputted as a loudspeaker (not shown).
  • the level detectors 26 and 36 each have an RF input level-control voltage characteristic indicating the relationship between the RF input level and the control voltage. Is set, and level detectors 26 and 36 output the first and second control voltages according to the first and second RF input levels, respectively.
  • RF AGC21 and 31 have the control voltage (RF AGC control voltage) attenuation (gain) characteristics shown in Fig. 4
  • IF AGC25 and 35 have the control voltage (IF AGC control voltage) attenuation characteristics shown in Fig. 5. It shall have
  • the input level of RF AGC2 1 is 60dBm (noise level is 80dBm: S / N) as shown in FIG. 6 (a).
  • the first control voltage 2.0V is output to RF AGC21 and IF AGC25.
  • AGC of the received signal is performed.
  • the output of RF AGC21 is attenuated by 10 dB, and its output level becomes 70 dB (noise level becomes 90 dB).
  • the gain is set to 10 dB (see Fig. 5), and AGC of the first IF signal is performed.
  • the output of IF AGC25 is calculated with a gain gain of 10 dB, and its output level becomes -60 dB (noise level becomes 80 dB).
  • the output of the RF AGC 31 is attenuated by 30 dB, and the output level becomes 170 dB (the noise level becomes 1 lOdB).
  • the gain is set to 30 dB (see Fig. 5), and the AGC of the second IF signal is performed.
  • the output of IF AGC35 is gained by 30 dB, and the output level becomes 140 dB (noise level becomes 80 dB).
  • the signal level after synthesis becomes 39.2 dBm (noise level is 1 77 dBm), and the SZN ratio Is 37.8 dBm (note that if the equal gain synthesis is performed at the RF input level shown in Fig. 6 (a) and Fig. 7 (b), the SZN ratio is 26 dB).
  • the noise level (noise floor) in the branches A and B before synthesis is shown in FIGS. 10 (a) and 10 (b).
  • the S / S after combining by IF combiner 41 The N ratio is improved to 11.2 dB as shown in Fig. 10 (c).
  • the noise floor is set to the same level for each branch and then the synthesis is performed, the SZN ratio after the synthesis can be improved. There are fruits.
  • the first control voltage applied to the RF AGC 21 is applied to the IF AGC 25, and the second control voltage applied to the RF AGC 31 is applied to the IF AGC 35, so that the noise floors between the branches are made uniform.
  • the S / N ratio after synthesis can be improved with a simple configuration.
  • the illustrated receiver 10 includes level converters (control voltage level adjusting means) 51 and 52, and level detectors 26 and 36 are connected to IF AGCs 25 and 35 via level shifts 51 and 52, respectively. ing.
  • the RF AGC control voltage attenuation characteristic and the IF AGC control voltage-gain characteristic have been described as having the same slope 1S, that is, RF AGC 21 and 31.
  • IF AGC25 and 35 have been described as having the same characteristics, RF AGC21 and 31 may be different from IF AGC25 and 35 in practice.
  • the slope of the straight line indicating the RF AGC control voltage-attenuation characteristic may be different from the slope of the straight line indicating the IF AGC control voltage-gain characteristic (example shown in the figure). Then, the slope of the straight line indicating the RF AGC control voltage-attenuation characteristic is 1Z2 of the slope of the straight line indicating the IF AGC control voltage-gain characteristic.
  • the first control voltage is applied to AGC25 and the second control voltage is applied to RF AGC31 and IF AGC35 from level detector 36, respectively, the first and second IF signals output from IF AGC25 and 35 respectively.
  • the noise level cannot be made uniform, and as a result, the SZN ratio after synthesis cannot be improved.
  • level change ⁇ 51 is inserted, and the control voltage applied to IF AGC25 is level-converted by level converter 51, so that the attenuation in RF AGC21 and the gain in IF AGC25 are To be equal.
  • the level change ⁇ 51 gives the first control voltage 1Z2 to IF AGC25.
  • the attenuation in RF AGC21 and the gain in IF AGC25 are equal.
  • control voltage applied to IF AGC 35 is level-converted by level converter 52, and RF
  • Attenuation at AGC31 and IF AGC35 gain should be equal.
  • level change ⁇ 52 gives the IF AGC 35 1/2 the second control voltage
  • the RF AGC 21 and 31 and the IF AGC 25 and 35 have different control voltage-gain (attenuation) characteristics when the first and second control functions are different. Since the voltage is level-converted according to the control voltage-gain characteristic and applied to IF AGC25 and 35, respectively, the noise floors of the first and second IF signals can be aligned before synthesis. This has the effect of improving the SZN ratio.
  • Embodiment 3 Next, a receiving apparatus according to the third embodiment of the present invention will be described with reference to FIG. In FIG. 16, the same components as those in FIG. In the examples shown in Fig. 4, Fig. 5, Fig. 14 and Fig. 15, the RF input level control voltage characteristics, RF AGC control voltage attenuation characteristics, and IF AGC control voltage gain characteristics change linearly (linearly). As described above, the RF AGC control voltage—attenuation characteristic and the IF AGC control voltage—gain characteristic may change nonlinearly (curved).
  • the receiving apparatus 10 shown in the figure is provided with a computing unit (CPU) 53, and this CPU 53 is connected to the outputs of the level detectors 26 and 36, and is connected to the RF AGCs 21 and 31 and the IF AGCs 25 and 35. Control RF AGC 21 and 31 and IF AG C25 and 35 as described below.
  • CPU computing unit
  • the CPU 53 has a voltage detection unit 53a, an information storage unit (storage unit) 53b, and an output voltage calculation unit 53c.
  • the first output from the level detectors 26 and 36 is the first.
  • the branch A side RF AGC control voltage and IF AGC control voltage are generated based on the second control voltage and the branch B side RF AGC control voltage and IF AGC control voltage are output.
  • the level detectors 26 and 36 have the RF input level control voltage characteristics shown in FIG. 18, respectively, and the RF AGC 21 and 31 have the RF AGC control voltage attenuation characteristics shown in FIG. IF AGC25 and 35 each have the IF AGC control voltage-gain characteristics shown in FIG. 17 stores the RF input level control voltage characteristics, RF AGC control voltage attenuation characteristics, and IF AGC control voltage-gain characteristics shown in FIGS. 18 to 20 as a detector data table. Has been.
  • CPU 53 obtains the first and second control voltages by voltage detector 53a (step ST19), and detects the first and second control voltage values.
  • the detection result is passed to the output voltage calculation unit 53c.
  • the CPU 53 does not include the information storage unit 53b, and an external information storage device (not shown) is stored in the CPU 53 so that the above-described detector data table is stored in the external information storage device. May be.
  • the voltage detector 53a and the output voltage calculator 53c function as control voltage level adjusting means.
  • the RF input level—control voltage characteristics change in a curve in level detectors 26 and 36, and further, RF AGC 21 and 31 and IF A GC 25 and 35 Even when the control voltage-gain (attenuation) characteristics change in a curve, the noise floor of the first and second IF signals can be aligned before synthesis, resulting in improved SZN ratio after synthesis. If you can, it has a positive effect.
  • the receiving apparatus 10 shown in FIG. 1 is used, the outputs of the level detectors 26 and 36 are given to the RF AGCs 21 and 31, respectively, and the outputs of the level detectors 26 and 36 are 22 is connected to the CPU 54 shown in FIG. 22, and the output of the CPU 54 is connected to the IF AGCs 25 and 35.
  • the CPU 54 includes a voltage difference calculation unit (voltage difference calculation unit) 54a, an information storage unit 54b, and a noise floor level difference detection determination unit (noise level difference detection determination unit) 54c.
  • the information storage unit 54b includes As shown in FIG. 23, a data table representing the relationship between the voltage difference and the noise floor level difference is stored.
  • the voltage difference calculation unit 54a acquires the first and second control voltages (step ST25), and obtains the difference between the first and second control voltages as a voltage difference (step ST26). The voltage difference is given to the noise floor level difference detection determination unit 54c.
  • the noise floor level difference detection determination unit 54c refers to the data table stored in the information storage unit 54b, and detects the noise floor level difference corresponding to the voltage difference (step S). Subsequently, it is determined whether or not the noise floor level difference is not less than a preset threshold value (for example, 10 dB) (step ST28).
  • a preset threshold value for example, 10 dB
  • the noise floor level difference detection determination unit 54c compares the branch A side RF input level with the branch B side RF input level. (Step ST29) If the branch A side RF input level is lower than the branch B side input level, the gain of the IF AGC25 corresponding to branch A is minimized, assuming that branch A becomes a degradation factor of the SZN ratio after synthesis. The gain control voltage is supplied to IF AGC25 as the branch A side IF AGC control voltage.
  • the noise floor level difference detection determination unit 54c changes the IF AGC control voltage on the branch A side to the maximum value (minimum gain control voltage) (step ST30) and minimizes the gain of IF AGC25. Then, the noise floor level difference detection / determination unit 54c gives the second control voltage as the branch B side IF AGC control voltage to the branch A side IF AGC 35.
  • the gain (that is, the signal level) of the first IF signal is minimized.
  • branch A which causes SZN ratio degradation, is ignored, and SZN ratio degradation after synthesis can be prevented.
  • the branch A side RF input level and the branch B side RF input level are compared, the first and second control voltages are used, and the first control voltage> the second control voltage.
  • the branch A side RF input level is less than the branch B side RF input level, and the first control voltage ⁇ second control voltage, the branch A side RF input level ⁇ branch B side RF input level. It will be judged as a level.
  • step ST29 if the branch A side RF input level ⁇ the branch B side RF input level, the noise floor level difference detection judgment unit 54c determines the SZN ratio of the branch B after the synthesis.
  • a control voltage that minimizes the gain of IF AGC35 corresponding to branch B is applied to IF AGC35 as the branch A side IF AGC control voltage. That is, the noise floor level difference detection determination unit 54c changes the IF AGC control voltage on the branch B side to the maximum value (step ST31), and minimizes the gain of IF AGC35.
  • the noise floor level difference detection determination unit 54c performs the first control on the IF AGC 25 on the branch A side.
  • the control voltage is given as the branch A side IF AGC control voltage.
  • step ST28 if the noise floor level difference is less than the threshold, the noise floor level difference detection determination unit 54c assigns the first and second control voltages to the branch A side IF AG C control voltage and branch B, respectively. Is applied to IF AGC 25 and 35 as the IF IFGC control voltage (step ST32) and the noise floor level before synthesis is made uniform, and then the IF synthesizer 41 synthesizes the first and second IF signals.
  • the CPU 54 has a built-in voltage difference calculation unit 54a.
  • the voltage difference calculation unit 54a is made independent as a voltage difference calculation circuit, and the first and second voltage difference calculation circuits are used.
  • the second control voltage may be received and the output of the voltage difference calculation circuit may be given to the CPU 54.
  • the difference in control voltage between branches is obtained as a voltage difference
  • the difference in noise level between branches is obtained as a noise level difference according to the voltage difference.
  • the noise level difference is greater than or equal to a predefined threshold
  • the IF AGC gain is minimized in the branch that causes degradation of the signal-to-noise ratio after synthesis. There is an effect that can be prevented.
  • the diversity receiver according to the present invention is suitable for maintaining a good reception state by simplifying the circuit configuration and maintaining a good SZN ratio after synthesis.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Radio Transmission System (AREA)

Abstract

A diversity receiver (10) is provided with branches (A, B) corresponding to a plurality of antennas (11, 12) arranged spatially separated from each other, and synthesizes and outputs a signal received by each branch. The noise levels of the signals received by each branch are permitted to be equal by controlling RF AGCs (21, 31) and IF AGCs (25, 35) by level detectors (26, 36), and then IF signals between the branches are synthesized.

Description

明 細 書  Specification
ダイバーシチ受信装置  Diversity receiver
技術分野  Technical field
[0001] この発明は、ダイバーシチ受信装置に関し、車両等の移動体で用いられ、受信信 号合成後の信号対雑音比 (SZN比)を改善することのできるダイバーシチ受信装置 に関するものである。  The present invention relates to a diversity receiver, and more particularly to a diversity receiver that can be used in a mobile body such as a vehicle and can improve a signal-to-noise ratio (SZN ratio) after reception signal synthesis.
背景技術  Background art
[0002] 一般に、ダイバーシチ受信装置では、複数のアンテナを備え、これらアンテナで受 信された受信信号をベースバンド帯で合成するようにして!/ヽる。ダイバーシチ受信装 置における合成手法として、例えば、複数の受信信号をベースバンド帯でその電力 を一定として合成する等利得合成手法及び複数の受信信号において信号対雑音比 (SZN比)のよ 、受信信号に重み付け(ウェイティング)を行って合成後の SZNを良 好に保つようにした最大比合成手法がある。  [0002] In general, a diversity receiver is provided with a plurality of antennas, and the received signals received by these antennas are combined in the baseband! / Speak. As a combining method in the diversity receiver, for example, an equal gain combining method for combining a plurality of received signals with a constant power in a baseband band and a signal-to-noise ratio (SZN ratio) in a plurality of received signals There is a maximum-ratio combining method that weights (weights) and keeps the combined SZN in good condition.
[0003] 従来、最大比合成手法を用いたダイバーシチ受信装置として、例えば、第 1及び第 2の受信アンテナで受信した受信信号をそれぞれ第 1及び第 2の受信器で第 1及び 第 2のベースバンド信号とし、第 1及び第 2の帯域濾波器によって第 1及び第 2の受信 器の雑音成分 (第 1及び第 2の雑音成分)を抽出して、これら第 1及び第 2の雑音成 分を合成する。  Conventionally, as a diversity receiver using the maximum ratio combining method, for example, first and second bases receive signals received by first and second receiving antennas by first and second receivers, respectively. The first and second receiver noise components (first and second noise components) are extracted by the first and second band-pass filters as the band signal, and the first and second noise components are extracted. Is synthesized.
[0004] その後、合成雑音成分を共通増幅器によって増幅するとともに、第 1及び第 2の雑 音成分を第 1及び第 2の補助増幅器によって共通増幅器の自動制御利得電圧によ つて利得制御して、第 1及び第 2の制御電圧発生器によって第 1及び第 2の補助増 幅器の出力の対数に比例する直流電圧を生成してそれぞれ第 1及び第 2の最大比 合成制御回路に与えて最大比合成を行うようにしたものがある(例えば、特許文献 1 参照)。  [0004] Thereafter, the synthesized noise component is amplified by the common amplifier, and the first and second noise components are gain-controlled by the first and second auxiliary amplifiers using the automatic control gain voltage of the common amplifier, A DC voltage proportional to the logarithm of the output of the first and second auxiliary amplifiers is generated by the first and second control voltage generators and given to the first and second maximum ratio combining control circuits, respectively. There is one in which ratio synthesis is performed (for example, see Patent Document 1).
[0005] 特許文献 1 :特開昭 63— 1222号公報 (第 3頁〜第 4頁、第 1図)  [0005] Patent Document 1: Japanese Patent Application Laid-Open No. 63-1222 (pages 3 to 4, Fig. 1)
[0006] 従来の最大比合成手法を用いたダイバーシチ受信装置は以上のように構成されて いるので、受信信号を合成した後における SZN比を良好にすることができるものの、 各アンテナ毎に信号レベルと雑音レベルとを検知しなければならず、結果的に回路 構成が複雑となるば力りでなぐ受信信号を合成するための制御が複雑になってしま うという課題があった。 [0006] Since the diversity receiver using the conventional maximum ratio combining method is configured as described above, the SZN ratio after combining the received signals can be improved. The problem is that the signal level and noise level must be detected for each antenna, and as a result, the control for synthesizing the received signal with force will become complicated if the circuit configuration becomes complicated. there were.
[0007] 一方、等利得合成手法を用いたダイバーシチ受信装置にお!/、ては、回路構成は 簡単になるものの、アンテナ間における SZN比の差が大きくなると、 SZN比が悪い 受信信号が支配的となってしまい、合成後における SZN比が劣化してしまい、良好 な受信状態が維持できな 、と 、う課題があった。  [0007] On the other hand, in a diversity receiver using the equal gain combining method, although the circuit configuration becomes simple, if the difference in the SZN ratio between antennas increases, the received signal with the poor SZN ratio dominates. As a result, the SZN ratio after synthesis deteriorates and a good reception state cannot be maintained.
[0008] この発明は上記のような課題を解決するためになされたもので、回路構成が簡単で し力も合成後における SZN比を良好に維持できるダイバーシチ受信装置を提供す ることを目的とする。  [0008] The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a diversity receiving apparatus that has a simple circuit configuration and can maintain a good SZN ratio after synthesis. .
発明の開示  Disclosure of the invention
[0009] この発明に係るダイバーシチ受信装置は、空間的に互いに離間して配置された複 数のアンテナ毎に対応するブランチを備え、該ブランチ毎に受信された受信信号を 合成して出力する。そして、このダイバーシチ受信装置は、ブランチ毎に受信された 受信信号におけるノイズレベルをブランチ間で同一のレベルとしてレベル調整済み 出力信号とするレベル調整手段と、レベル調整済み出力信号を合成して合成信号と する合成手段とを有することを特徴とするものである。  [0009] A diversity receiving apparatus according to the present invention includes branches corresponding to a plurality of antennas arranged spatially separated from each other, and synthesizes and outputs received signals received for each branch. The diversity receiving apparatus combines the level-adjusted output signal with a level-adjusted output signal by setting the noise level in the received signal received for each branch to the same level between the branches, and the synthesized signal by combining the level-adjusted output signal. And a synthesizing means.
[0010] この発明によれば、ブランチ毎に受信された受信信号を合成する前に、受信信号 のノイズレベル(ノイズフロアレベル)をブランチ間で同一のレベルとしてレベル調整 済み出力信号とした後、これらレベル調整済み出力信号を合成するように構成した ので、合成後における信号対雑音比 (SZN比)を改善でき、良好な受信状態を維持 できるという効果がある。  [0010] According to the present invention, before synthesizing the received signal received for each branch, the noise level (noise floor level) of the received signal is set to the same level between the branches to obtain a level-adjusted output signal. Since it is configured to synthesize these level-adjusted output signals, the signal-to-noise ratio (SZN ratio) after synthesis can be improved, and an excellent reception state can be maintained.
図面の簡単な説明  Brief Description of Drawings
[0011] [図 1]この発明の実施の形態 1によるダイバーシチ受信装置の一例を示すブロック図 である。  FIG. 1 is a block diagram showing an example of a diversity receiver according to Embodiment 1 of the present invention.
[図 2]図 1に示すダイバーシチ受信装置の動作を説明するためのフローチャートであ る。  2 is a flowchart for explaining the operation of the diversity receiver shown in FIG.
[図 3]図 1に示すダイバーシチ受信装置で用いられるレベル検出器の RF入力レベル —制御電圧特性を示す図である。 [Fig. 3] RF input level of the level detector used in the diversity receiver shown in Fig. 1 FIG. 4 is a diagram showing control voltage characteristics.
[図 4]図 1に示すダイバーシチ受信装置で用いられる RF AGCの制御電圧 減衰( 利得)特性を示す図である。  4 is a diagram showing the control voltage attenuation (gain) characteristics of the RF AGC used in the diversity receiver shown in FIG.
[図 5]図 1に示すダイバーシチ受信装置で用 、られる IF AGCの制御電圧一利得特 性を示す図である。  FIG. 5 is a diagram showing a gain characteristic of a control voltage of IF AGC used in the diversity receiver shown in FIG. 1.
[図 6]図 1に示すブランチ Aにおける IF AGC出力を説明するための図であり、 (a)は R F入力レベルを示す図、(b)は RF AGC出力レベルを示す図、(c)は IF AGC出力 レベルを示す図である。  6 is a diagram for explaining the IF AGC output in branch A shown in FIG. 1. (a) is a diagram showing the RF input level, (b) is a diagram showing the RF AGC output level, and (c) is a diagram. It is a figure which shows IF AGC output level.
[図 7]図 1に示すブランチ Bにおける IFAGC出力を説明するための図であり、 (a)は R F入力レベルを示す図、(b)は RF AGC出力レベルを示す図、(c)は IF AGC出力 レベルを示す図である。  7 is a diagram for explaining the IFAGC output in branch B shown in FIG. 1. (a) is a diagram showing the RF input level, (b) is a diagram showing the RF AGC output level, and (c) is an IF It is a figure which shows an AGC output level.
[図 8]図 6 (c)及び図 7 (c)に示す IF出力レベルを合成した後の合成出力レベルを示 す図である。  FIG. 8 is a diagram showing a combined output level after combining the IF output levels shown in FIGS. 6 (c) and 7 (c).
圆 9]等利得合成を行った際の SZN比の一例を説明するための図であり、 (a)はブ ランチ Aにおける IFAGC出力レベルを示す図、(b)はブランチ Bにおける IFAGC出 カレベルを示す図、(c)は合成後の合成出力レベルを示す図である。 圆 9] It is a diagram for explaining an example of the SZN ratio when equal gain synthesis is performed. (A) shows the IFAGC output level in branch A, and (b) shows the IFAGC output level in branch B. FIG. 4C is a diagram showing a combined output level after combining.
[図 10]図 1に示すダイバーシチ受信装置における SZN比の一例を説明するための 図であり、(a)はブランチ Aにおける IFAGC出力レベルを示す図、(b)はブランチ B における IFAGC出力レベルを示す図、(c)は合成後の合成出力レベルを示す図で ある。  10 is a diagram for explaining an example of the SZN ratio in the diversity receiver shown in FIG. 1. (a) shows the IFAGC output level in branch A, and (b) shows the IFAGC output level in branch B. FIG. 4C is a diagram showing a combined output level after combining.
圆 11]等利得合成を行った際の SZN比の他の例を説明するための図であり、 (a)は ブランチ Aにおける IFAGC出力レベルを示す図、(b)はブランチ Bにおける IF AGC 出力レベルを示す図、(c)は合成後の合成出力レベルを示す図である。 圆 11] It is a diagram for explaining another example of the SZN ratio when equal gain synthesis is performed. (A) shows the IFAGC output level in branch A, (b) shows the IF AGC output in branch B FIG. 5C is a diagram showing a combined output level after combining.
[図 12]図 1に示すダイバーシチ受信装置における SZN比の他の例を説明するため の図であり、(a)はブランチ Aにおける IFAGC出力レベルを示す図、(b)はブランチ 12 is a diagram for explaining another example of the SZN ratio in the diversity receiver shown in FIG. 1. (a) is a diagram showing an IFAGC output level in branch A, and (b) is a branch.
Bにおける IFAGC出力レベルを示す図、(c)は合成後の合成出力レベルを示す図 である。 Fig. 7 is a diagram showing the IFAGC output level in B, and (c) is a diagram showing the synthesized output level after synthesis.
圆 13]この発明の実施の形態 2によるダイバーシチ受信装置の一例を示すブロック図 である。 [13] Block diagram showing an example of a diversity receiver according to the second embodiment of the present invention. It is.
[図 14]図 13に示すダイバーシチ受信装置で用 ヽられる RF AGCの制御電圧 減 衰 (利得)特性を示す図である。  FIG. 14 is a diagram showing control voltage attenuation (gain) characteristics of the RF AGC used in the diversity receiver shown in FIG. 13.
[図 15]図 13に示すダイバーシチ受信装置で用 、られる IF AGCの制御電圧一利得 特性を示す図である。  FIG. 15 is a diagram showing a control voltage-gain characteristic of IF AGC used in the diversity receiver shown in FIG. 13.
[図 16]この発明の実施の形態 3によるダイバーシチ受信装置の一例を示すブロック図 である。  FIG. 16 is a block diagram showing an example of a diversity receiver according to Embodiment 3 of the present invention.
[図 17]図 16に示す演算器 (CPU)の構成を示すブロック図である。  FIG. 17 is a block diagram showing a configuration of a computing unit (CPU) shown in FIG.
[図 18]図 16に示すダイバーシチ受信装置で用 、られるレベル検出器の RF入力レべ ル―制御電圧特性を示す図である。  FIG. 18 is a diagram showing RF input level-control voltage characteristics of a level detector used in the diversity receiver shown in FIG. 16.
[図 19]図 16に示すダイバーシチ受信装置で用 ヽられる RF AGCの制御電圧 減 衰 (利得)特性を示す図である。  FIG. 19 is a diagram showing control voltage attenuation (gain) characteristics of the RF AGC used in the diversity receiver shown in FIG. 16.
[図 20]図 16に示すダイバーシチ受信装置で用 、られる IF AGCの制御電圧一利得 特性を示す図である。  20 is a diagram showing a control voltage-gain characteristic of IF AGC used in the diversity receiver shown in FIG.
[図 21]図 16に示すダイバーシチ受信装置の動作を説明するためのフローチャートで ある。  FIG. 21 is a flowchart for explaining the operation of the diversity receiver shown in FIG.
[図 22]この発明の実施の形態 4によるダイバーシチ受信装置で用いられる制御系の 一例を示すブロック図である。  FIG. 22 is a block diagram showing an example of a control system used in a diversity receiver according to Embodiment 4 of the present invention.
[図 23]図 22に示す情報記憶部に格納されたデータテーブルの一例を示す図である  FIG. 23 is a diagram showing an example of a data table stored in the information storage unit shown in FIG.
[図 24]図 22に示す制御系の動作を説明するためのフローチャートである。 24 is a flowchart for explaining the operation of the control system shown in FIG.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
以下、この発明をより詳細に説明するために、この発明を実施するための最良の形 態について、添付の図面に従って説明する。  Hereinafter, in order to explain the present invention in more detail, the best mode for carrying out the present invention will be described with reference to the accompanying drawings.
実施の形態 1. Embodiment 1.
まず、図 1を参照して、図示のダイバーシチ受信装置 10は、例えば、車両等の移動 体に搭載され AMラジオ放送波、 FMラジオ放送波(以下単に放送波と呼ぶ)を受信 するものとして説明するが、デジタル放送波を受信する受信装置についても同様にし て適用することができる。受信装置 10は複数の受信アンテナ(図示の例で 2つ) 11及 び 12を有しており、これら受信アンテナ 11及び 12は空間的に互いに離間して配置さ れている(以下受信アンテナ 11の系統をブランチ A、受信アンテナ 12の系統をブラ ンチ Bと呼ぶことがある)。 First, referring to FIG. 1, the illustrated diversity receiver 10 is described as being mounted on a moving body such as a vehicle and receiving AM radio broadcast waves and FM radio broadcast waves (hereinafter simply referred to as broadcast waves). However, the same applies to receivers that receive digital broadcast waves. Can be applied. The receiving device 10 has a plurality of receiving antennas (two in the illustrated example) 11 and 12, and these receiving antennas 11 and 12 are arranged spatially separated from each other (hereinafter referred to as receiving antenna 11). This system is sometimes called branch A, and the system of receiving antenna 12 is called branch B).
[0013] アンテナ 11に対応して、つまり、ブランチ Aに対応して高周波自動利得制御回路( RF AGC :第 1の利得調整手段) 21、 RF回路 22 (RF回路 22は増幅器 22a及びダ ゥン Zアップコンバータ 22bを有している)、分配器 23、中間周波 (IF)回路 24 (IF回 路 24は濾波器 24a、増幅器 24b、及びダウン/アップコンバータ 24cを有している)、 IF AGC (第 2の利得調整手段) 25、及びレベル検出器(detector:レベル検出手 段) 26が備えられている。  [0013] Corresponding to antenna 11, that is, corresponding to branch A, RF automatic gain control circuit (RF AGC: first gain adjusting means) 21, RF circuit 22 (RF circuit 22 is amplifier 22a and Z up-converter 22b), distributor 23, intermediate frequency (IF) circuit 24 (IF circuit 24 has filter 24a, amplifier 24b, and down / up converter 24c), IF AGC (Second gain adjusting means) 25 and a level detector (level detector) 26 are provided.
[0014] 同様にして、アンテナ 12に対応して、つまり、ブランチ Bに対応して、 RF AGC31 、 RF回路 32 (RF回路 32は増幅器 32a及びダウン/アップコンバータ 32bを有して いる)、分配器 33、 IF回路 34 (IF回路 34は濾波器 34a、増幅器 34b、及びダウン Z アップコンバータ 34cを有している)、 IF AGC35、及びレベル検出器 36が備えられ ている。  [0014] Similarly, RF AGC31, RF circuit 32 (RF circuit 32 includes amplifier 32a and down / up converter 32b), distribution corresponding to antenna 12, that is, corresponding to branch B 33, IF circuit 34 (IF circuit 34 has a filter 34a, an amplifier 34b, and a down-Z up-converter 34c), an IF AGC 35, and a level detector 36.
[0015] IF AGC25及び 35は IF合成器 (合成手段) 41に接続され、さらに、 IF AGC25 及び 35は位相差検出器 (位相差検出手段) 42に接続され、位相差検出器 42は位 相器 (位相調整手段) 43に接続されて、位相器 43によって後述するようにダウン Zァ ップコンバータ 34cが調整される(なお、位相器 43によってダウン Zアップコンバータ 24cを調整するようにしてもよい)。また、分配器 23及び 33はそれぞれレベル検出器 26及び 36に接続されて 、る。  [0015] IF AGCs 25 and 35 are connected to an IF synthesizer (synthesizing means) 41, and IF AGCs 25 and 35 are connected to a phase difference detector (phase difference detecting means) 42, and the phase difference detector 42 is a phase difference detector 42. Connected to the phase shifter (phase adjusting means) 43, and the phase shifter 43 adjusts the down Z up converter 34c as will be described later (the phase shifter 43 may adjust the down Z up converter 24c). . Distributors 23 and 33 are connected to level detectors 26 and 36, respectively.
[0016] 図 2も参照して、いま、アンテナ 11に注目して、放送波がアンテナ 11で受信信号と して受信されると、つまり、ブランチ Aに信号が入力されると (ステップ ST1)、 RF AG C21はレベル検出器 26から与えられる第 1の制御電圧に応じて受信信号の信号レ ベルを調整する(第 1の利得調整済み信号とする (ステップ ST2) )。そして、 RF AG C21の出力は RF回路 22において増幅及びダウン (アップ)コンバートされた後(ステ ップ ST3)、分配器 23によって分配されて (ステップ ST4)それぞれレベル検出器 26 及び IF回路 24に与えられる。 [0017] レベル検出器 26では RF回路 22の出力(以下第 1の RF出力と呼ぶ)に応じてその 信号レベルを第 1の RF入力レベルとして検出して、第 1の RF入力レベルに応じて第 1の制御電圧 (信号レベル制御電圧)を生成し (ステップ ST5)、第 1の制御電圧を RF AGC21及び IF AGC25に与える。一方、 IF回路 24では第 1の RF出力をフィルタ リングした後増幅し、さらにダウン (アップ)コンバートして (ステップ ST6)、第 1の IF信 号とし、この第 1の IF信号を IF AGC25に与える。そして、 IF AGC25では第 1の 制御電圧に応じて第 1の IF信号の信号レベルを調整する (第 1の利得調整済み信号 (つまり、レベル調整済み信号)とする (ステップ ST7) )。 [0016] Referring also to Fig. 2, now, paying attention to antenna 11, when a broadcast wave is received as a received signal by antenna 11, that is, when a signal is input to branch A (step ST1). The RF AG C21 adjusts the signal level of the received signal in accordance with the first control voltage given from the level detector 26 (the first gain adjusted signal (step ST2)). The output of RF AG C21 is amplified and down (up) converted in RF circuit 22 (step ST3) and then distributed by distributor 23 (step ST4) to level detector 26 and IF circuit 24, respectively. Given. [0017] The level detector 26 detects the signal level as the first RF input level according to the output of the RF circuit 22 (hereinafter referred to as the first RF output), and according to the first RF input level. A first control voltage (signal level control voltage) is generated (step ST5), and the first control voltage is applied to RF AGC21 and IF AGC25. On the other hand, in the IF circuit 24, the first RF output is filtered and then amplified, further down (up) converted (step ST6), and used as the first IF signal, and this first IF signal is sent to the IF AGC25. give. Then, IF AGC 25 adjusts the signal level of the first IF signal in accordance with the first control voltage (the first gain-adjusted signal (that is, the level-adjusted signal) (step ST7)).
[0018] 同様にして、アンテナ 12で放送波 (受信信号)が受信されると、つまり、ブランチ Bに 信号が入力されると (ステップ ST8)、 RF AGC31はレベル検出器 36から与えられ る第 2の制御電圧に応じて受信信号の信号レベルを調整する(第 1の利得調整済み 信号とする(ステップ ST9) )。そして、 RF AGC31の出力は RF回路 32において増 幅及びダウン (アップ)コンバートされた後 (ステップ ST10)、分配器 33によって分配 されて (ステップ ST11)それぞれレベル検出器 36及び IF回路 34に与えられる。  [0018] Similarly, when a broadcast wave (received signal) is received by antenna 12, that is, when a signal is input to branch B (step ST8), RF AGC 31 is supplied from level detector 36. Adjust the signal level of the received signal according to the control voltage of 2 (the first gain adjusted signal (step ST9)). The output of the RF AGC 31 is amplified and down (up) converted in the RF circuit 32 (step ST10), then distributed by the distributor 33 (step ST11), and supplied to the level detector 36 and the IF circuit 34, respectively. .
[0019] レベル検出器 36では RF回路 32の出力(以下第 2の RF出力と呼ぶ)に応じてその 信号レベルを第 2の RF入力レベルとして検出して、第 2の RF入力レベルに応じて第 2の制御電圧 (信号レベル制御電圧)を生成し (ステップ ST12)、第 2の制御電圧を R F AGC31及び IF AGC35に与える。一方、 IF回路 34では第 2の RF出力をフィル タリングした後増幅し、さらにダウン (アップ)コンバートして (ステップ ST13)、第 2の I F信号とし、この第 2の IF信号を IF AGC35に与える。そして、 IF AGC35では第 2 の制御電圧に応じて第 2の IF信号の信号レベルを調整する(第 2の利得調整済み信 号 (つまり、レベル調整済み信号)とする (ステップ ST14) )。  [0019] The level detector 36 detects the signal level as the second RF input level according to the output of the RF circuit 32 (hereinafter referred to as the second RF output), and according to the second RF input level. A second control voltage (signal level control voltage) is generated (step ST12), and the second control voltage is applied to RF AGC31 and IF AGC35. On the other hand, in the IF circuit 34, the second RF output is filtered and then amplified, further down (up) converted (step ST13), and used as the second IF signal, which is supplied to the IF AGC 35. . Then, IF AGC 35 adjusts the signal level of the second IF signal in accordance with the second control voltage (the second gain-adjusted signal (that is, the level-adjusted signal) (step ST14)).
[0020] 第 1及び第 2の IF信号は IF合成器 41に与えられるとともに、位相差検出器 42に与 えられる。位相差検出器 42では第 1及び第 2の IF信号の位相差を検出して、位相差 に応じた位相制御電圧を生成して (ステップ ST15)、この位相制御電圧を位相器 43 に与える。位相器 43はダウン Zアップコンバータ 34cに入力する局部発振器からの 入力信号の位相制御を行い (ステップ ST16)、第 2の IF信号の位相を第 1の IF信号 の位ネ目に揃える。 [0021] 一方、 IF合成器 41では第 1及び第 2の IF信号の合成 (信号レベル合成:ステップ S T17)を行い、 IF合成信号を出力する (ステップ ST18)。そして、 IF合成器 41からの 出力は後段の復調回路 (図示せず)に与えられて、ここで復調された後、音響信号が スピーカ(図示せず)力 音響として出力される。 [0020] The first and second IF signals are supplied to an IF synthesizer 41 and also to a phase difference detector 42. The phase difference detector 42 detects the phase difference between the first and second IF signals, generates a phase control voltage corresponding to the phase difference (step ST15), and applies this phase control voltage to the phase shifter 43. Phase shifter 43 controls the phase of the input signal from the local oscillator input to down-Z upconverter 34c (step ST16), and aligns the phase of the second IF signal to the order of the first IF signal. On the other hand, IF synthesizer 41 synthesizes the first and second IF signals (signal level synthesis: step ST17) and outputs an IF synthesized signal (step ST18). The output from the IF synthesizer 41 is given to a demodulation circuit (not shown) at the subsequent stage, and after being demodulated here, an acoustic signal is outputted as a loudspeaker (not shown).
[0022] 次に動作について説明する。  Next, the operation will be described.
図 1及び図 3を参照して、いま、図 3に示すように、レベル検出器 26及び 36には、そ れぞれ RF入力レベルと制御電圧との関係を示す RF入力レベル -制御電圧特性が 設定されており、レベル検出器 26及び 36はそれぞれ第 1及び第 2の RF入力レベル に応じて第 1及び第 2の制御電圧を出力する。ここでは、 RF AGC21及び 31は図 4 に示す制御電圧 (RF AGC制御電圧) 減衰量 (利得)特性を有し、 IF AGC25 及び 35は図 5に示す制御電圧 (IF AGC制御電圧) 減衰量特性を有しているもの とする。  Referring to FIGS. 1 and 3, now, as shown in FIG. 3, the level detectors 26 and 36 each have an RF input level-control voltage characteristic indicating the relationship between the RF input level and the control voltage. Is set, and level detectors 26 and 36 output the first and second control voltages according to the first and second RF input levels, respectively. Here, RF AGC21 and 31 have the control voltage (RF AGC control voltage) attenuation (gain) characteristics shown in Fig. 4, and IF AGC25 and 35 have the control voltage (IF AGC control voltage) attenuation characteristics shown in Fig. 5. It shall have
[0023] ここで図 6も参照して、いま、図 6 (a)に示すよう〖こ、ブランチ Aにお!/、て RF AGC2 1の入力レベルが 60dBm (ノイズレベルは 80dBm: S/N比 = 20dB)であると すると(なお、 RF回路 22及び 32と IF回路 24及び 34の利得は OdBであるとする)、図 3からレベル検出器 26は第 1の RF入力レベル = 60dBに対して第 1の制御電圧 = 2. 0Vを出力し、 RF AGC21及び IF AGC25に与える。  [0023] Here, referring also to FIG. 6, the input level of RF AGC2 1 is 60dBm (noise level is 80dBm: S / N) as shown in FIG. 6 (a). Ratio = 20 dB) (assuming that the gains of the RF circuits 22 and 32 and IF circuits 24 and 34 are OdB), the level detector 26 from Fig. 3 shows that for the first RF input level = 60 dB The first control voltage = 2.0V is output to RF AGC21 and IF AGC25.
[0024] RF AGC21では、第 1の制御電圧 = 2. 0Vが与えられると、減衰量 = 10dBとして  [0024] In RF AGC21, when the first control voltage = 2.0V is applied, the attenuation is 10dB.
(図 4参照)、受信信号の AGCを行うことになる。つまり、図 6 (b)に示すように、 RF AGC21の出力は 10dB減衰されて、その出力レベルは 70dBとなる(ノイズレベル は 90dBとなる)。 IF AGC25では、第 1の制御電圧 = 2. 0Vが与えられると、利得 = 10dBとして(図 5参照)、第 1の IF信号の AGCを行うことになる。つまり、図 6 (c)に 示すように、 IF AGC25の出力は 10dB利得カ卩算されて、その出力レベルは— 60d Bとなる(ノイズレベルは 80dBとなる)。  (See Fig. 4) AGC of the received signal is performed. In other words, as shown in Fig. 6 (b), the output of RF AGC21 is attenuated by 10 dB, and its output level becomes 70 dB (noise level becomes 90 dB). In IF AGC25, when the first control voltage = 2.0 V is applied, the gain is set to 10 dB (see Fig. 5), and AGC of the first IF signal is performed. In other words, as shown in Fig. 6 (c), the output of IF AGC25 is calculated with a gain gain of 10 dB, and its output level becomes -60 dB (noise level becomes 80 dB).
[0025] 一方、図 7 (a)〖こ示すように、ブランチ Bにおいて、 RF AGC31の入力レベルが一 40dBm (ノイズレベルは 80dBm: S/N比 = 40dB)であるとすると、図 3からレべ ル検出器 36は第 2の RF入力レベル = 40dBに対して第 2の制御電圧 = 1. 0Vを 出力し、 RF AGC31及び IF AGC35に与える。 RF AGC31では、第 2の制御電 圧 = 1. OVが与えられると、減衰量 = 30dBとして(図 4参照)、受信信号の AGCを行 うことになる。 On the other hand, as shown in FIG. 7 (a), assuming that the input level of the RF AGC 31 in branch B is one 40 dBm (noise level is 80 dBm: S / N ratio = 40 dB), The bell detector 36 outputs the second control voltage = 1.0V for the second RF input level = 40 dB, and applies it to the RF AGC31 and IF AGC35. In RF AGC31, the second control power When pressure = 1. OV is applied, AGC of the received signal is performed with attenuation = 30 dB (see Fig. 4).
[0026] つまり、図 7 (b)に示すように、 RF AGC31の出力は 30dB減衰されて、その出力 レベルは一 70dBとなる(ノイズレベルは一 l lOdBとなる)。 IF AGC35では、第 2の 制御電圧 = 1. OVが与えられると、利得 = 30dBとして(図 5参照)、第 2の IF信号の AGCを行うことになる。つまり、図 7 (c)に示すよう〖こ、 IF AGC35の出力は 30dB利 得加算されて、その出力レベルは一 40dBとなる(ノイズレベルは一 80dBとなる)。  That is, as shown in FIG. 7B, the output of the RF AGC 31 is attenuated by 30 dB, and the output level becomes 170 dB (the noise level becomes 1 lOdB). In IF AGC35, when the second control voltage = 1. OV is applied, the gain is set to 30 dB (see Fig. 5), and the AGC of the second IF signal is performed. In other words, as shown in Fig. 7 (c), the output of IF AGC35 is gained by 30 dB, and the output level becomes 140 dB (noise level becomes 80 dB).
[0027] そして、 IF AGC25の出力(第 1の IF信号)及び IF AGC35の出力(第 2の IF信 号)は IF合成器 41に与えられて合成される。この際、第 1及び第 2の IF信号において は、ノイズフロアが揃えられているから、等利得合成を行う際においても SZN比が劣 化することなく合成を行うことができる。図 6及び図 7で示す例において、 IF合成器 41 で合成を行うと、図 8に示すように、合成後の信号レベルは 39. 2dBm (ノイズレべ ルは一 77dBm)となって、 SZN比は 37. 8dBmとなる(なお、単に図 6 (a)及び図 7 ( b)に示す RF入力レベルの際、等利得合成を行うと、 SZN比は 26dBとなる)。  [0027] The output of the IF AGC 25 (first IF signal) and the output of the IF AGC 35 (second IF signal) are given to the IF combiner 41 for synthesis. At this time, since the noise floors of the first and second IF signals are the same, even when equal gain synthesis is performed, synthesis can be performed without degrading the SZN ratio. In the examples shown in Fig. 6 and Fig. 7, when the synthesis is performed by the IF synthesizer 41, as shown in Fig. 8, the signal level after synthesis becomes 39.2 dBm (noise level is 1 77 dBm), and the SZN ratio Is 37.8 dBm (note that if the equal gain synthesis is performed at the RF input level shown in Fig. 6 (a) and Fig. 7 (b), the SZN ratio is 26 dB).
[0028] 上述したように、ブランチ A及び Bにおいて、第 1及び第 2の制御電圧(つまり、 RF AGC制御電圧)を用いて IF AGCの制御を行うようにしたから(RF AGCの減衰量 =IF AGCの利得)、第 1及び第 2の IF信号を合成する際、ノイズレベルが揃えられ ることになつて合成後の SZN比を良好にすることができることになる(なお、 RF AG Cの減衰量 + a (一定値) =IF AGCの利得とするようにしても、第 1及び第 2の IF信 号を合成する際のノイズレベルを揃えることができる)。  [0028] As described above, in branches A and B, the IF AGC is controlled using the first and second control voltages (that is, the RF AGC control voltage) (RF AGC attenuation = IF AGC gain), when the first and second IF signals are synthesized, the SZN ratio after synthesis can be improved as the noise levels are equalized (RF AG C's gain). Attenuation + a (Constant value) = IF Even if the gain of AGC is set, the noise level when combining the first and second IF signals can be made uniform).
[0029] 等利得合成を行う場合には、図 9 (a)及び (b)に示すように、合成前においてブラン チ A及び Bにおける信号レベルが揃えられる結果 (ブランチ Aにおいては、信号レべ ル = 70dBm、ノイズレベル =— 76dBm、 SZN比 = 6dB、ブランチ Bにおいては 、信号レベル = 70dBm、ノイズレベル =—80dBm、 SZN比 = 10dB)、合成の S ZN比は図 9 (c)に示すように、 10. 5dBとなる。  [0029] When equal gain combining is performed, as shown in Figs. 9 (a) and 9 (b), the signal levels in branches A and B are aligned before combining (in branch A, the signal level is = 70 dBm, noise level = — 76 dBm, SZN ratio = 6 dB, in branch B, signal level = 70 dBm, noise level = — 80 dBm, SZN ratio = 10 dB), and the combined S ZN ratio is shown in Figure 9 (c) Thus, it becomes 10.5dB.
[0030] 一方、前述のようにして、 RF AGC21及び 31と IF AGC25及び 35を制御すると 、図 10 (a)及び (b)に示すように合成前においてブランチ A及び Bにおけるノイズレ ベル (ノイズフロア)が一 80dBmと揃えられる結果、 IF合成器 41で合成した後の S/ N比は図 10 (c)に示すように 11. 2dBと向上することになる。 On the other hand, when the RF AGC 21 and 31 and the IF AGC 25 and 35 are controlled as described above, the noise level (noise floor) in the branches A and B before synthesis is shown in FIGS. 10 (a) and 10 (b). ) Is set to 80 dBm, the S / S after combining by IF combiner 41 The N ratio is improved to 11.2 dB as shown in Fig. 10 (c).
[0031] 同様にして、図 11 (a)及び (b)に示す例では、等利得合成を行う場合には、合成前 にお 、てブランチ A及び Bにおける信号レベルが揃えられる結果 (ブランチ Aにお ヽ ては、信号レベル =— 70dBm、ノイズレベル =— 80dBm、 SZN比 = 10dB、ブラ ンチ Bにおいては、信号レベル =— 70dBm、ノイズレベル = 100dBm、 SZN比 = 30dB)、合成後の SZN比は図 11 (c)に示すように、 16. OdBとなる。  Similarly, in the example shown in FIGS. 11 (a) and 11 (b), when equal gain synthesis is performed, the result of the signal levels in branches A and B being aligned before synthesis (branch A Signal level = —70 dBm, noise level = —80 dBm, SZN ratio = 10 dB, and in branch B, signal level = —70 dBm, noise level = 100 dBm, SZN ratio = 30 dB), SZN after synthesis The ratio is 16. OdB as shown in Fig. 11 (c).
[0032] 一方、前述のようにして、 RF AGC21及び 31と IF AGC25及び 35を制御すると 、図 12 (a)及び (b)に示すように、合成前においてブランチ A及び Bにおけるノイズレ ベルが— lOOdBmと揃えられる結果、 IF合成器 41で合成した後の SZN比は図 12 ( c)に示すように 27. 8dBと向上することになる。  On the other hand, when RF AGC 21 and 31 and IF AGC 25 and 35 are controlled as described above, as shown in FIGS. 12 (a) and 12 (b), the noise levels in branches A and B are reduced before synthesis. As a result of aligning with lOOdBm, the SZN ratio after synthesis by the IF synthesizer 41 is improved to 27.8dB as shown in Fig. 12 (c).
[0033] 以上のように、この実施の形態 1によれば、ブランチ毎にノイズフロアを同一のレべ ルとした後、合成を行うようにしたので、合成後における SZN比を改善できるという効 果がある。  [0033] As described above, according to the first embodiment, since the noise floor is set to the same level for each branch and then the synthesis is performed, the SZN ratio after the synthesis can be improved. There are fruits.
[0034] この実施の形態 1によれば、 RF AGC21に与える第 1の制御電圧を IF AGC25 に与え、 RF AGC31に与える第 2の制御電圧を IF AGC35に与えて、ブランチ間 のノイズフロアを揃えるようにしたので、簡単な構成で合成後における S/N比を改善 できるという効果がある。  [0034] According to the first embodiment, the first control voltage applied to the RF AGC 21 is applied to the IF AGC 25, and the second control voltage applied to the RF AGC 31 is applied to the IF AGC 35, so that the noise floors between the branches are made uniform. As a result, the S / N ratio after synthesis can be improved with a simple configuration.
[0035] 実施の形態 2.  Embodiment 2.
次に、図 13を参照してこの発明の実施の形態 2による受信装置について説明する 。図 13において、図 1と同一の構成要素については同一の参照番号を付し説明を省 略する。図示の受信装置 10では、レベル変換器 (制御電圧レベル調整手段) 51及 び 52が備えられ、レベル検出器 26及び 36がそれぞれレベル変翻 51及び 52を介 して IF AGC25及び 35に接続されている。  Next, a receiving apparatus according to the second embodiment of the present invention will be described with reference to FIG. In FIG. 13, the same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. The illustrated receiver 10 includes level converters (control voltage level adjusting means) 51 and 52, and level detectors 26 and 36 are connected to IF AGCs 25 and 35 via level shifts 51 and 52, respectively. ing.
[0036] ところで、実施の形態 1で説明した図 4及び図 5においては RF AGC制御電圧 減衰量特性と IF AGC制御電圧一利得特性が同一の傾きを有するとして説明した 1S つまり、 RF AGC21及び 31と IF AGC25及び 35とは同一の特性を有するとし て説明したが、実際には RF AGC21及び 31と IF AGC25及び 35とはその特性が 異なることがある。 [0037] 例えば、図 14及び図 15に示すように、 RF AGC制御電圧—減衰量特性を示す 直線の傾きが IF AGC制御電圧一利得特性を示す直線の傾きと異なることがある( 図示の例では、 RF AGC制御電圧—減衰量特性を示す直線の傾きが IF AGC制 御電圧一利得特性を示す直線の傾きの 1Z2なって 、る)。 Incidentally, in FIGS. 4 and 5 described in the first embodiment, the RF AGC control voltage attenuation characteristic and the IF AGC control voltage-gain characteristic have been described as having the same slope 1S, that is, RF AGC 21 and 31. Although IF AGC25 and 35 have been described as having the same characteristics, RF AGC21 and 31 may be different from IF AGC25 and 35 in practice. For example, as shown in FIGS. 14 and 15, the slope of the straight line indicating the RF AGC control voltage-attenuation characteristic may be different from the slope of the straight line indicating the IF AGC control voltage-gain characteristic (example shown in the figure). Then, the slope of the straight line indicating the RF AGC control voltage-attenuation characteristic is 1Z2 of the slope of the straight line indicating the IF AGC control voltage-gain characteristic.
[0038] このように特性が異なる際に、レベル検出器 26からそれぞれ RF AGC21及び IF  [0038] When the characteristics are different in this way, the RF detector AGC21 and IF
AGC25に第 1の制御電圧を与え、レベル検出器 36からそれぞれ RF AGC31及 び IF AGC35に第 2の制御電圧を与えると、 IF AGC25及び 35からそれぞれ出力 される第 1及び第 2の IF信号のノイズレベルを揃えることができず、その結果、合成後 の SZN比を改善することができなくなってしまう。  When the first control voltage is applied to AGC25 and the second control voltage is applied to RF AGC31 and IF AGC35 from level detector 36, respectively, the first and second IF signals output from IF AGC25 and 35 respectively. The noise level cannot be made uniform, and as a result, the SZN ratio after synthesis cannot be improved.
[0039] このため、前述のようにレベル変^ ^51を挿入して、 IF AGC25に与える制御電 圧をレベル変換器 51でレベル変換して、 RF AGC21における減衰量と IF AGC2 5における利得が等しくなるようにする。つまり、図 14及び図 15に示す特性を RF A GC21及び IF AGC25が有している際には、レベル変^ ^51は第 1の制御電圧を 1Z2して IF AGC25に与えることになり、この結果、 RF AGC21における減衰量と IF AGC25における利得が等しくなる。  [0039] For this reason, as described above, level change ^^ 51 is inserted, and the control voltage applied to IF AGC25 is level-converted by level converter 51, so that the attenuation in RF AGC21 and the gain in IF AGC25 are To be equal. In other words, when RF A GC21 and IF AGC25 have the characteristics shown in FIGS. 14 and 15, the level change ^ 51 gives the first control voltage 1Z2 to IF AGC25. As a result, the attenuation in RF AGC21 and the gain in IF AGC25 are equal.
[0040] 同様に、 IF AGC35に与える制御電圧をレベル変換器 52でレベル変換して、 RF  [0040] Similarly, the control voltage applied to IF AGC 35 is level-converted by level converter 52, and RF
AGC31における減衰量と IF AGC35における利得が等しくなるようにする。つまり 、図 14及び図 15に示す特性を RF AGC31及び IF AGC35が有している際には、 レベル変^ ^52は第 2の制御電圧を 1/2して IF AGC35に与えることになり、この 結果、 RF AGC31における減衰量と IF AGC35における利得が等しくなる。従つ て、 IF AGC25及び 35からそれぞれ出力される第 1及び第 2の IF信号のノイズレべ ルが揃えられることになつて、合成後の S/N比を改善することができることになる。  Attenuation at AGC31 and IF AGC35 gain should be equal. In other words, when RF AGC31 and IF AGC35 have the characteristics shown in FIG. 14 and FIG. 15, level change ^ 52 gives the IF AGC 35 1/2 the second control voltage, As a result, the attenuation at RF AGC31 and the gain at IF AGC35 are equal. Therefore, the noise levels of the first and second IF signals output from IF AGC 25 and 35, respectively, are aligned, and the S / N ratio after synthesis can be improved.
[0041] 以上のように、この実施の形態 2によれば、 RF AGC 21及び 31と IF AGC25及 び 35とにおいてその制御電圧一利得 (減衰)特性が異なる際、第 1及び第 2の制御 電圧を制御電圧一利得特性に応じてレベル変換してそれぞれ IF AGC25及び 35 に与えるようにしたので、合成前において第 1及び第 2の IF信号のノイズフロアを揃え ることができる結果、合成後における SZN比を改善できるという効果がある。  [0041] As described above, according to the second embodiment, the RF AGC 21 and 31 and the IF AGC 25 and 35 have different control voltage-gain (attenuation) characteristics when the first and second control functions are different. Since the voltage is level-converted according to the control voltage-gain characteristic and applied to IF AGC25 and 35, respectively, the noise floors of the first and second IF signals can be aligned before synthesis. This has the effect of improving the SZN ratio.
[0042] 実施の形態 3. 次に、図 16を参照してこの発明の実施の形態 3による受信装置について説明する 。図 16において、図 1と同一の構成要素については同一の参照番号を付し説明を省 略する。図 4及び図 5と図 14及び図 15に示す例では、 RF入力レベル 制御電圧特 性、 RF AGC制御電圧 減衰量特性、及び IF AGC制御電圧一利得特性が線形 的(直線的)に変化する場合にっ ヽて説明したが、 RF AGC制御電圧—減衰量特 性及び IF AGC制御電圧—利得特性は非線形的(曲線的)に変化することもある。 [0042] Embodiment 3. Next, a receiving apparatus according to the third embodiment of the present invention will be described with reference to FIG. In FIG. 16, the same components as those in FIG. In the examples shown in Fig. 4, Fig. 5, Fig. 14 and Fig. 15, the RF input level control voltage characteristics, RF AGC control voltage attenuation characteristics, and IF AGC control voltage gain characteristics change linearly (linearly). As described above, the RF AGC control voltage—attenuation characteristic and the IF AGC control voltage—gain characteristic may change nonlinearly (curved).
[0043] このような場合には、実施の形態 2におけるレベル変 及び 52を用いて第 1 及び第 2の制御電圧をレベル変換した後、 IF AGC25及び 35に与えても、 RF A GC21及び 31における減衰量と IF AGC25及び 35における利得とを等しくすること が難しい。このため、図示の受信装置 10では、演算器 (CPU) 53を備えて、この CP U53をレベル検出器 26及び 36の出力に接続するとともに、 RF AGC21及び 31と I F AGC25及び 35に接続して、後述するようにして、 RF AGC21及び 31と IF AG C25及び 35を制御する。  [0043] In such a case, even if the first and second control voltages are level-converted using the level change and 52 in the second embodiment and then applied to the IF AGCs 25 and 35, the RF A GCs 21 and 31 It is difficult to equalize the attenuation at IF and the gain at IF AGC25 and 35. For this reason, the receiving apparatus 10 shown in the figure is provided with a computing unit (CPU) 53, and this CPU 53 is connected to the outputs of the level detectors 26 and 36, and is connected to the RF AGCs 21 and 31 and the IF AGCs 25 and 35. Control RF AGC 21 and 31 and IF AG C25 and 35 as described below.
[0044] 図 17を参照すると、 CPU53は電圧検出部 53a、情報記憶部(記憶手段) 53b、及 び出力電圧演算部 53cを有しており、レベル検出器 26及び 36から出力される第 1及 び第 2の制御電圧に基づいて、ブランチ A側 RF AGC制御電圧及び IF AGC制御 電圧を生成するとともに、ブランチ B側 RF AGC制御電圧及び IF AGC制御電圧 を出力する。  Referring to FIG. 17, the CPU 53 has a voltage detection unit 53a, an information storage unit (storage unit) 53b, and an output voltage calculation unit 53c. The first output from the level detectors 26 and 36 is the first. The branch A side RF AGC control voltage and IF AGC control voltage are generated based on the second control voltage and the branch B side RF AGC control voltage and IF AGC control voltage are output.
[0045] いま、レベル検出器 26及び 36がそれぞれ図 18に示す RF入力レベル 制御電圧 特性を有しているものとし、さらに RF AGC21及び 31がそれぞれ図 19に示す RF AGC制御電圧 減衰量特性を有し、 IF AGC25及び 35がそれぞれ図 20に示す I F AGC制御電圧—利得特性を有しているものとする。そして、図 17に示す情報記 憶部 53bに図 18〜図 20に示す RF入力レベル 制御電圧特性、 RF AGC制御電 圧 減衰量特性及び IF AGC制御電圧一利得特性が検出器データテーブルとし て格納されている。  [0045] Now, it is assumed that the level detectors 26 and 36 have the RF input level control voltage characteristics shown in FIG. 18, respectively, and the RF AGC 21 and 31 have the RF AGC control voltage attenuation characteristics shown in FIG. IF AGC25 and 35 each have the IF AGC control voltage-gain characteristics shown in FIG. 17 stores the RF input level control voltage characteristics, RF AGC control voltage attenuation characteristics, and IF AGC control voltage-gain characteristics shown in FIGS. 18 to 20 as a detector data table. Has been.
[0046] 図 16〜図 21を参照して、 CPU53では電圧検出部 53aによって第 1及び第 2の制 御電圧を取得し (ステップ ST19)、第 1及び第 2の制御電圧値を検知して、その検知 結果を出力電圧演算部 53cに渡す。いま、レベル検出器 26及び 36への RF入力(レ ベル検出器入力レベル)がそれぞれ—60dBm及び—40dBmであるとすると(RF入 カレベル =—60dBmの際の減衰量を 10dB、 RF入力レベル =—40dBmの際の減 衰量を 30dBとする)、図 18に示すように、レベル検出器 26及び 36はそれぞれ第 1の 制御電圧 = 1. OV及び第 2の制御電圧 =0. 4Vを出力することになる。つまり、電圧 検出部 53aはブランチ A= l. 0V及びブランチ B = 0. 4Vを示す検知結果を出力す ることになる。 Referring to FIGS. 16 to 21, CPU 53 obtains the first and second control voltages by voltage detector 53a (step ST19), and detects the first and second control voltage values. The detection result is passed to the output voltage calculation unit 53c. Now, the RF input (level) to level detectors 26 and 36 Assuming that the bell detector input level is -60 dBm and -40 dBm, respectively, the attenuation when the RF input level = --60 dBm is 10 dB, and the attenuation when the RF input level = -40 dBm is 30 dB. As shown in FIG. 18, the level detectors 26 and 36 output the first control voltage = 1.OV and the second control voltage = 0.4V, respectively. That is, the voltage detection unit 53a outputs the detection result indicating the branch A = l.0V and the branch B = 0.4V.
[0047] 出力電圧演算部 53cでは情報記憶部 53b中の検出器データテーブルを検知結果 に基づいて参照し (ステップ ST20)、まずブランチ A= l. OV及びブランチ B = 0. 4 Vに対応する RF入力レベルを図 18から知る。続いて、ブランチ A側 RF入力レベル 及びブランチ B側 RF入力レベルに対応する減衰量を求める(ここでは、ブランチ A側 RF入力レベル =—60dBm、ブランチ B側 RF入力レベル =—40dBmであるから、 出力電圧演算部 53cはブランチ A側減衰量 = 10dB、ブランチ B側減衰量 = 30dBと する。なお、検出器データテーブルには RF入力と減衰量との関係を示す情報が記 録されているものとする)。  [0047] The output voltage calculation unit 53c refers to the detector data table in the information storage unit 53b based on the detection result (step ST20), and first corresponds to branch A = l. OV and branch B = 0.4 V. Know the RF input level from Figure 18. Subsequently, the attenuation corresponding to the branch A side RF input level and the branch B side RF input level is obtained (here, the branch A side RF input level = —60 dBm, the branch B side RF input level = —40 dBm, The output voltage calculation unit 53c sets the attenuation on the branch A side = 10 dB and the attenuation on the branch B side = 30 dB, and the detector data table contains information indicating the relationship between the RF input and the attenuation. And).
[0048] 出力電圧演算部 53cでは検出器データテーブルを参照して(図 19 :RF AGC制 御電圧参照 (ステップ ST21) )、ブランチ A側減衰量 = 10dBに対応するブランチ A 側 RF AGC制御電圧 = 2. IVを得るとともに、ブランチ B側減衰量 = 30dBに対応 するブランチ B側 RF AGC制御電圧 = 1. 7Vを得て、ブランチ A側 RF AGC制御 電圧 = 2. IV及びブランチ B側 RF AGC制御電圧 = 1. 7Vをそれぞれ RF AGC2 1及び 31に与える(ステップ ST22)。  [0048] The output voltage calculator 53c refers to the detector data table (see Figure 19: RF AGC control voltage (step ST21)), and the branch A side RF AGC control voltage corresponding to the branch A side attenuation = 10 dB. = 2. Obtaining IV, branch B side RF AGC control voltage = 1.7V corresponding to branch B side attenuation = 30dB, branch A side RF AGC control voltage = 2. IV and branch B side RF AGC Apply control voltage = 1.7V to RF AGC2 1 and 31 respectively (step ST22).
[0049] 同様にして、出力電圧演算部 53cでは検出器データテーブルを参照して(図 20 :1 F AGC制御電圧参照 (ステップ ST23) )、ブランチ A側減衰量 = 10dBを利得して この利得に対応するブランチ A側 IF AGC制御電圧 =0. 2Vを得るとともに、ブラン チ B側減衰量 = 30dBを利得としてこの利得に対応するブランチ B側 RF AGC制御 電圧 =0. 80Vを得て、ブランチ A側 IF AGC制御電圧 =0. 2V及びブランチ B側 R F AGC制御電圧 =0. 80Vをそれぞれ IF AGC25及び 35に与える(ステップ ST2 4)。そして、ステップ ST24を行った後、ステップ ST19に戻る。  Similarly, the output voltage calculation unit 53c refers to the detector data table (see FIG. 20: 1 F AGC control voltage (step ST23)), gains the branch A side attenuation = 10 dB and gains this gain. Branch A side IF AGC control voltage = 0.2V corresponding to the branch B side RF AGC control voltage = 0.80V corresponding to this gain with the branch B side attenuation = 30dB as the gain. A side IF AGC control voltage = 0.2V and branch B side RF AGC control voltage = 0.80V are applied to IF AGC25 and 35, respectively (step ST2 4). Then, after performing step ST24, the process returns to step ST19.
[0050] このようにすれば、 RF入力レベル 制御電圧特性、 RF AGC制御電圧 減衰量 特性及び IF AGC制御電圧一利得特性の少なくても一つが曲線的に変化しても、 R F AGC21及び 31における減衰量と IF AGC25及び 35における利得とを等しくす ることができることになり、合成前におけるノイズフロアレベルを揃えることができる結 果、合成後の SZN比を改善することができる。 [0050] By doing this, RF input level control voltage characteristics, RF AGC control voltage attenuation Even if at least one of the characteristics and the IF AGC control voltage gain characteristic changes in a curve, the attenuation in RF AGC 21 and 31 and the gain in IF AGC 25 and 35 can be made equal, and before synthesis. As a result, the SZN ratio after synthesis can be improved.
[0051] なお、 CPU53には情報記憶部 53bを備えず、 CPU53に外部情報記憶装置(図示 せず)を記憶して、この外部情報記憶装置に前述の検出器データテーブルを格納す るようにしてもよい。また、この実施の形態 3においては、電圧検出部 53a及び出力電 圧演算部 53cが制御電圧レベル調整手段として機能することになる。  Note that the CPU 53 does not include the information storage unit 53b, and an external information storage device (not shown) is stored in the CPU 53 so that the above-described detector data table is stored in the external information storage device. May be. In the third embodiment, the voltage detector 53a and the output voltage calculator 53c function as control voltage level adjusting means.
[0052] 以上のように、この実施の形態 3によれば、レベル検出器 26及び 36において RF入 カレベル—制御電圧特性が曲線的に変化し、さらに、 RF AGC21及び 31と IF A GC25及び 35とにおいてその制御電圧—利得 (減衰)特性が曲線的に変化する際 においても、合成前において第 1及び第 2の IF信号のノイズフロアを揃えることができ る結果、合成後における SZN比を改善できると 、う効果がある。  As described above, according to the third embodiment, the RF input level—control voltage characteristics change in a curve in level detectors 26 and 36, and further, RF AGC 21 and 31 and IF A GC 25 and 35 Even when the control voltage-gain (attenuation) characteristics change in a curve, the noise floor of the first and second IF signals can be aligned before synthesis, resulting in improved SZN ratio after synthesis. If you can, it has a positive effect.
[0053] 実施の形態 4.  [0053] Embodiment 4.
次に、図 22を参照してこの発明の実施の形態 4による受信装置について説明する 。実施の形態 4においては、例えば、図 1に示す受信装置 10が用いられ、レベル検 出器 26及び 36の出力はそれぞれ RF AGC21及び 31に与えられ、さらにレベル検 出器 26及び 36の出力は、図 22に示す CPU54に接続され、 CPU54の出力が IF AGC25及び 35に接続されている。  Next, a receiving apparatus according to the fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment, for example, the receiving apparatus 10 shown in FIG. 1 is used, the outputs of the level detectors 26 and 36 are given to the RF AGCs 21 and 31, respectively, and the outputs of the level detectors 26 and 36 are 22 is connected to the CPU 54 shown in FIG. 22, and the output of the CPU 54 is connected to the IF AGCs 25 and 35.
[0054] CPU54は電圧差分演算部(電圧差演算手段) 54a,情報記憶部 54b、及びノイズ フロアレベル差検出判定部(ノイズレベル差検出判定手段) 54cを備えており、情報 記憶部 54bには、図 23に示すように電圧差とノイズフロアのレベル差との関係を表す データテーブルが格納されている。図 24も参照して、第 1及び第 2の制御電圧を電 圧差分演算部 54aが取得して (ステップ ST25)、第 1及び第 2の制御電圧の差分を 電圧差として求め (ステップ ST26)、この電圧差をノイズフロアレベル差検出判定部 5 4cに与える。  The CPU 54 includes a voltage difference calculation unit (voltage difference calculation unit) 54a, an information storage unit 54b, and a noise floor level difference detection determination unit (noise level difference detection determination unit) 54c. The information storage unit 54b includes As shown in FIG. 23, a data table representing the relationship between the voltage difference and the noise floor level difference is stored. Referring also to FIG. 24, the voltage difference calculation unit 54a acquires the first and second control voltages (step ST25), and obtains the difference between the first and second control voltages as a voltage difference (step ST26). The voltage difference is given to the noise floor level difference detection determination unit 54c.
[0055] ノイズフロアレベル差検出判定部 54cでは情報記憶部 54bに格納されたデータテ 一ブルを参照して、電圧差に対応するノイズフロアのレベル差を検出して (ステップ S T27)、続いて、このノイズフロアレベル差が予め設定された閾値 (例えば、 10dB)以 上であるか否かを判定する(ステップ ST28)。 [0055] The noise floor level difference detection determination unit 54c refers to the data table stored in the information storage unit 54b, and detects the noise floor level difference corresponding to the voltage difference (step S). Subsequently, it is determined whether or not the noise floor level difference is not less than a preset threshold value (for example, 10 dB) (step ST28).
[0056] この判定の結果、ノイズフロアレベル差が閾値以上であると、さらにノイズフロアレべ ル差検出判定部 54cでは、ブランチ A側 RF入力レベルとブランチ B側 RF入カレべ ルとを比較して(ステップ ST29)、ブランチ A側 RF入力レベルくブランチ B側入カレ ベルであると、ブランチ Aを合成後の SZN比の劣化要因となるとして、ブランチ Aに 対応する IF AGC25の利得を最小利得する制御電圧をブランチ A側 IF AGC制 御電圧として IF AGC25に与える。つまり、ノイズフロアレベル差検出判定部 54cで はブランチ A側 IF AGC制御電圧を最大値 (最小利得制御電圧)に変更して (ステツ プ ST30)、 IF AGC25の利得を最小とする。そして、ノイズフロアレベル差検出判 定部 54cはブランチ B側の IF AGC35に対しては第 2の制御電圧をブランチ B側 IF AGC制御電圧として与えることになる。  [0056] If the noise floor level difference is equal to or greater than the threshold as a result of this determination, the noise floor level difference detection determination unit 54c compares the branch A side RF input level with the branch B side RF input level. (Step ST29) If the branch A side RF input level is lower than the branch B side input level, the gain of the IF AGC25 corresponding to branch A is minimized, assuming that branch A becomes a degradation factor of the SZN ratio after synthesis. The gain control voltage is supplied to IF AGC25 as the branch A side IF AGC control voltage. In other words, the noise floor level difference detection determination unit 54c changes the IF AGC control voltage on the branch A side to the maximum value (minimum gain control voltage) (step ST30) and minimizes the gain of IF AGC25. Then, the noise floor level difference detection / determination unit 54c gives the second control voltage as the branch B side IF AGC control voltage to the branch A side IF AGC 35.
[0057] その結果、 IF合成器 41 (図 1)で第 1及び第 2の IF信号を合成した際には、第 1の I F信号の利得 (つまり、信号レベル)は最小となっているから、結果的に第 1の IF信号 が合成されないことになつて、 SZN比劣化要因となるブランチ Aが無視され、合成後 の SZN比劣化を防止することができる。  As a result, when the first and second IF signals are combined by the IF combiner 41 (FIG. 1), the gain (that is, the signal level) of the first IF signal is minimized. As a result, since the first IF signal is not synthesized, branch A, which causes SZN ratio degradation, is ignored, and SZN ratio degradation after synthesis can be prevented.
[0058] なお、ブランチ A側 RF入力レベルとブランチ B側 RF入力レベルとを比較する際に は、第 1及び第 2の制御電圧が用いられ、第 1の制御電圧 >第 2の制御電圧である際 に、ブランチ A側 RF入力レベルくブランチ B側 RF入力レベルと判定され、第 1の制 御電圧≤第 2の制御電圧である際に、ブランチ A側 RF入力レベル≥ブランチ B側 R F入力レベルと判定されることになる。  [0058] When the branch A side RF input level and the branch B side RF input level are compared, the first and second control voltages are used, and the first control voltage> the second control voltage. When the branch A side RF input level is less than the branch B side RF input level, and the first control voltage ≤ second control voltage, the branch A side RF input level ≥ branch B side RF input level. It will be judged as a level.
[0059] 一方、ステップ ST29にお!/、て、ブランチ A側 RF入力レベル≥ブランチ B側 RF入 カレベルであると、ノイズフロアレベル差検出判定部 54cでは、ブランチ Bを合成後の SZN比の劣化要因となるとして、ブランチ Bに対応する IF AGC35の利得を最小 利得する制御電圧をブランチ B側 IF AGC制御電圧として IF AGC35に与える。 つまり、ノイズフロアレベル差検出判定部 54cではブランチ B側 IF AGC制御電圧を 最大値に変更して (ステップ ST31)、 IF AGC35の利得を最小とする。そして、ノィ ズフロアレベル差検出判定部 54cはブランチ A側の IF AGC25に対しては第 1の制 御電圧をブランチ A側 IF AGC制御電圧として与えることになる。 [0059] On the other hand, in step ST29, if the branch A side RF input level ≥ the branch B side RF input level, the noise floor level difference detection judgment unit 54c determines the SZN ratio of the branch B after the synthesis. As a cause of deterioration, a control voltage that minimizes the gain of IF AGC35 corresponding to branch B is applied to IF AGC35 as the branch A side IF AGC control voltage. That is, the noise floor level difference detection determination unit 54c changes the IF AGC control voltage on the branch B side to the maximum value (step ST31), and minimizes the gain of IF AGC35. Then, the noise floor level difference detection determination unit 54c performs the first control on the IF AGC 25 on the branch A side. The control voltage is given as the branch A side IF AGC control voltage.
[0060] その結果、 IF合成器 41 (図 1)で第 1及び第 2の IF信号を合成した際には、第 2の I F信号の利得 (つまり、信号レベル)は最小となっているから、結果的に第 2の IF信号 が合成されないことになつて、 SZN比劣化要因となるブランチ Bが無視され、合成後 の SZN比劣化を防止することができる。 As a result, when the first and second IF signals are combined by the IF combiner 41 (FIG. 1), the gain (that is, the signal level) of the second IF signal is minimized. As a result, since the second IF signal is not synthesized, branch B, which is the cause of SZN ratio degradation, is ignored, and SZN ratio degradation after synthesis can be prevented.
[0061] ステップ ST28において、ノイズフロアレベル差が閾値未満であると、ノイズフロアレ ベル差検出判定部 54cは、第 1及び第 2の制御電圧をそれぞれブランチ A側 IF AG C制御電圧及びブランチ B側 IF AGC制御電圧として IF AGC25及び 35に与えて (ステップ ST32)、合成前におけるノイズフロアレベルを揃えた後、 IF合成器 41によ つて第 1及び第 2の IF信号が合成される。 [0061] In step ST28, if the noise floor level difference is less than the threshold, the noise floor level difference detection determination unit 54c assigns the first and second control voltages to the branch A side IF AG C control voltage and branch B, respectively. Is applied to IF AGC 25 and 35 as the IF IFGC control voltage (step ST32) and the noise floor level before synthesis is made uniform, and then the IF synthesizer 41 synthesizes the first and second IF signals.
[0062] なお、図 22に示す例では、 CPU54が電圧差分演算部 54aを内蔵しているが、電 圧差分演算部 54aを電圧差分演算回路として独立させて、電圧差分演算回路で第 1 及び第 2の制御電圧を受け、電圧差分演算回路の出力を CPU54に与えるようにし てもよい。 In the example shown in FIG. 22, the CPU 54 has a built-in voltage difference calculation unit 54a. However, the voltage difference calculation unit 54a is made independent as a voltage difference calculation circuit, and the first and second voltage difference calculation circuits are used. The second control voltage may be received and the output of the voltage difference calculation circuit may be given to the CPU 54.
[0063] 以上のように、この実施の形態 4によれば、ブランチ間における制御電圧の差分を 電圧差として求め、電圧差に応じてブランチ間におけるノイズレベルの差をノイズレ ベル差として求めて、ノイズレベル差が予め規定された閾値以上である際合成後に おける信号対雑音比劣化の要因となるブランチにお 、て IF AGCの利得を最小と するようにしたので、合成後における SZN比の劣化を防止できるという効果がある。 産業上の利用可能性  [0063] As described above, according to the fourth embodiment, the difference in control voltage between branches is obtained as a voltage difference, and the difference in noise level between branches is obtained as a noise level difference according to the voltage difference. When the noise level difference is greater than or equal to a predefined threshold, the IF AGC gain is minimized in the branch that causes degradation of the signal-to-noise ratio after synthesis. There is an effect that can be prevented. Industrial applicability
[0064] 以上のように、この発明に係るダイバーシチ受信装置は、回路構成を簡単にし、合 成後における SZN比を良好に維持することで良好な受信状態を維持するのに適し ている。 As described above, the diversity receiver according to the present invention is suitable for maintaining a good reception state by simplifying the circuit configuration and maintaining a good SZN ratio after synthesis.

Claims

請求の範囲 The scope of the claims
[1] 空間的に互いに離間して配置された複数のアンテナ毎に対応するブランチを備え [1] A branch corresponding to each of a plurality of antennas arranged spatially apart from each other is provided.
、該ブランチ毎に受信された受信信号を合成して出力するダイバーシチ受信装置に おいて、 In the diversity receiver that synthesizes and outputs the received signals received for each branch,
前記ブランチ毎に受信された受信信号におけるノイズレベルを前記ブランチ間で 同一のレベルとしてレベル調整済み出力信号とするレベル調整手段と、  Level adjustment means for setting the noise level in the received signal received for each branch to the same level between the branches and making the level adjusted output signal;
前記レベル調整済み出力信号を合成して合成信号とする合成手段とを有すること を特徴とするダイバーシチ受信装置。  A diversity receiving apparatus comprising: combining means for combining the level-adjusted output signals into a combined signal.
[2] レベル調整手段は、ブランチ毎に受信された受信信号の利得調整を行って第 1の 利得調整済み信号とする第 1の利得制御手段と、  [2] The level adjusting means includes first gain control means for adjusting the gain of the received signal received for each branch to obtain a first gain adjusted signal;
前記第 1の利得調整済み信号力 得られた中間周波信号の利得調整を行い第 2の 利得調整済み信号とする第 2の利得制御手段と、  A second gain control means for adjusting a gain of the obtained intermediate frequency signal to obtain a second gain adjusted signal;
前記第 1の利得調整済み信号の信号レベルを検知して該信号レベルに応じた制 御電圧を生成するレベル検出手段とを有し、  Level detecting means for detecting a signal level of the first gain-adjusted signal and generating a control voltage according to the signal level;
第 1の利得制御手段における制御電圧一利得特性と第 2の利得制御手段における 制御電圧一利得特性とは互いに等しい際、前記制御電圧を前記レベル検知手段か ら前記第 1及び前記第 2の利得制御手段に与えて前記第 2の利得調整済み信号を レベル調整済み信号とするようにしたことを特徴とする請求項 i記載のダイバーシチ 受信装置。  When the control voltage one gain characteristic in the first gain control means and the control voltage one gain characteristic in the second gain control means are equal to each other, the control voltage is supplied from the level detection means to the first and second gains. The diversity receiving apparatus according to claim i, wherein the second gain-adjusted signal is supplied to a control means to be a level-adjusted signal.
[3] レベル調整手段は、ブランチ毎に受信された受信信号の利得調整を行って第 1の 利得調整済み信号とする第 1の利得制御手段と、  [3] The level adjusting means includes first gain control means for adjusting the gain of the received signal received for each branch to obtain a first gain adjusted signal;
前記第 1の利得調整済み信号力 得られた中間周波信号の利得調整を行い第 2の 利得調整済み信号とする第 2の利得制御手段と、  A second gain control means for adjusting a gain of the obtained intermediate frequency signal to obtain a second gain adjusted signal;
前記第 1の利得調整済み信号の信号レベルを検知して該信号レベルに応じた制 御電圧を生成するレベル検出手段と、  Level detecting means for detecting a signal level of the first gain-adjusted signal and generating a control voltage according to the signal level;
第 1の利得制御手段おける制御電圧一利得特性と第 2の利得制御手段における制 御電圧一利得特性が互いに異なる際、前記レベル検出手段からの制御電圧を前記 第 1の利得制御手段おける制御電圧一利得特性と前記第 2の利得制御手段におけ る制御電圧一利得特性との関係に応じてレベル変換して前記第 2の利得制御手段 に与える制御電圧レベル調整手段とを有し、 When the control voltage-one gain characteristic in the first gain control means and the control voltage-gain characteristic in the second gain control means are different from each other, the control voltage from the level detection means is the control voltage in the first gain control means. One gain characteristic and the second gain control means. A control voltage level adjusting unit that converts the level according to a relationship with the control voltage-gain characteristic and gives the second voltage to the second gain control unit,
前記第 1の利得調整手段には前記レベル検出手段からの制御電圧を与えるよう〖こ したことを特徴とする請求項 1記載のダイバーシチ受信装置。  2. The diversity receiving apparatus according to claim 1, wherein the first gain adjusting means is supplied with a control voltage from the level detecting means.
[4] レベル調整手段は、ブランチ毎に受信された受信信号の利得調整を行って第 1の 利得調整済み信号とする第 1の利得制御手段と、 [4] The level adjustment means adjusts the gain of the received signal received for each branch and sets the first gain adjusted signal as the first gain adjusted signal;
前記第 1の利得調整済み信号力 得られた中間周波信号の利得調整を行い第 2の 利得調整済み信号とする第 2の利得制御手段と、  A second gain control means for adjusting a gain of the obtained intermediate frequency signal to obtain a second gain adjusted signal;
前記第 1の利得制御手段おける制御電圧一利得特性と前記第 2の利得制御手段 における制御電圧一利得特性をデータテーブルとして記憶する記憶手段と、 前記第 1の利得調整済み信号の信号レベルを検知して該信号レベルに基づいて 前記データテーブルを参照して制御電圧を生成して前記制御電圧を前記第 1及び 前記第 2の利得調整手段に与えて前記第 2の利得調整済み信号をレベル調整済み 信号とする制御電圧レベル調整手段とを有することを特徴とする請求項 1記載のダイ バーシチ受信装置。  Storage means for storing the control voltage-one gain characteristic in the first gain control means and the control voltage-gain characteristic in the second gain control means as a data table; and detecting the signal level of the first gain-adjusted signal Then, based on the signal level, a control voltage is generated by referring to the data table, and the control voltage is supplied to the first and second gain adjusting means to adjust the level of the second gain adjusted signal. 2. The diversity receiving apparatus according to claim 1, further comprising a control voltage level adjusting unit configured as a completed signal.
[5] レベル調整手段は、ブランチ毎に受信された受信信号の利得調整を行って第 1の 利得調整済み信号とする第 1の利得制御手段と、  [5] The level adjustment means adjusts the gain of the received signal received for each branch and sets the first gain adjusted signal as the first gain adjusted signal;
前記第 1の利得調整済み信号力 得られた中間周波信号の利得調整を行い第 2の 利得調整済み信号とする第 2の利得制御手段と、  A second gain control means for adjusting a gain of the obtained intermediate frequency signal to obtain a second gain adjusted signal;
前記第 1の利得調整済み信号の信号レベルを検知して該信号レベルに応じた制 御電圧を生成するレベル検出手段と、  Level detecting means for detecting a signal level of the first gain-adjusted signal and generating a control voltage according to the signal level;
ブランチ間における制御電圧の差分を電圧差として求める電圧差演算手段と、 該電圧差に応じて前記ブランチ間におけるノイズレベルの差をノイズレベル差とし て求め該ノイズレベル差が予め規定された閾値以上である力否かを判定して、前記 ノイズレベル差が予め規定された閾値以上である際合成後における信号対雑音比 劣化の要因となるブランチにおいて第 2の利得制御手段の利得を最小とする最小利 得制御電圧を生成して前記第 2の利得制御手段に与えるノイズレベル差検出判定手 段とを有し、 前記第 1の利得調整手段には、前記レベル検出手段からの制御電圧が与えられ、 前記合成後における信号対雑音比劣化の要因となるブランチ以外のブランチにおけ る第 2の利得制御手段には前記レベル検出手段からの制御電圧を与えるようにした こと特徴とする請求項 1記載のダイバーシチ受信装置。 Voltage difference calculation means for obtaining a difference in control voltage between the branches as a voltage difference, and obtaining a noise level difference between the branches as a noise level difference according to the voltage difference, the noise level difference being equal to or greater than a predetermined threshold value When the noise level difference is equal to or greater than a predetermined threshold, the gain of the second gain control means is minimized in the branch that causes degradation of the signal-to-noise ratio after synthesis. A noise level difference detection determination means for generating a minimum gain control voltage and supplying the minimum gain control voltage to the second gain control means, The first gain adjustment means is supplied with a control voltage from the level detection means, and the second gain control means in a branch other than the branch that causes degradation of the signal-to-noise ratio after the synthesis is supplied to the first gain adjustment means. 2. The diversity receiver according to claim 1, wherein a control voltage is supplied from the level detection means.
[6] ノイズレベル差検出判定手段は、レベル検出手段で検出されたブランチ間におけ る制御電圧に応じて合成後における信号対雑音比劣化の要因となるブランチを判定 するようにしたことを特徴とする請求項 5記載のダイバーシチ受信装置。 [6] The noise level difference detection / determination means determines a branch that causes degradation of the signal-to-noise ratio after synthesis in accordance with a control voltage between the branches detected by the level detection means. The diversity receiver according to claim 5.
[7] レベル調整済み信号間の位相差を検出する位相差検出手段と、 [7] Phase difference detection means for detecting a phase difference between level-adjusted signals;
該位相差に応じて中間周波信号の位相を調整する位相調整手段を有することを特 徴とする請求項 1記載のダイバーシチ受信装置。  2. The diversity receiver according to claim 1, further comprising phase adjusting means for adjusting the phase of the intermediate frequency signal in accordance with the phase difference.
PCT/JP2005/017058 2004-12-24 2005-09-15 Diversity receiver WO2006067899A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004-374142 2004-12-24
JP2004374142A JP2006180419A (en) 2004-12-24 2004-12-24 Diversity receiver

Publications (1)

Publication Number Publication Date
WO2006067899A1 true WO2006067899A1 (en) 2006-06-29

Family

ID=36601510

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/017058 WO2006067899A1 (en) 2004-12-24 2005-09-15 Diversity receiver

Country Status (2)

Country Link
JP (1) JP2006180419A (en)
WO (1) WO2006067899A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6559078B2 (en) * 2016-02-11 2019-08-14 アルパイン株式会社 Receiver

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01171330A (en) * 1987-12-25 1989-07-06 Nec Corp Phase synthesizer
JPH04222124A (en) * 1990-12-21 1992-08-12 Nec Corp Common-mode synthesizing circuit
JPH0522202A (en) * 1991-07-10 1993-01-29 Nec Corp Space diversity circuit
JPH08223098A (en) * 1995-02-14 1996-08-30 Ido Tsushin Syst Kaihatsu Kk Diversity combined equalizer
JPH09298502A (en) * 1996-05-08 1997-11-18 Nec Corp Diversity compositor
JPH11186946A (en) * 1997-12-24 1999-07-09 Hitachi Denshi Ltd Diversity receiver and agc circuit used for the receiver
JPH11220346A (en) * 1998-02-02 1999-08-10 Fujitsu Ltd Automatic gain control circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01171330A (en) * 1987-12-25 1989-07-06 Nec Corp Phase synthesizer
JPH04222124A (en) * 1990-12-21 1992-08-12 Nec Corp Common-mode synthesizing circuit
JPH0522202A (en) * 1991-07-10 1993-01-29 Nec Corp Space diversity circuit
JPH08223098A (en) * 1995-02-14 1996-08-30 Ido Tsushin Syst Kaihatsu Kk Diversity combined equalizer
JPH09298502A (en) * 1996-05-08 1997-11-18 Nec Corp Diversity compositor
JPH11186946A (en) * 1997-12-24 1999-07-09 Hitachi Denshi Ltd Diversity receiver and agc circuit used for the receiver
JPH11220346A (en) * 1998-02-02 1999-08-10 Fujitsu Ltd Automatic gain control circuit

Also Published As

Publication number Publication date
JP2006180419A (en) 2006-07-06

Similar Documents

Publication Publication Date Title
KR101150602B1 (en) System for dynamic control of automatic gain control take-over-point and method of operation
EP2107640A1 (en) Receiver system for receiving analog and digital signals
JP4204589B2 (en) Automatic gain controller
US5513222A (en) Combining circuit for a diversity receiving system
JPH11504183A (en) AGC configuration of tuner
US20090310723A1 (en) Automatic gain control circuit
US20120157029A1 (en) Antenna switch circuit and method of switching the same
US20070026839A1 (en) Bi-modal RF architecture for low power devices
US7110735B2 (en) Automatic gain control system
CN101133567A (en) Diversity receiver and gain adjusting method therefore
JPH07154316A (en) Frequency signal synthesizer and synthesizing method
JP2004215246A (en) In-phase composite diversity receiving apparatus and method for the same
KR19980033998A (en) Receiver and Method Using Space Diversity in Wireless Transmission System
US8027644B2 (en) Transceiver system including dual low-noise amplifiers
WO2006067899A1 (en) Diversity receiver
WO2009011143A1 (en) Automatic gain control circuit
US20060223471A1 (en) Receiver having a gain cancelling amplifier
JP2797845B2 (en) AM tuner
US20070147554A1 (en) Receiver and transmitter/receiver
KR20080047219A (en) Method and apparatus simultaneous multi-channel reception in broadcasting service system
JPH11281732A (en) Saturation prevention circuit
JP6880346B2 (en) Radio reception control device, radio reception device, and radio reception control method
JP2006524976A (en) Tuner AGC circuit layout
WO2006061930A1 (en) Receiving device
JPH11186946A (en) Diversity receiver and agc circuit used for the receiver

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05783524

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP