WO2006064604A1

WO2006064604A1 - Image processor

Info

Publication number: WO2006064604A1
Application number: PCT/JP2005/018228
Authority: WO
Inventors: Akio Kobayashi; Toru Asaeda; Hidefumi Okada; Mitsuaki Kurokawa
Original assignee: Sanyo Electric Co., Ltd.
Priority date: 2004-12-17
Filing date: 2005-09-26
Publication date: 2006-06-22
Also published as: CN101061531A; JP4118272B2; JP2006171524A

Abstract

An image processor (10) includes a bus (B1) and a bus (B2). A series of processings for creating YUV image data for HDTV are executed by using the bus (B1) and an SDRAM (32). A series of processings for creating the YUV image data for an LCD monitor (66) are executed by using a bus (B3) and an SDRAM (54). The resolution of the YUV image data for the HDTV is higher than that of the YUV image data for the LCD monitor. Namely, the bus (B1) and the SDRAM (32) are used for processing high resolution moving image data, and the bus (B3) and the SDRAM (54) are used for processing low resolution moving image data.

Description

Specification

Technical field of image processing equipment

The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that is applied to, for example, a video camera and displays a moving image of an object scene on a monitor. Conventional technology

An example of a conventional device of this type is disclosed in Patent Document 1 (Japanese Laid-Open Patent Publication No. 2 0 2 2 4 7 5 1 7). According to this prior art, a composite image signal is created based on the moving image data of the photographed subject, and the created composite image signal is output to the monitor. As a result, a real-time moving image of the object scene is displayed on the monitor screen.

However, in the prior art, only one monitor displays an image. For this reason, conventional technologies only assume the creation of composite image signals corresponding to one format. In other words, the conventional technology does not disclose any processing corresponding to a plurality of formats such as HD TV images and NTSC images. Summary of the Invention

Therefore, a main object of the present invention is to provide a novel image processing apparatus.

Another object of the present invention is to provide an image processing apparatus capable of executing processing conforming to a plurality of formats without causing failure.

The image processing apparatus according to the invention of claim 1 comprises the following: a fetching means for fetching the first moving image data to be written to the first memory through the first bus; a first read from the first memory through the first bus First processing means for performing first processing on moving image data and generating second moving image data to be written to the first memory through the first bus; second processing data read from the first memory through the first bus A first output means for applying an output process directed to the first monitor to the moving image data; from the first memory through the first bus; Reducing means for reducing the resolution of the second moving image data read out to create the third moving image data to be written to the second memory through the second bus; and from the second memory to the second bus. Second output means for performing output processing directed to the second monitor on the read third moving image data.

The first moving image data is fetched by the fetching means and written to the first memory through the first bus. The first moving image data stored in the first memory is read through the first bus and subjected to the first processing by the first processing means. The second moving image data created by the first process is written to the first memory through the first bus. The second moving image data stored in the first memory is read through the first bus and subjected to output processing directed to the first monitor by the first output means. As a result, the corresponding moving image is displayed on the first monitor screen.

The reduction means reduces the resolution of the second moving image data read from the first memory through the first bus. The third moving image data thus created is written to the second memory through the second bus. The third moving image data stored in the second memory is read through the second bus and subjected to output processing directed to the second monitor by the second output means. As a result, the corresponding moving image is displayed on the screen of the second monitor.

As described above, a series of processes for creating the second moving image data output to the first monitor is executed using the first bus and the first memory. In addition, a series of processes for generating the third moving image data output toward the second monitor is executed using the second pass and the second memory. Here, the resolution of the second moving image data is higher than the resolution of the third moving image data. In other words, the first pass and first memory are used for high-speed processing such as high-resolution moving image data processing, and the second bus and second memory are used for low-speed processing such as low-resolution moving image data processing. Is used. As a result, processing conforming to multiple formats can be executed without causing a failure. An image processing apparatus according to the invention of claim 2 is dependent on claim 1, wherein the first moving image data is data in which any one of a plurality of colors is assigned to each pixel, and the first processing is all of the plurality of colors. Color processing for assigning to each pixel. By temporarily storing the first moving image data in the first memory, the first moving image data can be captured. Flexibility.

An image processing apparatus according to the invention of claim 3 is dependent on claim 1, wherein the second moving image data has a first resolution corresponding to the first aspect ratio, and the third moving image data is the second image. Has a second resolution corresponding to the aspect ratio.

An image processing apparatus according to the invention of claim 4 is dependent on claim 3, wherein the first aspect ratio is 16: 9 and the second aspect ratio is 4: 3. In this case, a moving image based on the second moving image data can be displayed on an HD TV (High Definition TV), and a moving image based on the third moving image data can be displayed on an NTSC, P A L, or S E CA M M TV.

The image processing apparatus according to the invention of claim 5 is dependent on claim 1, and the second moving image data and the third moving image data have the same frame rate. Thus, a moving image having the same smoothness can be displayed on each of the first monitor and the second monitor.

An image processing apparatus according to the invention of claim 6 is dependent on claim 1, and the capturing means includes photographing means for periodically photographing the object scene. This realizes a video power camera that creates moving image data that conforms to multiple formats.

An image processing apparatus according to the invention of claim 7 is dependent on claim 6, and the imaging means includes an imaging surface on which a plurality of partial imaging areas are formed, and a plurality of output paths respectively assigned to the plurality of partial imaging areas. And the capturing means further includes a creating means for creating the first moving image data based on the charges output from the plurality of output paths. As a result, the first moving image data with improved resolution and frame rate can be obtained.

The image processing apparatus according to the invention of claim 8 is dependent on claim 1, compressing the data amount of the second moving image data read from the first memory through the first bus, and passing the first memory through the first path. It further includes a first compression means for creating fourth moving image data to be written. By transferring both the second video data before compression and the fourth video data after compression using the common first bus, high-speed compression processing is realized.

An image processing apparatus according to the invention of claim 9 is dependent on claim 8, and is a first compression means. Performs the compression process when the first predetermined operation is performed.

An image processing device according to the invention of claim 10 is dependent on claim 8 and further comprises: the fourth moving image data read from the first memory through the first bus to the second memory through the second bus A first writing means for writing; and a moving image recording means for recording the fourth moving image data read from the second memory through the second pass on a recording medium.

An image processing device according to the invention of claim 1 is dependent on claim 1, and performs a second process on the first still image data of one frame forming the first moving image data, and a second bus is provided to the second memory. And a second processing means for creating second still image data to be written through. The first still image data is extracted from the first moving image data transferred through the first bus, and converted to the second still image data by the second process. The converted second still image data is written to the second memory through the second bus. By using the second pass and second memory for still image data processing (low-speed processing) that does not cause frame rate problems, processing failures are avoided.

The image processing device according to the invention of claim 12 is dependent on claim 11 and the second processing means executes the second process when the second predetermined operation is performed.

The image processing device according to the invention of claim 13 is dependent on claim 11 and compresses the amount of data of the second still image read from the second memory through the second bus to the second memory. Second compression means for creating third still image data to be written through the second bus is further provided. High-speed compression processing is realized by transferring both the second still image data before compression and the third still image data after compression using the common second path.

The image processing apparatus according to the invention of claim 14 is dependent on claim 13 and further includes a still image recording means for recording the third still image data created by the second compression means on the recording medium.

The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings. Brief Description of Drawings FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention; FIG. 2 is an illustrative view showing an example of the configuration of a CCD imager applied to the embodiment of FIG.

Fig. 3 is an illustrative view showing an example of the configuration of the imaging surface of the CCD imager shown in Fig. 2;

FIG. 4 is an illustrative view showing one example of a mapping state of the S D RAM applied to the embodiment of FIG. 1;

FIG. 5 is an illustrative view showing an example of another SD RAM mapping state applied to the embodiment of FIG. 1;

FIG. 6 is a block diagram showing an example of the configuration of the S D RAM controller applied to the FIG. 1 embodiment;

FIG. 7 is a block diagram showing an example of the configuration of another SDRAM controller applied to the FIG. 1 embodiment;

Fig. 8 (A) is an illustration showing the aspect ratio of the moving image displayed on the HDTV;

Figure 8 (B) is an illustration showing the aspect ratio of the video displayed on the LCD monitor;

Fig. 8 (C) is an illustration showing the aspect ratio of recorded still images. BEST MODE FOR CARRYING OUT THE INVENTION

Referring to FIG. 1, a digital video camera 10 of this embodiment includes a CCD imager 12. The optical image of the object scene is irradiated onto the imaging surface of the CCD imager 12 through an optical lens (not shown). The imaging surface is covered with a primary color filter array color filter 1 2 f. For this reason, the charge generated in each of the plurality of light receiving elements formed on the imaging surface has color information of R (Red), G (Green), or B (Blue).

When the camera mode is selected by the key input device 68, the TG (Timing Generator) 16 is activated by the CPU 44. TGI 6 generates multiple timing signals including horizontal sync signal Hsync and vertical sync signal Vsync. The Each of drivers 14a and 14b drives CCD imager 12 in response to such timing signals. As a result, a charge image signal corresponding to one frame is output from the CCD imager 12. The vertical synchronization signal Vs ync is generated every 1Z30 seconds, and the raw image signal output from the CCD imager 12 has a frame rate of 30 fps.

Referring to FIG. 2, the imaging surface of CCD imager 12 has partial imaging areas IML and IMR. The partial imaging area IML is formed on the left side of the boundary line BL extending vertically from the center of the imaging surface, and the partial imaging area IMR is formed on the right side of the same boundary line BL. As can be seen from Fig. 3, the imaging surface has a resolution of horizontal 1324 pixels x vertical 9696 pixels. Each of the partial imaging areas IML and IMR has a resolution of horizontal 662 pixels × vertical 996 pixels. Therefore, the partial imaging areas IML and IMR touch each other at the boundary line.

The effective area irradiated with the optical image is an area of horizontal 1300 pixels x vertical 975 pixels allocated almost at the center of the imaging surface.

A plurality of vertical transfer registers (not shown) are assigned to each of the partial imaging areas IML and IMR. Further, the horizontal transfer register HL is assigned to the partial imaging area IML, and the horizontal transfer register HR is assigned to the imaging area IMR. Therefore, the charges generated by the plurality of light receiving elements on the partial imaging area IML are output from the channel CH 1 via the vertical transfer register and the horizontal transfer register HL (not shown). Similarly, the charges generated by the plurality of light receiving elements on the imaging area IMR are also output from the channel CH2 via a vertical transfer register (not shown) and the horizontal transfer register HR.

In other words, the dryino I 4 a performs a raster scan (interlaced scan) on the partial image area IML based on the timing signal from the TG 16, and outputs the raw image signal of the left 12 frames from the channel CH1. Similarly, the driver 14b performs raster scanning (interlace scanning) on the imaging area IMR based on the timing signal from the TG16, and outputs the raw image signal of the right 12 frames from the channel CH2. However, the transfer direction of the horizontal transfer register HR is the opposite of the transfer direction of the horizontal transfer register HL. For this reason, the last evening scanning direction is also the partial imaging area IML. And I MR invert each other.

Returning to Fig. 1, in response to the timing signal from TG16, the CDSZAGCZAD circuit 18a performs a series of processes such as correlated double sampling, automatic gain adjustment, and AZD conversion on the raw image signal of channel CH1. 〇03 / ^/ 080 〇80 circuit 1 8b In the same way, in response to the timing signal from TG16, it correlates with the raw image signal of channel CH2 A series of processing of double sampling, automatic gain adjustment and AZD conversion Apply. The timing signal has a frequency of 27 MHz. Therefore, each of the CDS / AGCZAD converters 18a and 18b outputs raw image data as a digital signal at a clock rate of 27 MHz.

The channel matching circuit 22 provided in the AS IC 20 cuts out the raw image data given from each of the A / D converters 18a and 18b, and performs a series of matching processes such as clamping and white balance adjustment. Raw image data belonging to the valid area is extracted by a clipping process. The level difference between channels is eliminated by the clamping process. The white balance deviation is eliminated by the white balance adjustment process. This matching process is executed in response to the timing signal output from TG16. The channel matching circuit 22 issues a write request to the SDRAM controller 30 every time a predetermined amount of matching processing is completed.

The SDRAM controller 30 is configured as shown in FIG. The request issued by the channel matching circuit 22 is given to the arbitration circuit 30a. In addition to the channel matching circuit 22, the arbitration circuit 30a includes a signal processing circuit 24, an MPEG codec 26, a D4-I / F 28, an XBUS-I / F 34, a stream I / F 36, a CCD output circuit 38, D 1—Receives requests from I-NO F 40 and CPU 44 and accepts any one request according to preset priority. The arbitration circuit 30a gives an approval signal to the issuer of the approved request, and instructs the memory access circuit 30b to perform processing corresponding to the approved request.

7 If the approved request is a write request, the memory access circuit 3 Ob writes a predetermined amount of data transferred from the issuer of the write request via the path B 1 or B 2 to the SDRAM 32. If the approved request is a read request, the memory access circuit 30 b A predetermined amount of data according to the request is read from SDR AM 32, and the read data is transferred to the issuer of the read request via bus B1 or B2.

In this way, data transfer via the bus B 1 or B 2 is executed intermittently in a time division manner. This avoids collisions in the evening.

Returning to FIG. 1, the channel matching circuit 22 transfers the fixed amount of raw image data that has undergone the matching process to the SD RAM controller 30 through the path B 1. The raw image data given from the channel matching circuit 22 is written into the raw image area 3 2 a (see FIG. 4) by the SD RAM controller 30. The raw image data of channel C H 1 is written to the left side of the raw image area 3 2 a, and the raw image data of channel C H 2 is written to the right side of the raw image area 3 2 a. In this way, raw image data of horizontal 1300 pixels x vertical 975 pixels representing one frame object scene image is secured in the raw image area 3 2 a.

The signal processing circuit 24 repeatedly issues a read request to the SDRAM controller 30 in order to read the raw image data stored in the raw image area 3 2 a by a predetermined amount. The raw image data read by the SD RAM controller 30 is given to the signal processing circuit 24 through the scan B 1. The signal processing circuit 24 performs processing such as color separation and YUV conversion on the transferred raw image data. This series of processing is executed at a clock rate of 54 MHz.

By repeating this process, a YUV image data having a resolution of horizontal 1280 pixels X vertical 720 pixels is generated at a rate of one frame per 1300 seconds. The YUV image data generated in this way is transferred to the SDRAM controller 30 by a predetermined amount through the bus B1. At this time, the write request is repeatedly issued, and the YUV image data is written into the moving image area 3 2 b (see FIG. 4) by the SDRAM controller 30.

Since the resolution of the raw image data is horizontal 1300 pixels x vertical 975 pixels, the aspect ratio of the image based on this raw image data is 4: 3. In contrast, the resolution of the YUV image data generated by the signal processing circuit 24 is horizontal 1280 pixels x vertical 720 pixels, so the aspect ratio of the image based on this YUV image data is 1 6: 9. Therefore, when generating YUV image data, The vertical ends of the evening are partially removed.

The D 1—I / F 40 repeatedly issues a read request to the SDRAM controller 30, and reads YUV image data stored in the moving image area 32b by a predetermined amount. The YUV image data is read out from the moving image area 32b in a raster scanning manner (interlaced scanning manner), and given to the D1-I / F 40 via the path B1. At this time, the YUV image data is input to D1-I / F40 at a rate of 1 frame per 1Z30 seconds.

D l— lZF4 (Hi, format conversion processing is applied to the given YUV image data. This processing is performed according to the 27 MHz clock rate, and the processed YU V image data is 720 pixels horizontal by X vertical. It has a resolution of 480 pixels and an aspect ratio of 4: 3 In this way, YUV image data conforming to the D1 standard is generated at a rate of 1 frame per 1/30 second.

The aspect ratio of YUV image data given to D1-IZF40 is 16: 9, while the aspect ratio of YUV image data output from D1-IZF40 is 4: 3. . Therefore, letterpox components are assigned to both ends in the vertical direction of the YUV image data output from D1-IZF40.

The YUV image data generated by D 1-I / F 40 is output to D 1—IZF 52 provided in AS I C 42. D l—IZF52 also captures YUV image data according to a clock rate of 27 ζ ζ. D 1—The I / F 52 issues a write request to the SDRAM controller 56 every time a predetermined amount of YUV image data is fetched, and when this request is approved, the predetermined amount of YUV image data is sent to the bus B 3. To the SDRAM controller 56. Referring to FIG. 7, SDRAM controller 56 is formed by arbitration circuit 56a and memory access circuit 56b, similarly to SDRAM controller 39 shown in FIG. Further, the arbitration circuit 56 a and the memory access circuit 56 b operate in the same manner as the arbitration circuit 30 a and the memory access circuit 30 b shown in FIG. Therefore, duplicate descriptions are omitted.

Returning to FIG. 1, the SDRAM controller 56 writes a predetermined amount of YUV image data transferred from the D 1—I 52 in the moving image area 54 b (see FIG. 5). YUV image data is written to the video area 54b at a rate of 1 frame per 1/30 second.

The NTSC encoder 62 repeatedly issues a read request to the SDRAM controller 56 in order to read out the YUV image data stored in the moving image area 54b by a predetermined amount. The YUV image data is read out by the SDRAM controller 56 and supplied to the NTS C encoder 62 through the bus B3.

The NTS C encoder 62 converts the supplied YUV image data into an NTS C format composite video signal. The composite video signal is also generated at a rate of 1 frame per 1/30 second, and the generated composite video signal is output to the LCD monitor 66. As a result, a real-time moving image (through image) of the object scene is displayed on the monitor screen as shown in Fig. 8 (B).

When the D4-IZF 28 is connected to an HDTV (not shown), the CPU 44 activates the D4-I / F 28 instead of the D1-IZF 40 or together with the D1-IZF 40. D4—IZF 28 reads the YUV image data stored in the moving image area 32 b by a predetermined amount through path B 1 and SDRAM controller 30. YUV image data is read out in a lath scanning mode (sequential scanning mode) according to a frame rate of 30 f ps. D4—IZF28 converts the read YUV image data into a video signal conforming to the D4 standard, and outputs the converted video signal to HDTV. As a result, a high-quality through image is displayed on the TV screen as shown in Fig. 8 (A).

When the moving image recording start operation is executed by the key input device 68, the MPEG4 codec 26 and the stream IZF 36 are activated by the CPU 44. The MP 4 codec 26 reads out the YUV image data stored in the moving image area 32 b (see FIG. 4) of the SDRAM 32 by a predetermined amount in the same manner as described above. That is, a read request is repeatedly issued to the SDRAM controller 30, and Y UV image data is acquired by a predetermined amount through the bus B1. The acquired YUV image data is compressed according to the MPEG4 format. Such read processing and compression processing are executed at a rate of one frame per 130 seconds.

The MPEG4 stream generated by the compression process is the same as that described above. A predetermined amount is supplied to the SDR AM controller 30 through 1 and written in the MPEG area 32 c of the SDRAM 32 (see FIG. 4).

The stream I / F 36 reads the MP EG 4 stream stored in the MPEG area 32 c by a predetermined amount through the bus B 1 and the SDRAM controller 30 and reads the read MPEG 4 stream to the stream provided in the AS I C 42. Output to IZF 48. The stream IZF 48 gives the given MP EG4 stream to the SDRAM controller 56 by a predetermined amount through the bus B 3 and writes it to the MP EG area 54 c (see FIG. 5) of the SDRAM 54.

The CPU 44 repeatedly issues a read request to the SDRAM controller 56 in order to read the MPEG4 stream stored in the MPEG area 54c in a fixed amount. The MP EG4 stream read by the SDRAM controller 56 is given to the card I / F 58 through the bus B 4 and is recorded in the memory card 64 by the card I / F 58. The MPEG4 stream is stored in an MP EG file formed on the memory card 64. When the moving image recording end operation is performed, the MP EG 4 codec 26 and the stream I / F 36 are stopped by the CPU 44, thereby ending the moving image recording process.

When a still image recording operation is performed during or after the moving image recording process, the CPU 44 activates the CCD output circuit 38, the signal processing circuit 50, and the JPEG codec 60. The CCD output circuit 38 issues a read request to the SDRAM controller 30 to read a predetermined amount of the raw image data of one frame from the raw image area 32 a of the SDRAM 32 (see FIG. 4). The raw image data read by the S DRAM controller 30 is given to the CCD output circuit 38 via the bus B1. The CCD output circuit 38 outputs one frame of raw image data thus given to the signal processing circuit 50 provided in the AS IC 42.

The signal processing circuit 50 performs processing such as color separation and YUV conversion on the raw image data given from the CCD output circuit 38, and as shown in Fig. 8 (C), the resolution of 1280 pixels horizontal x 960 pixels vertical and 4 : YUV image data having an aspect ratio of 3 is generated. The generated YUV image data is sent to SDRAM controller via bus B3. After being given to the roller 56, it is written in the still image area 54d of the S DRAM 54 (see FIG. 5).

The J PEG codec 60 repeatedly issues a read request to the SDRAM controller 56 to read the YUV image data stored in the still image area 54 d by a predetermined amount. The YUV image data is read out by the SDRAM controller 56 and supplied to the J PEG codec 60 via the bus B 3. The J PEG codec 60 performs J PEG compression on the given YUV image data, and repeatedly requests the SDR AM controller 56 to write the compressed image data, that is, J PEG data. The SDRAM controller 56 writes the J PEG data given from the J PEG codec 60 through the bus B 3 into the JP EG area 54 a of the SDR AM 54. ,

The CPU 44 reads one frame of JPEG data secured in the JPEG area 54 a in this way through the bus B4 and the SDRAM controller 56 by a predetermined amount, and reads the read JPEG data into the bus B4 and card IZF. Record to memory card 64 through 58. As a result, a J PEG file is created in the memory card 64.

When the playback mode is selected by the key input device 68 and the desired MP EG file recorded on the memory card 64 is selected, the CPU 44 accesses the memory card 64 through the bus B 4 and the power I / F 58. Play the MP EG 4 stream from the desired MPEG file. The reproduced MP EG 4 stream is given to the SDRAM controller 56 by a predetermined amount through the bus B 4 and written into the MPEG area 54 c (see FIG. 5) of the SDRAM 54 by the SDRAM controller 56.

The stream IZF 48 repeatedly issues a read request to the SDRAM controller 56, and reads the MPEG 4 stream stored in the MP EG area 54c by a predetermined amount. The read MP EG 4 stream is given to the stream IZF 48 through the bus B3 and then outputted to the stream IZF 36.

Stream IZF36 writes a given MP EG 4 stream to SD Requests to the RAM controller 30 repeatedly. The SDRAM controller 30 writes the MPEG4 stream supplied from the stream IZF 36 through the bus B 1 to the MPEG area 32 c of the SDRAM 32 (see FIG. 4).

The MPEG4 codec 26 reads the MP EG 4 stream stored in the MP EG area 32 c by a predetermined amount through the SDRAM controller 30. The read MPEG4 stream is given to the MPEG4 codec 26 through path B1 and decompressed according to the MPEG4 format. The decompressed YUV image data is output from the MP EG4 codec 26 at a rate of 1 frame per 1/30 second, and given to the SDRAM controller 30 through the bus B 1 by a predetermined amount. After that, the YUV image data is written in the moving image area 32 b (see Fig. 4) of SDRAM32. '

The D 1—IZF 40 reads YUV image data from the moving image area 32 b through the SDRAM controller 30 and performs the same format conversion processing as described above on the YUV image data input through the bus B 1. The resolution of YUV image data is reduced from horizontal 1280 pixels x vertical 720 pixels to horizontal 720 pixels x horizontal 480 pixels, and letterbox components are assigned to both ends of the reduced YUV image data in the vertical direction. This YUV image data is also created at a rate of 1 frame per 1 to 30 seconds, and the created YUV image data is output to D 1—IZF 52.

As above, SDRAM 32 forces, etc. Data transfer to D 1—I ZF 40 is performed according to a clock rate of 54 MHz, and data transfer from D 1—I / F 40 to D 1 -I / F 52 is 27 MH It is executed according to the clock rate of z.

The D 1 -I / F 52 supplies the YUV image data of each frame given from the Dl—IZF 40 to the SDRAM controller 56 by a predetermined amount through the path B 3. The YUV image data is written into the moving image area 54b (see FIG. 5) of the SDRAM 54 by the SDRAM controller 56.

The NT SC encoder 62 reads the YUV image data stored in the moving image area 754b by a predetermined amount through the SDRAM controller 56 and converts the YUV image data given through the bus B 3 into an NT SC composite video signal. To do. Read processing and conversion processing are also executed at a rate of 1 frame per 30 seconds. It is. The converted composite video signal is output to the LCD monitor 66, whereby the playback moving image is displayed on the monitor screen in the manner shown in FIG. 6 (B).

When D4—IZF28 is connected to an HDTV, D4—I / F 28 is activated along with D1—IZF40 or with D1—IZF40. D4—The IZF 28 reads YUV image data from the moving image area 3 2b (see FIG. 4) of the SDRAM 32 through the SDRAM controller 30. The YUV image data for each frame is read out in the last evening scanning mode (sequential scanning mode) every 1Z30 seconds, and given to D4_I / F 28 through bus B1.

D4—IZF28 converts the provided YUV image data into a video signal conforming to the D4 standard, and outputs the converted video signal to the HDTV. As a result, high-quality playback video is displayed on the TV screen as shown in Fig. 6 (A).

When the desired JPEG file is selected with the playback mode selected, the CPU 44 accesses the memory card 64 through path B 4 and card I / F 58, and stores the J JPEG file stored in the desired J PEG file. Play the PEG video. The reproduced J PEG data is written into the J PEG area 54a (see FIG. 5) of the S DRAM 54 through the bus B 4 and the SDRAM controller 56.

The J PEG codec 60 reads the J PEG data stored in the J PEG area 54a by a predetermined amount through the SDRAM controller 56, and decompresses the J PEG data given through the bus B3. The JPEG codec 60 further requests the SDRAM controller 56 to write the extended YUV image data. The SDRAM controller 56 writes the YUV image data transferred through the path B 3 in the still image area 54 d of the SDRAM 54 (see FIG. 5).

The NTS C encoder 62 reads the YUV image data stored in the still image area 54d through the bus B 3 and the SDRAM controller 56, and converts the read YUV image data into an NTSC C composite video signal. At this time, the resolution is reduced from horizontal 1280 pixels x vertical 960 pixels to horizontal 720 pixels x horizontal 480 pixels. The read process and conversion process are executed at a rate of 1 frame per 1300 seconds, as described above. The converted composite video signal is output to the LCD monitor 66, and the playback still image is displayed on the monitor screen. Indicated.

When D4-I / F28 is connected to HDTV, XBUS—I / F46 is activated instead of NTS C encoder 62. XBUS—IZF46 reads YUV image data from still image area 54d through bus B4 and SDRAM controller 56, and reads the read YUV image data to XBUS—I / F 34 provided in AS I C20. Output to. The XBUS—I / F 34 writes the given Y UV image data through the bus B 2 and the SDRAM controller 30 to the still image area 32 d (see FIG. 4) of the SDRA M32 by a predetermined amount.

D4—IZF 28 reads a predetermined amount of YUV image data from static image area 32 d through bus B 1 and SDRAM controller 30, and converts the read YUV image data into a D4 standard video signal. The reading process and conversion process are executed at a rate of 1 frame per 1 Z 30 seconds. The converted video signal is output to the HD TV, and as a result, a high-quality still image is displayed on the TV screen. The resolution of YUV image data read from the still image area 32d is 1280 pixels x 960 pixels horizontally, while the resolution of the video signal output to the HDTV is 1280 pixels x 720 pixels vertically. Therefore, a still image that is partially missing at both ends in the vertical direction is displayed on the TV screen.

As can be seen from the above explanation, the raw image data (first moving image data) output from each of the circuits 03a and 18b 18a and 18b is transmitted by the channel matching circuit 22 (capture means). It is fetched and written to SDRAM32 (first memory) through bus B 1 (first bus). The raw image data stored in the first memory is read through the bus B 1 and subjected to processing (first processing) such as color separation and YUV conversion by the signal processing circuit 24 (first processing means). The YUV image data (second moving image data) created by the signal processing circuit 24 is written to the SDRAM 32 through the path B 1. The YUV image data stored in the SDRAM 32 is read out via the bus B1, and output processing directed to the HDTV (first monitor) is performed by the D4-IZF28 (first output means). As a result, the corresponding video is displayed on the HDTV screen.

D 1-I / F40 (reduction measure) reads from SDRAM 32 through bus B 1 Reduce the resolution of the output YUV image data. The low-resolution YUV image data (third moving image data) is written to SDRAM 54 (second memory) through path B 3 (second bus). The YUV image data stored in the SDRAM 54 is read through the bus B 3 and subjected to output processing directed to the LCD monitor (second monitor) by the NTSC encoder 62 (second output means). As a result, the corresponding moving image is displayed on the second monitor screen.

In this way, a series of processes for creating HDTV YUV image data is executed using the bus B 1 and the SDRAM 32. A series of processing for creating YUV image data for the LCD monitor 66 is executed using the bus B 3 and the SDRAM 54. Here, the resolution of YUV image data for HDTV is higher than the resolution of YUV image data for LCD monitors. In other words, bus B 1 and SDRAM 32 are used for high-speed processing such as high-resolution video data processing, and bus B 3 and SDR for low-speed processing such as low-resolution video processing. AM54 is used. As a result, processing that conforms to multiple formats can be executed without causing failure.

When a moving image recording operation is performed, YUV image data read from the SDRAM 32 through the path B 1 is compressed by the MPEG codec 26 (first compression means). The MPEG4 stream (fourth moving image data) created in this way is written to the SDRAM 32 through the bus B1. High-speed compression processing is realized by transferring both the uncompressed YUV image data and the compressed MP EG 4 stream using the common path B1.

The MP EG 4 stream is then read from SDRAM 32 via bus B 1 and written to SDRAM 54 via path B 3. Thereafter, the MPEG4 stream is read from the SDRAM 54 through the bus B 3 and recorded on the memory card 64 (recording medium) by the card I / F 58 (moving image recording means). When a still image recording operation is performed, one frame of raw image data (first still image data) is extracted by the CCD output circuit 38 (second processing means), and YUV image data (second still image data) is extracted. ) Is converted to. The converted YUV image data is written to the SD RAM 54 through path B 3, and then subjected to JPEG compression and memory power. — Recorded at 58. By using bus B2 and SDRAM54 for still image data processing (low-speed processing) that does not cause frame rate problems, processing failures are avoided.

In this embodiment, a CCD imager is used as the image sensor, but other image sensors such as a CMOS imager may be adopted instead. In this embodiment, the J PEG method is adopted as a still image compression method, but the J PEG 2000 method may be adopted instead. Furthermore, in this embodiment, the MP EG 4 system is adopted as the moving picture compression system, but other video compression systems such as the MJ PEG system, the MJ PEG2000 system, or the H.264 system are employed instead. May be.

Although the invention has been described and illustrated in detail, it is clear that the invention has been used merely as an illustration and example and should not be construed as limiting, the spirit and scope of the invention being attached Limited only by the wording of the claims.

Claims

The scope of the claims

1. An image processing device comprising:

Means for capturing the first moving image data to be written to the first memory through the first bus;

A first process for performing a first process on the first moving image data read from the first memory through the first bus and generating a second moving image data to be written to the first memory through the first bus. Means;

First output means for performing an output process directed to the first monitor on the second moving image data read from the first memory power ^ through the first bus;

Reducing means for reducing the resolution of the second moving image data read from the first memory through the first bus and creating third moving image data to be written to the second memory through the second pass. ;and

Second output means for applying an output process directed to the second monitor to the third moving image data read from the second memory through the second bus;

2. An image processing apparatus according to claim 1, wherein the first moving image data is data in which any one of a plurality of colors is assigned to each pixel, and the first processing is performed for all of the plurality of colors. Color processing for assigning to each pixel.

3. An image processing apparatus according to claim 1, wherein the second moving image data has a first resolution corresponding to a first aspect ratio, and the third moving image data is a second case. A second resolution corresponding to the image ratio.

4. An image processing apparatus according to claim 3, wherein the first aspect ratio is 16: 9, and the second aspect ratio is 4: 3.

5. An image processing device according to claim 1, wherein the second moving image data and the third moving image data have the same frame rate.

6. An image processing apparatus according to claim 1, wherein the capturing means includes imaging means for periodically imaging the object scene.

7. An image processing device according to claim 6, wherein the imaging means has an imaging surface on which a plurality of partial imaging areas are formed and a plurality of output paths respectively assigned to the plurality of partial imaging areas. And the capturing means includes the plurality of output paths. Further, a creation means for creating the first moving image data based on the electric charge output from the path is further included.

8. An image processing apparatus according to claim 1, wherein the first bus is compressed in the first memory by compressing a data amount of the second moving image data read from the first memory through the first bus. The first compression means for creating the fourth moving image data to be written through is further provided.

9. An image processing apparatus according to claim 8, wherein the first compression means executes a compression process when a first predetermined operation is performed.

1 0. An image processing apparatus according to claim 8, further comprising: fourth moving image data read from the first memory through the first bus to the second memory; First writing means for writing through a bus; and moving image recording means for recording the fourth moving image data read from the second memory through the second bus on a recording medium.

1 1. An image processing device according to claim 1, wherein the second processing is performed on the first still image data of one frame forming the first moving image data, and the second memory is passed through the second bus. It further includes a second processing means for creating second still image data to be written.

1 2. An image processing device according to claim 1 1, wherein the second processing means executes the second processing when a second predetermined operation is performed.

1 3. An image processing device according to claim 1 1, wherein the amount of second still image data read from the second memory through the second pass is compressed and stored in the second memory. The apparatus further comprises second compression means for creating third still image data to be written through the second bus.

1 4. The image processing device according to claim 13 further comprising still image recording means for recording the third still image data created by the second compression means on a recording medium.