WO2006059775A3 - Processeur a reconfiguration dynamique - Google Patents

Processeur a reconfiguration dynamique Download PDF

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Publication number
WO2006059775A3
WO2006059775A3 PCT/JP2005/022401 JP2005022401W WO2006059775A3 WO 2006059775 A3 WO2006059775 A3 WO 2006059775A3 JP 2005022401 W JP2005022401 W JP 2005022401W WO 2006059775 A3 WO2006059775 A3 WO 2006059775A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic circuit
disclosed
configuration information
circuit configuration
reconfigurable processor
Prior art date
Application number
PCT/JP2005/022401
Other languages
English (en)
Other versions
WO2006059775A2 (fr
Inventor
Kazuaki Murakami
Makoto Shuto
Lovic Gauthier
Takuma Matsuo
Tetsuya Hasebe
Shuichi Kikuchi
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/267,026 external-priority patent/US20060242385A1/en
Priority claimed from JP2005338457A external-priority patent/JP4390211B2/ja
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to EP05814535A priority Critical patent/EP1836601A2/fr
Publication of WO2006059775A2 publication Critical patent/WO2006059775A2/fr
Publication of WO2006059775A3 publication Critical patent/WO2006059775A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

L'invention porte sur un procédé qui permet de produire une architecture de segment d'instructions (dénommée ci-après 'ISA' pour 'instruction set architecture') et une série d'informations de configuration de circuit logique d'un processeur pour l'exécution d'un programme d'applications issu d'un programme d'applications décrit dans un langage de haut niveau. L'invention concerne également une technique de plateforme de développement de LSI personnalisable qui permet de concevoir, développer et fabriquer un LSI pesonnalisé spécifique d'application en peu de temps en appliquant l'architecture ISA et les informations de configuration de circuit logique produites à un processeur à circuit logique pouvant être reconfiguré de manière dynamique. L'invention se rapporte aussi à un processeur à reconfiguration dynamique, que l'on peut reconfigurer au moyen des informations de configuration de circuit logique produites. L'invention concerne enfin des procédés associés.
PCT/JP2005/022401 2004-11-30 2005-11-30 Processeur a reconfiguration dynamique WO2006059775A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05814535A EP1836601A2 (fr) 2004-11-30 2005-11-30 Processeur a reconfiguration dynamique

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2004345400 2004-11-30
JP2004-345400 2004-11-30
US11/267,026 2005-11-04
US11/267,026 US20060242385A1 (en) 2004-11-30 2005-11-04 Dynamically reconfigurable processor
JP2005-338457 2005-11-24
JP2005338457A JP4390211B2 (ja) 2004-11-30 2005-11-24 カスタムｌｓｉ開発プラットフォーム、命令セット・アーキテクチャ及び論理回路構成情報の生成方法、並びにプログラム

Publications (2)

Publication Number Publication Date
WO2006059775A2 WO2006059775A2 (fr) 2006-06-08
WO2006059775A3 true WO2006059775A3 (fr) 2006-08-17

Family

ID=35705273

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/022401 WO2006059775A2 (fr) 2004-11-30 2005-11-30 Processeur a reconfiguration dynamique

Country Status (3)

Country Link
EP (1) EP1836601A2 (fr)
KR (1) KR20070097051A (fr)
WO (1) WO2006059775A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379706B2 (en) 2012-05-02 2016-06-28 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7073069B1 (en) * 1999-05-07 2006-07-04 Infineon Technologies Ag Apparatus and method for a programmable security processor
KR102025694B1 (ko) * 2012-09-07 2019-09-27 삼성전자 주식회사 재구성 가능한 프로세서의 검증 방법
KR102032895B1 (ko) 2013-01-28 2019-11-08 삼성전자주식회사 기능 유닛들 간의 기능 로직 공유 장치, 방법 및 재구성 가능 프로세서
US10445092B2 (en) * 2014-12-27 2019-10-15 Intel Corporation Method and apparatus for performing a vector permute with an index and an immediate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5752035A (en) * 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5933642A (en) * 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US6182206B1 (en) * 1995-04-17 2001-01-30 Ricoh Corporation Dynamically reconfigurable computing using a processing unit having changeable internal hardware organization

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5752035A (en) * 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5933642A (en) * 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US6182206B1 (en) * 1995-04-17 2001-01-30 Ricoh Corporation Dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379706B2 (en) 2012-05-02 2016-06-28 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device

Also Published As

Publication number Publication date
WO2006059775A2 (fr) 2006-06-08
KR20070097051A (ko) 2007-10-02
EP1836601A2 (fr) 2007-09-26

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