WO2006059262A1

WO2006059262A1 - An integration method for conductive interconnects

Info

Publication number: WO2006059262A1
Application number: PCT/IB2005/053893
Authority: WO
Inventors: Laurent Gosset
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-12-01
Filing date: 2005-11-24
Publication date: 2006-06-08

Abstract

A method of forming air gaps (13) between adjacent interconnects (3), wherein the interconnects (3) are embedded in a first dielectric layer (1) and encapsulated on the sides and bottom in an outer barrier layer (4). Trenches (7) are etched by removing the dielectric material between the interconnects (3), and, subsequently, a supplemental barrier layer (15) is provided (at least) on the sides of the interconnects (3) over what may be left of the outer barrier layer (4). Finally, the air gaps (13) are formed by non-conformal CVD of a second dielectric layer (16). The supplemental barrier layer (15) supplements or even replaces the outer barrier layer (4) which may be degraded by the etching process.

Description

An integration method for conductive interconnects

FIELD OF THE INVENTION

This invention relates generally to a method of manufacturing an integrated circuit, comprising forming a plurality of conductive interconnects on an integrated circuit die. It finds notably its application in the field of the CMOS technology.

BACKGROUND OF THE INVENTION

Due to the constant shrinking of the critical dimensions in ULSI (ultra large scale integrated) circuits in order to meet integration requirements, delay and crosstalk related to the interconnection part of the circuit become limiting factors for speed and logical performance. The relatively recent move from Aluminium to Copper interconnects has yielded a 30% reduction in the resistance of wired connections on a chip, and there is now a drive to achieve better isolation between lines by introducing insulators with lower dielectric constant than that of the traditionally used material, silicon dioxide (which has a dielectric constant, k, of 4.2).

This approach is relatively expensive, as it clearly requires new material development and integration at each technology node. Furthermore, the multilevel integration of extreme low-k (i.e. k<2) materials into production processes raises several challenges that could potentially impact device reliability, in areas such as leakage, mechanical instability and joule heating, driving up the cost of integrating newly developed ultra- low-k materials into new CMOS process generations. In addition, the barrier and cap layers associated with these materials tend to increase the effective permittivity of the final dielectric stack.

For these reasons, and also because a vacuum is the best insulator available, there has been significant effort made in the integration of air gaps between intra-level lines. In one embodiment of the prior art, these so-called air gaps are, in fact, residual voids made in the bulk dielectric during the material deposition, with the very low pressure of residual trapped gas making the permittivity of the gap very close to that of a perfect vacuum (k=l). Very low effective k values can thus be achieved, and consequently excellent propagation times and very low crosstalk levels have been shown to be attainable.

There are various known ways in which the above-mentioned air gaps can be produced. Among all of the different techniques proposed, two main techniques have been developed to define air gap trench formation areas in between the metal lines, thereby introducing the need for a chemical treatment and/or dry etching (e.g. reactive ion etching) process that may weaken the integrity of the complete interconnect stack.

In a first, known technique, described in, for example, US Patent No. 6,451,669, it has been demonstrated that the introduction of a dedicated air-gap mask at each metal level can assist in precisely defining the areas in which air gaps are required. Referring to Figure Ia of the drawings, this technique comprises forming a dielectric layer 1 on a substrate 2 (which may correspond to an intermediary manufacturing level of an integrated circuit. Copper interconnect lines 3 are embedded in the dielectric layer 2 with a barrier/bonding layer 4 therebetween. The barrier/bonding layer 4, which may comprise, for example tantalum or tantalum nitride, serves several key functions. First, it provides a mechanical constraint on the conductive interconnect 3 against electromigration-driven mass transport of copper out of the interconnect structures. This helps prevent open circuits caused by diffusion of interconnect material out of the original interconnect to leave a cavity, and short circuits caused by the build up of interconnect material outside the original interconnect to form a protrusion. In addition, the layer 4 can protect the wiring 3 from exposure to gaseous environmental contaminants in the air gap (such as oxygen), and block possible migration pathways for atoms of interconnect material which might otherwise find their way to components, such as transistors, in the semiconductor substrate (not shown) in or below the substrate 2. In the described embodiment of the prior art, a thin layer 5 of insulating material (or

"dielectric liner") is provided above the metal line, on which insulating layer 5 is selectively deposited a mask or resist layer 6 is deposited to provide so-called "capping" in respect of respective interconnects 3. After exposure, the liner 5 and then the dielectric 1 are etched to form trenches 7, as shown in Figure Ib of the drawings. The etching process typically used is a reactive ion etching (RIE) process, in which plasma systems are used to ionize reactive gases, and the ions are accelerated to bombard the surface. Etching occurs through a combination of the chemical reaction and momentum transfer from the etching species.

However, quite apart from the cost of employing an additional mask, this approach faces a significant integration issue caused by the misalignment of the masks relative to the metal lines. In the theoretical optimum case described above with reference to Figures Ia and Ib, in which the masks 6 are precisely aligned with the copper interconnects 3, all of the dielectric material 2 between adjacent copper lines 3 can be removed, leaving the copper line surface untouched during the etching process. However, referring to Figure 2a of the drawings (in which the dielectric liner has been omitted for simplicity), there will inevitably be some misalignment between the different lithography steps some of the copper lines 3 will remain uncapped, as shown. As a consequence, and referring to Figure 2b of the drawings, during the etching process, not only is the metal barrier 4 and the copper interconnect attacked (as indicated by the arrow A), but some metallic residues and polymers 8 are also deposited at the bottom of the trenches 7, thus causing some dielectric to remain (this is known as the "grass" effect). On the other hand, since this is not a self-aligned process, it is necessary to normalize the air gap trench widths and, therefore, the intra-metal level coupling capacitance values. This consists in completely removing the unetched dielectric protected by the misaligned masking portions 6 during the etching process as well as the residues 8 at the bottom of the trenches 7. This is typically achieved by means of a chemical treatment, such as an isotropic treatment using hydrofluoric acid (HF), although it will be appreciated that the chemical treatment used will depend on the sacrificial material required to be removed and/or the post-etching residues. Referring to Figure 2c of the drawings, it is well known that HF can degrade poor metal barrier quality. For instance, diluted HF dipping is used as a standard characterization test for TaN barrier integrity evaluation to check the conformity of the TaN barrier. As a consequence, it is of great importance to limit or prevent any degradation of the interconnect stack which may occur during etching treatments. In the example described above, the HF attack potentially leads to partial or complete degradation of the copper (at 9) and the metal barrier (at 10), depending on HF concentration, attack duration and barrier properties (material composition, thickness, density, orientation), leading to weak points in the interconnect stack, which in turn leads to reliability issues, such as copper diffusion, mechanical instability, stress voiding and electromigration issues. Referring to Figure 3a of the drawings, another proposed technique involves introducing a self-aligned barrier 11 on the copper lines 3 by, for example, depositing CoWP thereon using an electroless process (see, for example, EJ. O'Sullivan et al, IBM Res. Develop. 42, no 5, p. 607-619 (1998)). Direct etching of the trenches 7 is then achieved by means of an etching process, typically using HF (see Figure 3b), during which process the metal barrier 4 may once again be removed (indicated at 12 in Figure 3c), such that when the air gaps 13 are fabricated using a non-conformal CVD process, as shown in Figure 3d, efficiency against copper diffusion is not completed (as indicated at 14).

In an attempt to obviate the need for expensive dedicated air gap masks, it has also been proposed to directly etch the trenches (without masking the copper lines). During trench formation using the above-mentioned RIE technique, uncapped copper is thus submitted to the plasma, which leads to the deposition of residues in the bottom of the trenches. At the same time, the metal (TaN or Ta) barrier is also degraded during exposure to the RIE process. As a result, an additional cleaning step is required to be performed to completely remove the dielectric and achieve the perfect trench shape (using, for example, a HF treatment, as before), which can further degrade the barrier.

In yet another approach, it has been proposed that it may be softer to the copper surface to employ a specific wet chemical etching treatment to remove a "sacrificial" dielectric layer, such as (but not limited to) undoped silicon glass (USG). In this approach, once the final multilevel interconnect module is completed, the sacrificial embedded USG layers are successively attacked and decomposed using a diluted HF solution. Moreover, a single, relatively inexpensive air gap mask with large open areas can be added to precisely control HF diffusion, but there is still the risk of some degradation of the barrier 4 due to exposure thereof to HF.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a method of manufacturing an integrated circuit in which degradation of the interconnect barrier efficiency is minimized. In accordance with the present invention, there is provided a method of manufacturing an integrated circuit, comprising forming a plurality of conductive interconnects on an integrated circuit die, embedding said plurality of conductive interconnects in one or more layers of dielectric material to form a trench between adjacent interconnects, and subsequently selectively depositing a supplemental barrier layer on at least one of the exposed surfaces of said interconnects. The present invention also extends to an integrated circuit comprising a plurality of interconnects formed by means of the above-mentioned method.

In accordance with an exemplary embodiment of the present invention, the interconnects are embedded in a first layer of dielectric material, said first layer of dielectric material is etched so as to form a trench between adjacent interconnects, and the supplemental barrier layer is subsequently deposited on at least one of the exposed surfaces of said interconnects, the method further comprising subsequently non-conformal depositing a second layer of dielectric material over said interconnects and in said trenches so as to form air gaps in said second layer of dielectric material corresponding to the location of said trenches. This exemplary embodiment of the present invention extends to an integrated circuit comprising a plurality of interconnects, wherein air gaps formed by the above-mentioned method are provided between adjacent interconnects, and to a method of manufacturing such an integrated circuit. The integrated circuit may comprise a multi- level interconnect structure, in which case, each interconnect level is sequentially formed with the respective air gaps therein.

Beneficially, prior to etching the trenches, at least the surfaces of the interconnects embedded within the first layer of dielectric material are provided with an outer barrier layer, which is beneficially conductive (e.g. Tantalum or Tantalum nitride), and after etching of the trenches, at least the surfaces embedded within the first layer of dielectric material, and adjacent thereto (i.e. the side surfaces) are provided with the supplemental barrier layer, to supplement or replace the outer barrier layer which may have been degraded during the etching process.

The supplemental barrier layer is also preferably conductive, i.e. metallic, and may, for example, comprise a self-aligned Co-based barrier (e.g. CoWP or CoWB metal liners) or a Ni-based barrier such as NiMoP. These materials have been shown to improve EM performance. Preferably, the supplemental barrier layer is deposited by means of an electroless technique, optionally with chemical grafting although other methods of depositing the supplemental barrier layer will be apparent to a person skilled in the art chemical, on the surfaces initially carrying the outer barrier layer irrespective of whether or not that barrier layer has been partially or completely degraded as a result of the etching process. As a consequence, a completely attacked outer barrier layer can be advantageously supplemented or replaced by a supplemental barrier layer of another type, which supplemental barrier layer can also play the role of a diffusion barrier. The interconnects may be copper, and the outer barrier material may, for example, be

Tantalum or Tantalum nitride (Ta or TaN), TiN or Ruthenium.

As a result of the present invention, it is possible to completely cap the copper surface with a barrier layer of a material having excellent adhesion properties to copper as well as outstanding reliability performances (i.e. electromigration performance and barrier efficiency) after air gap formation has taken place using, for example, non-conformal chemical vapor deposition (CVD), for example, and all of these advantages are achieved whilst still enabling good quality trenches, having an optimized aspect ratio, to be formed between the metal lines in order to ensure that high performance air gaps can be fabricated so as to ensure improved signal propagation performances. These and other aspects of the present invention will be apparent from, and elucidated with reference to, the embodiments described herein.

BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which:

Figures Ia and Ib are schematic cross-sectional views illustrating a first method of air gap formation according to the prior art;

Figures 2a - 2c are schematic cross-sectional views illustrating a second method of air gap formation according to the prior art;

Figures 3a - 3d are schematic cross-sectional views illustrating a third method of air gap formation according to the prior art;

Figures 4a and 4b are schematic cross-sectional views illustrating a first method of air gap formation according to an exemplary embodiment of the present invention; - Figure 5a and 5b are schematic cross-sectional views illustrating a second method of air gap formation according to an exemplary embodiment of the present invention; and

Figure 6 is a schematic cross-sectional view illustrating a third method of air gap formation according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The copper damascene process is widely established and has brought higher performance to semiconductor devices. Copper has replaced aluminium because of its lower resistivity and higher reliability, but it still suffers from electromigration (EM) and stress migration (SM) reliability issues as geometries continue to shrink and current densities increase.

As explained above, in the copper damascene process, the copper line is encapsulated on the sides and bottom by barrier metal, and in some cases on top by a barrier/etch stop (passivating) material.

Thus, the present invention effectively provides an integration scheme for air gap formation, which permits Cu line integrity repair. This process is carried out after trench formation between adjacent interconnects has been performed using any technique (including RIE, wet etching using for example HF, or both) which can lead to the partial or complete removal of the dielectric layer between adjacent interconnects and induce the potential issue explained in detail above with regard to metal barrier integrity. This is true in all cases, including where the metal barrier actually remains intact (because the provision of the supplemental barrier layer may enhance the barrier efficiency or EM performance, for example), is partially attacked or completely removed during one of the process steps employed for air gap formation.

Thus, for example, referring back to the method described with reference to Figures 3a - 3d of the drawings, in a method according to an exemplary embodiment of the present invention, referring to Figures 4a and 4b of the drawings, after the trenches 7 have been etched between adjacent interconnects 3, whereby a first barrier layer 4 (e.g. Ta, TaN, TiN or Ruthenium) may or may not have been partially attacked or completely removed, each interconnect 3 is encapsulated on the sides and bottom by a second barrier layer 15, after which process, the air gaps 13 are formed by non-conformal chemical vapor deposition (CVD) of a second dielectric material 16. It can be seen, in this case, that the second barrier layer is selectively deposited on the interconnect 3 such that it does not cover the mask layer 11.

In fact, in any event, the process of depositing the second barrier layer 15 is required to be selective as it is only to be deposited in the portions of the trench 7 corresponding to the copper lines 3 (and/or on the copper line surface, in some cases depending on the integration scheme previously used and/or the deposition selectivity between the metals at the upper surface and at the edges of the copper lines 3). Since the technique must be selective between metal areas and dielectric areas, in order to prevent short circuits, a preferred technique for selective deposition of the second barrier layer 15 comprises electroless deposition of metal layers using chemical grafting on the first metal barrier 4. As an example, it has been illustrated that Cobalt (Co) - based self-aligned barriers (e.g. Cobalt Tungsten Phosphide (CoWP) or Cobalt Tungsten Bromide (CoWB) metal liners) deposited on copper lines show an improvement in terms of EM performance. However, other suitable metallic barrier materials and deposition processes will be apparent to a person skilled in the art and the present invention is not intended to be limited in this regard. As a consequence, a completely attacked TaN barrier, for example, could be advantageously replaced by such barrier types, while at the same time, this type of barrier can also provide a diffusion barrier. In any event, electroless CoWP or CoWB deposition is self-aligned to copper and forms a smooth conformal film. This process will be known to a person skilled in the art and is described in, for example, the EJ. O'Sullivan et al reference referred to above, and will not be discussed in any further detail herein. As mentioned above, the method of the present invention is equally applicable to capped or uncapped metal interconnect lines. Referring to Figure 5a of the drawings, there is illustrated schematically (i) an uncapped metal line 3, and (ii), (iii) first and second capped metal lines 3. Referring to Figure 5b of the drawings, it is illustrated that in the case of (i) the uncapped line, the second barrier layer 15 is deposited on the sides and top of the interconnect 3; in the case of (ii) the first capped line, the second barrier layer 15 is deposited only on the sides of the interconnect 3, and in the case of (iii) the second capped line, the second barrier layer 15 is deposited on the sides and top of the interconnect 3.

Referring to Figure 6 of the drawings, even in the case where the mask 6 is misaligned (as in the example described with reference to Figures 2a - 2c of the drawings), the provision of the second barrier layer 15 not only supplements or replaces the degraded first barrier layer 4, but also protects the exposed copper of the interconnect 3 caused by the misalignment of the mask 6.

Yet in another integration scheme, a multi- level interconnect stack may be built in a dielectric such as pure USG, following which the sacrificial USG layers are removed by means of a specific wet chemical etching treatment, using for example, a diluted HF solution. This process may result in degradation of the interconnect barrier due to exposure thereof to HF. Thus, a method according to another exemplary embodiment of the present invention includes the subsequent step of selectively depositing a metallic barrier layer on the sidewalls (and optionally ever on the tope and bottom) of the interconnect lines by means of an electroless deposition technique, so as to effect interconnect line integrity repair.

In all cases, the most important issue is that of the selectivity of the electroless deposition technique, in the sense that no deposition should occur on the dielectric in which the interconnects are embedded, otherwise electrical shorts will form in between the metal interconnects. In a conventional electroless deposition technique, a CoWP barrier layer is required to be deposited (only) on top of the copper interconnects, and the process has thus been developed such that CoWP is only deposited on Cu, as will be known to a person skilled in the art. In the case of the present invention, the electroless deposition process may 'see' any remaining metallic barrier layer as well as exposed Cu. As will be known to a person skilled in the art, the electroless deposition of a material, such as NiMoP, for example, is dependent on the chemistry employed to initiate the deposition process and/or to define the final composition of the layer. It is these factors that can also be used to define the selectivity of the process (i.e. metal versus dielectric or in-between difference metallic compounds). Thus, in the case of the present invention, the deposition process can be 'tuned' such that deposition takes place only on Cu or on both Cu and any remaining metallic barrier, perhaps with different deposition rates. In fact, the deposition rate and conformity of the process may be different on Cu relative to that on TaN/Ta and, as a consequence, the thickness of the electroless barrier deposited on Cu may be different to that deposited on any remaining barrier material. However, this does not effect unduly the usefulness of providing the additional metallic barrier on the TaN/Ta barrier (whether untouched or partially degraded).

In a full integration scheme in all cases, the next integration step can consist in a PECVD treatment leading to air-gap formation in-between the metal lines including (or not) a dielectric liner deposition, followed by a standard dual-damascene integration scheme. The process can also partially be implemented as a repair process after some sacrificial dielectric has been removed on a multi- level interconnect stack in the case when the metal barrier deposited prior to copper filling needs to be repair or enforced.

As an alternative, in order to completely control air gap trench formation, it is proposed that an ultra-thin liner may be introduced within the interconnect stack. Already known as an Etch Stop Layer assisting dual damascene integration scheme, such a liner would assist trench formation, and with specific selectivity to an etching process for instance, will allow trench formation control. In association with an HF removal technique, it will enable dielectric removal below the trenches to be avoided, thus ensuring the mechanical stability of the lines and help in defining the trenches geometry.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice- versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of manufacturing an integrated circuit, comprising: forming a plurality of conductive interconnects (3) on an integrated circuit die, embedding said plurality of interconnects (3) in one or more layers of dielectric material (1), etching said one or more layers of dielectric material (1) so as to form a trench (7) between adjacent interconnects (3), and subsequently selectively depositing a supplemental barrier layer (15) on at least one of the exposed surfaces of said interconnects (3).

2. A method according to claim 1, wherein said interconnects (3) are embedded in a first layer of dielectric material (1), said first layer of dielectric material (1) is etched so as to form a trench (7) between adjacent interconnects (3), and the supplemental barrier layer

(15) is subsequently deposited on at least one of the exposed surfaces of said interconnects (3), the method further comprising: subsequently non-conformal depositing a second layer (16) of dielectric material over said interconnects (3) and in said trenches (7) so as to form air gaps (13) in said second layer

(16) of dielectric material corresponding to the location of said trenches (7).

3. A method according to claim 2, wherein prior to etching the trenches (7), at least the surfaces of the interconnects (3) embedded within the first layer of dielectric material (1) and adjacent thereto, are provided with an outer barrier layer (4), and after etching of the trenches (7), at least the surfaces embedded within the first layer of dielectric material and adjacent thereto are provided with the supplemental barrier layer (15).

4. A method according to claim 1, wherein said supplemental barrier layer (15) comprises a conductive material.

5. A method according to claim 4, wherein said supplemental conductive barrier layer (15) is selectively deposited on said at least one of said exposed surfaces of said interconnects (3) by means of an electroless deposition process.

6. A method according to claim 4, wherein said supplemental conductive barrier layer (15) comprises a self-aligned Co-based or Ni-based barrier.

7. A method according to claim 1, wherein said interconnects (3) comprise copper.

8. A method according to claim 1, wherein said outer barrier material (4) comprises Tantalum or Tantalum nitride or Ruthenium.

9. An integrated circuit comprising a plurality of interconnects (3) formed by a method according to claim 1.

10. An integrated circuit according to claim 9, wherein air gaps (13) formed by a method according to claim 2, are provided between adjacent interconnects (3).

11. An integrated circuit according to claim 10, comprising a multi- level interconnect structure, wherein each interconnect level is sequentially formed with the respective air gaps (13) therein.

12. An integrated circuit according to claim 9, comprising a multi- level interconnect structure, wherein a plurality of interconnect levels are formed in respective dielectric layers and all of said dielectric layers are subsequently etched to form respective trenches between adjacent interconnection (3) in each interconnect level.