WO2006058262A2 - Semiconductor integrated injection logic device and method - Google Patents

Abstract

This invention relates to a semiconductor device consisting of one or more logic gates, resistors and high voltage devices fabricated from silicon carbide or other related materials and to methods for fabricating the same. The logic gates are formed using integrated injection logic (IIL) structure, in which a single logic cell includes a constant current source transistor (I) and a multi-collector switch transistor (II) formed on a common silicon carbide substrate (10).

Description

SEMICONDUCTOR INTEGRATED INJECTION LOGIC DEVICE AND METHOD

This application claims priority from U.S. provisional patent application serial no. 60/630,456, entitled "Semiconductor Integrated Logic Gate Silicon Carbide Device," filed on November 23, 2004. TECHNICAL FIELD

This invention relates to semiconductor devices and methods to fabricate same, and in particular to such devices consisting of logic gates integrated with high voltage devices.

BACKGROUND ART Silicon carbide is known as a wide band-gap semiconductor material with highly desirable properties. These include a high critical electrical field -{about 2 x 10⁶ V/cm), a high thermal conductivity, a high electron mobility and a large band gap leading to capability for continuous operation at high temperature. Silicon carbide crystallizes in over 150 different polytypes, or crystal structures, including common types designated as 3C, 4H and 6H, where "C" stands for "cubic" and "H" for "hexagonal". At the present time, 4H polytype is attractive for power devices due to its higher electron mobility. The 6H polytype is also enjoying wide usage in electronics applications. Recent advances in -crystal growth methods have allowed for larger (i.e., 75 mm diameter) substrates, making wafer fabrication more amenable to automation. At the same time, capabilities for epitaxial growth methods have improved and related support equipment has become more available.

Together, the characteristics of silicon carbide enable performance of high voltage devices that are dramatically superior to silicon, with power losses as much as 200 times less than for a comparable silicon device. In addition, operating temperatures may theoretically approach 600° centigrade. Fabrication of semiconductor devices in silicon carbide is, however, very difficult. One reason for this difficulty is the fact that implantation to -create an electrical junction must be done at elevated temperatures in order to activate dopants. In addition, such ion implanted electrical junctions suffer from difficulties with crystal lattice imperfections and associated leakage currents. Such high-temperature ion implantation techniques are described, for example, in U.S. Pat. Nos. 4,945,394 and 5,087,576. Yet, in addition to doping by epitaxy, ion implantation is required since dopant diffusion rates are too small to allow for thermal diffusion in silicon carbide. It is therefore difficult to fabricate bipolar transistors in silicon carbide materials. The other choice of transistor technology is MOSFET, widely employed in silicon. Silicon carbide, however, exhibits a high surface state charge and low surface inversion mobility, making it also difficult to fabricate MOSFET transistors. In addition, it is well known that the threshold voltage of MOSFET devices changes continuously with temperature, limiting the range of operating temperatures that a given design can accommodate. With the possible exception of static induction transistor (SIC) devices, which are in the class of through-the- substrate transistors, no versatile transistor technology has been developed in silicon carbide to date. The SIC transistor is, however, not readily amenable to integration, since it depends on current flowing from a first surface of the substrate to a second, opposing surface. As such, fabrication of integrated circuits based on planar technology cannot be-completed using state-of-the-art technology.

The fabrication technology for silicon carbide transistors is fundamentally limited by the poor quality of ion implanted junctions. Palmour, et al. in U.S. Patent No. 4,945,394 disclose a bipolar junction transistor formed in silicon carbide wherein the base and emitter are formed as wells using high temperature ion implantation. In general, such double-junction bipolar transistors have not found common usage since the junctions so formed are still leaky, and associated manufacturing yields are low. With current technology constraints, it is important when forming logic gates to minimize dependence on ion implanted junctions. U.S. Patent No. 6,303,058 to Alok discloses methods to make integrated circuits in silicon carbide by application of amorphization techniques to convert a portion of the silicon carbide to silicon. Therefore, islands of silicon devices may be fabricated upon a silicon carbide substrate. As is well known in the art, such devices may be expected to contain significant crystalline defects, limiting this approach to fabrication of unipolar devices where the amor-phisized region does not intersect with a p-n junction. Due to the change in threshold voltage with temperature, such unipolar devices may have limited operability above about 150° - 200° centigrade. There is increased interest in providing all-electronics systems that can withstand continuous operation at elevated temperatures of 300° - 600⁰C. This interest drives investigation of high-voltage, high-current switching power diodes and transistors that dissipate a good deal of heat. Current solid state devices fabricated in silicon require heat sinks that are expensive and massive. In some cases it has been estimated that by eliminating heat sinks, both system weight and system volume would be decreased by one to two orders of magnitude. In space applications, considerations for weight and volume dominate over^ost. In other emerging applications, attempts are being made to eliminate hydraulic or other control systems in favor of all-electronic systems. This is impractical with the limitations of silicon materials. Semiconductor devices fabricated in a new material are required. In order to deliver on the vision of an all-electronic system, control systems in addition to high-voltage, high-current switching devices are required to operate at increasingly higher temperatures. Overall, a generalized integrated circuit requires provision for logic gates operating typically at 5 volts or less, for control amplifiers operating typically at 5 - 30 volts, and for high-voltage, high-current devices operating at perhaps 30 - 3000 volts. To date, no single integrated circuit device has been capable of spanning the range of required voltages. Silicon carbide in particular and wide band-gap materials in general holds the promise of providing the necessary flexibility.

The vision of all-electronic systems serviced by silicon carbide semiconductor devices is currently limited by the lack of high temperature logic gates. Logic gates typically require transistors, and the difficulties in silicon carbide transistor fabrication have already been discussed. Silicon high- temperature alternatives require exotic fabrication technology such as the silicon- on-insulator (SOI) technique, and these technologies are fundamentally limited in operation to at most 300° C. Therefore, a demand exists for logic gates fabricated in silicon carbide.

Finally, since silicon carbide exhibits relatively short minority -carrier lifetimes of 40 nsec - 3 sec, it is important to tightly control the physical dimensions of devices formulated in this material. In particular, base regions of bipolar transistors must be less than 1.0 microns in thickness in order to have alphas (base transport factor) approaching 1.0. The inventor hereof has recognized that control can be developed by applying a combination of silicon carbide p-n junctions produced by epitaxial growth and adaptation of integrated injection logic (ML) circuitry previously developed for silicon. ML as previously implemented in silicon will not work in silicon carbide without modification. The NL cell can be incorporated with high-density fabrication by the same processing as that of mesa-isolated bipolar transistors. The HL circuit structure was widely used as logic gates in silicon technology prior to the widespread adoption of CMOS (complementary MOS insulating gate field-effect transistor) as the standardized building block for integrated circuits. CMOS has since become the dominant silicon technology due to advantages of high frequency capability, low power consumption and low cost. However, HL logic gates may be formed with high layout density and relatively few process steps, making the technology interesting for silicon carbide and other wide band gap applications. Due to the various technology barriers, there has been no publication to date of attempts to adapt HL to silicon carbide. For instance, a typical HL implementation in silicon applies a lateral PNP as a current source. There is no straightforward way to duplicate this in silicon carbide.

In addition, the HL cell structure makes it possible to construct a linear circuit combining both logic gates and bipolar transistors of wide-ranging design and functionality. The inventor hereof has recognized that such a circuit is highly desirable as a control element to be used in conjunction with high-voltage devices.

An HL cell comprises a NAND logic gate. In a typical implementation, multiple cells are connected in a wired-AND configuration. As such, if a single one of the multiple wires that are connected is held at a low logic state, then all wires will be pulled low. Therefore, the logic gate that pulls the wire low must -be able to sink sufficient collector current to maintain the several wires at a low logic state. A semiconductor device meeting all of the requirements set forth above is highly desirable. DISCLOSURE OF INVENTION

The present invention relates to a semiconductor device applying an IIL cell structure along with provision for high voltage devices. The HL logic cell comprises a common semiconductor substrate, a constant current source transistor and a switch transistor. Both of the constant current source transistor, the switch transistor and the high voltage blocking device are formed on the common semiconductor substrate. Conveniently, the emitters of various switch transistors and the cathode of high voltage devices are connected in common to the substrate.

A logic gate applying the HL approach and integrated with high-voltage devices overcomes the disadvantages and obstacles involved in silicon carbide by minimizing use of ion implanted metallurgical p-n junctions, which are inherently leaky; acting to reduce costs through simplification of processing; applying a low-gain vertical PNP transistor; and making use of DRIE trench and refill transistor isolation methodology. The method of the present invention may be implemented using as a starting structure a silicon carbide substrate on which there is deposited one or more epitaxial layers of silicon carbide. Epitaxial layers of silicon carbide may be applied as described in U.S. Pat. Nos. 5,011 ,549 and 4,912,064 to Kong et al., the disclosures of which are incorporated herein by reference.

In addition, a preferred embodiment of the present invention makes use of bipolar junction transistors. A bipolar junction transistor is an active, three- terminal semiconductor device comprising two p-n junctions in close proximity. Bipolar junction transistors may be broadly characterized as NPN or PNP depending on the conductivity types of their respective emitters, bases and collectors.

While the present invention relates primarily to silicon carbide, it is understood that the same approach will be useful in developing integrated circuits in other wide band-gap semiconductors such as the family of Ill-Nitride materials (Gallium Nitride in particular), and diamond, for example.

Accordingly, an object of the present invention is to provide novel semiconductor devices comprised of multiple logic gates and one or more high voltage devices fabricated in silicon carbide. This allows for continuous high temperature service and capability.

Another object of this invention is to provide an NL gate fabricated in silicon carbide. Another object of this invention is to provide multiple logic gates fabricated in silicon carbide.

Another object of this invention is to provide a compact bipolar vertical PNP transistor fabricated in silicon carbide. Another object of this invention is to provide an HL gate fabricated in silicon carbide and using a vertical PNP transistor as a current source.

Another object of this invention is to provide a high-voltage device fabricated in silicon carbide.

Another object of this invention is to provide one or more high voltage devices and one or more ML gates fabricated in silicon carbide.

Another object of this invention is to provide resistors fabricated in silicon carbide.

Another object of this invention is to provide logic gates, resistors and capacitors fabricated in silicon carbide. Another object of this invention is to provide electrical isolation between adjacent transistors fabricated on a silicon carbide substrate.

It is a further object of the present invention to enable fabrication of a general integrated circuit in silicon carbide, making use of the capabilities of bipolar transistors. A still further object of the invention is to minimize the number of fabrication steps required to fabricate a logic gate in silicon carbide.

A still further object of the invention is to fabricate silicon carbide resistors integrated with logic gates. Such silicon carbide resistors are designed to exhibit a temperature coefficient of resistance that matches that of other devices co- fabricated in a common substrate.

A still further object of the invention is to fabricate thin-film resistors deposited as thin-film material overlying an oxide layer. Such thin-film resistors are specially fabricated to exhibit near-zero temperature coefficient of resistance.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic illustration of an integrated injection logic gate.

FIG 2A is a plan view of a prior art ML logic gate. Fig. 2B is a side cross-sectional view a prior art HL logic gate. FIG. 3 is a side cross-sectional view of a starting substrate with grown epitaxial layers according to a preferred embodiment of the present invention.

FIG. 4 is a side cross-sectional view of the starting substrate of FIG. 3 following steps to pattern and mesa etch P+ regions, to pattern and mesa N- islands, and to pattern and ion implant N+ contact regions as well as N+ collar regions according to a preferred embodiment of the present invention.

FIG. 5 is a side cross-sectional view of the substrate shown in FIG. 4 following subsequent dielectric deposition, patterning and etching to open contact regions according to a preferred embodiment of the present invention, FIG. 6 is a side cross-sectional view of the substrate shown in FIG. 5 following subsequent metal deposition and patterning over each of the contact regions according to a preferred embodiment of the present invention.

FIG. 7 is a plan layout of a single HL gate according to a preferred embodiment of the present invention. FIG. 8 is a plan layout of two side-by-side ML gates according to a preferred embodiment of the present invention.

FIG. 9 is a side cross-sectional view of a second preferred embodiment of the present invention including extended metal between the base of the vertical PNP transistor (second n-type layer) and the first n-type layer beneath, illustrating the variation in pattern and etch of dielectric to open contact regions.

FIG. 10 is a side cross-sectional view of a third embodiment of the present invention with an optional P-type ion implantation region over the base contact of the switch transistor, designed to improve ohmic contact.

FIG. 11 is a side cross-sectional view of a fourth embodiment of the present invention with Schottky collector contacts.

FIG. 12 is a side cross-sectional view of a fifth embodiment of the present invention with trench-refill-planarization method of isolation.

FIG. 13A is a plan view of a resistor formed of silicon carbide according to a preferred embodiment of the present invention. FIG. 13B is a side .cross-sectional view of the resistor of FIG. 13A.

FIG. 14A is a plan view of a resistor formed on top of silicon carbide according to a preferred embodiment of the present invention.

FIG. 14B is a side •cross-sectional view of the resistor of FIG 14A. BEST MODE(S) FOR CARRYING OUT THE INVENTION AND INDUSTRIAL

APPLICABILITY

While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts which can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. When referring to the drawings, like reference numbers are used for like parts throughout the various views. Directional references such as, top, bottom, upper, lower, left, right, used in the discussion of the drawings are intended for convenient reference to the drawings themselves as laid out on the page, and are not intended to limit the orientation of the invention unless specifically indicated. The drawings are not to scale and some features have been exaggerated in order to show particular aspects of the invention.

An overview of certain of the preferred embodiments of the present invention may now be provided. A first embodiment of the present invention involves the formation of a lightly-doped first n-type silicon carbide epitaxial layer on top of a heavily-doped n-type substrate, followed by a heavily doped second n-type epitaxial layer. The thickness of the lightly-doped first n-type epitaxial layer will be designed in accordance with the requirements for voltage standoff of a high voltage device. For example, the thickness of the lightly-doped first n-type epitaxial layer may typically range from 5 to 50 microns. The heavily doped second n-type epitaxial layer will be patterned and etched to form an island of heavily doped material. In the finished construction, these islands will form n⁺ buried layers. Subsequently, a lightly doped third n-type epitaxial layer may optionally be grown, followed by a moderately-doped first p-type epitaxial layer. A lightly doped fourth n-type layer is grown over the p-type layer. A heavily doped second p-type epitaxial capping layer may be grown over the lightly-doped fourth n-type layer.

To understand the device requirements, three separate regions 1, 11 and III must be considered. These regions relate to the fabrication of, respectively, the vertical PNP current source, the multicollector vertical NPN switching device, and a high-voltage device. In a preferred embodiment, transistor isolation is completed as an n-type ion implant region extending downwards from the lightly- doped fourth n-type layer through the first p-type layer and into the lightly-doped third n-type layer. The function of transistor isolation is to increase the upwards current gain of the NPN switch transistor. The n-type ion implant region does not truly electrically isolate adjacent logic gates. Rather, the interposed ion implanted region acts to decrease the current gain of parasitic lateral devices, and to improve the emitter efficiency of the switch transistor. Since all emitters of switch transistors are in common with the substrate, true electrical isolation is not required. In a second embodiment, however, transistor oxide isolation is completed by the trench, refill and planarization (TRP) method. Although this technique is more costly, the advantages of the TRP method of electrical isolation are to reduce layout area required for a logic gate and to enable increased operating frequency by minimizing parasitic capacitance. It should be understood that various isolation mechanisms have been envisioned within the scope of the invention, also including mesa etch with passivation.

In region I, that of the vertical PNP current source, the heavily-doped second p-type epitaxial layer forms the emitter of the vertical PNP, while the base of the vertical PNP is formed by the lightly-doped fourth n-type epitaxial layer. A patterned mesa etch is performed first removing the heavily doped second p-type surface layer from all locations except for the emitter region and optionally other regions outside of the logic gates. A second patterned mesa etch is performed to expose the underlying moderately-doped first p-type epitaxial layer in designed regions. Optionally a third patterned mesa etch is performed to expose the underlying lightly-doped third n-type epitaxial layer in designed regions. Optionally, ion implantation, activation and diffusion of dopant atoms is completed into exposed base regions of the vertical PNP transistor in order to increase the surface concentration and prepare for good ohmic contact. Optionally, ion implantation and activation is completed into the collector region and other n-type regions to prepare for good ohmic contact. A quality ohmic contact typically comprises a tunneling Schottky diode contact. The chosen metal determines the metal-semiconductor barrier height. The doping level in the semiconductor immediately beneath the metal determines the width of the depletion region. A highly doped semiconductor surface beneath the metal will exhibit a depletion width of, for instance, 200 Angstroms or less, which is conducive to carrier tunneling. Ion implantation is a technique for increasing the doping at the semiconductor surface. The usage of ion implantation to improve ohmic contact is beneficial, but the scope of the invention is not limited by the application of the ion implantation step.

In region II, that of the multicollector switching transistor, the collectors are formed by first removing the heavily doped second p-type surface layer by photoresist pattern and mesa etch. A photoresist pattern and mesa etch step follow in order to electrically isolate each collector island. Ion implantation, activation and diffusion of high-dose n-type dopant is completed into each separate collector region in order to prepare for good ohmic contact. It should be understood that desirably said ion implantation and activation steps in region Il are exactly the same as those made in region I, such that common masking and ion implantation steps may be used.

In region III, that of the high-voltage device, a number of devices may be constructed. For purposes of illustration, a static induction transistor (SIC) will be considered as one example of a high-voltage device. Typically, a SIC is designed to handle high voltages and high currents (high power). As such, the current path is from the front surface to the back surface. In the absence of a voltage applied to the gate region, a large current will flow through the SIC. With application of a pinch-off voltage to the gate region, current flow is restricted. Typically, the current flow in pinch-off, or OFF state, is one to two orders of magnitude less than that when no gate voltage is applied. The construction of a SIC requires good ohmic contact to both the front-side source and the back-side drain regions. In addition, good ohmic contact is required to a gate region surrounding the top¬ side source region. It should be understood that the present invention is not limited to integration of SIC high-voltage devices, but also includes any of a variety of power-handling devices, such as high-voltage MOSFETs, DMOSFETs, JFETs, Schottky barrier diodes, IGBT, and thyristors. Preferably, heavily doped n-type buried layer islands will underlie regions I and Il by design. For convenience, a single contiguous region of heavily doped n- type buried layer may underlie many HL logic gates.

The fabrication methods outlined above have the advantage of not depending on junctions formed by ion implantation. Ion implantations and in particular p-type ion implantations are difficult to activate in silicon carbide, and electrical p-n junctions formed by ion implantation in silicon carbide material are known to be electrically leaky. In optimization of ion implantations in silicon carbide, it should be understood that desirably the -energy for ion implantation is tailored to minimize residual lattice damage in the region of the p-n junction. In silicon carbide, this requires that the ion implantation be done while holding the wafer at an elevated temperature. Even so, p-n junction leakage currents are present and may vary considerably as the ambient temperature is changed, causing inconsistently in logic gate switching. In the instant application, each ion implantation dopant is preferably of the same type as the region into which it is implanted. For example, n-type dopant phosphorous may be implanted into an n- type region in order to boost the surface concentration and prepare for good ohmic contact. Alternatively, p-type dopant boron may be implanted into a p-type region for the same purpose. Optionally, a passivation treatment step may be performed to minimize the number of dangling bonds intersecting with the exposed top surface and to minimize spurious surface currents. For example, a high temperature anneal in NO₂ is known to have a beneficial effect. Those skilled in the art will recognize a number of possibilities for surface treatment and passivation. Following all mesa etch steps, along with subsequent ion implant, activation and passivation treatment steps, and optional planarization steps, a Schottky metal layer is optionally deposited. Following the Schottky metal layer, a dielectric layer is deposited uniformly over the top surface of the substrate. Applying photolithography and etch techniques, openings are now created in this dielectric over regions where electrical contact to the Schottky metal is desired. Interconnection metal is applied, patterned and etched to produce desired metal interconnect and bonding pads. Optionally, ohmic contact metal may be applied to the bottom surface of the substrate. In a second preferred embodiment, a third mesa etch step is completed in order to expose the moderately-doped first p-type layer. This allows for metal interconnect between the lightly doped third n-type epitaxial layer and the lightly doped fourth n-type epitaxial layer. In a third preferred embodiment, a patterned p-type ion implantation region is formed on the top surface of the p-type epitaxial layer in order to enhance the quality of the ohmic contact to interconnect metal.

In a fourth preferred embodiment, Schottky diodes are formed over the collector regions of the switch transistor. This results in a so-called Schottky collector NPN. Such a device has advantages in some applications due to the reduced voltage swing between logic levels, and the associated increase in operating frequency. Essentially, in this embodiment the n-type ion implantation step is patterned such as to not penetrate over the collector regions. In addition, a Schottky metal is carefully chosen to have the desired barrier height and other properties.

In a fifth preferred embodiment, isolation by trench-refill-planarization (TRP) method is completed prior to mesa etch steps. Preferably, TRP methods will be employed following ion implantation anneals steps in order to avoid excessive stress due to mismatch in thermal expansion coefficients. According to the above embodiments, logic gates are formed in silicon carbide with reliance entirely on epitaxial p-n junctions. It is preferable to planarize the surface of the silicon carbide substrate following formation of transistors, in preparation for electrical interconnection. Multiple levels of interconnect may be freely applied as necessary to complete a complex of integrated circuits including many logic gates or other devices. In addition, layers of interconnection may be interleaved with resistive material in order to complete the requirement for resistors in an electrical circuit. Finally, capacitors based on silicon dioxide or other deposited dielectric material may be readily formed without significantly altering the fabrication approach. The invention may be applied with advantage using other substrate materials substituted for silicon carbide. For example, substrate materials are readily available for H-Vl, MI-V and Ill-Nitride materials such as .Gallium Arsenide, Indium Phosphide and -Gallium Nitride. In particular, Gallium Nitride is another wide band-gap semiconductor material of interest. Both fabrication techniques applied and the devices constructed may be based on alternative semiconductor substrate materials.

Certain of the preferred embodiments of the present invention may now be described in greater detail with reference to the figures forming a part hereof. In FIG. 1 is shown a PNP current source transistor with collector connected to the base of the NPN switch transistor. When the input voltage is high, the NPN transistor is "on" and outputs are pulled low as the transistor goes into saturation. As the outputs are further connected in a circuit, the NPN transistor may be required to sink current to ground. In this case, the PNP transistor is in saturation and provides the base drive current that is required. When the input voltage is low, the NPN transistor is "off' and the output voltages will drift towards the breakdown voltage limit. As the outputs are further connected in a circuit, the output voltages will tend to be limited to a V_BE- In this case, no base drive current is required by the NPN transistor. It is noted that a single ML logic gate acts as an inverter, and may be advantageously employed as such.

In FIG. 2 is shown a plan view of a prior art HL logic gate. An N+ collar is shown surrounding a single logic gate. For convenience, Input and Outputs may be freely interchanged in layout with little effect on functionality. Fig. 2B is a side cross-sectional view a prior art HL logic gate, illustrating the usage of a common p-type diffusion to create both the emitter of a vertical PNP current source transistor and the base of the vertical PNP switch transistor {merged with the collector of the vertical PNP transistor).

As seen in FIG. 3, a starting substrate according to embodiments of the present invention preferably includes an n⁺ mono-crystalline silicon carbide substrate 10 with a front surface 9 and an opposing tack surface 19. Although starting substrate 10 may be formed from any of a number of different silicon carbide polytypes in alternative embodiments, a single crystal 4H alpha-SiC material (Si-face) is preferred. This is due to a combination of high electron mobility and thermal conductivity found in the 4H substrate.

In a preferred embodiment, a first lightly-doped n-type silicon carbide layer 11 is epitaxially formed on a first face of the starting substrate 10. A second heavily doped n-type layer {not shown in Fig. 3) is epitaxially formed on the first n-type silicon carbide layer 11. This heavily doped n-type layer is patterned and etched to form isolated islands 13, exposing the first n-type layer 11 in areas surrounding islands 13. An third n-type silicon carbide layer 14 is epitaxially formed on islands 13 as well as on the surface of surrounding first n-type layer 11. A p-type silicon carbide layer 15 is epitaxially formed in sequence on the n- type silicon carbide layer 14. A fourth n-type silicon carbide layer 16 is epitaxially formed in sequence on p-type silicon carbide layer 15. Finally a second p-type silicon carbide layer 18 is epitaxially formed in sequence on the third n-type silicon carbide layer 16. The first n-type silicon carbide layer 11 may preferably have a thickness of from about 1.0 to about 50 micrometers and is doped to provide a carrier concentration of from about 1 x 10¹⁴ cm^'3 to about 1 x 10¹⁷ cm^"3. The second n- type silicon carbide layer 12 may preferably have a thickness of from about 0.02 to about 0.5 micrometers and is doped to provide a carrier concentration of from about 1 x 10¹⁸ cm^"3 to about 1 x 10²⁰ cm^"3. The third n-type silicon carbide layer 14 may preferably have a thickness of from about 0.1 to about 5.0 micrometers and is doped to provide a carrier concentration of from about 1 x 10¹⁴ cm^'3 to about 1 x 10¹⁷ cm^"3. The first p-type silicon carbide layer 15 may preferably have a thickness of from about 0.05 to about 1.0 micrometers and is doped to provide a carrier concentration of from about 2 x 10¹⁶ cm^"3 to about 1 x 10¹⁸ cm^"3. The fourth n-type silicon carbide layer 16 may preferably have thickness of from about 0.02 to about 0.5 microns and is doped to provide a carrier concentration of from about 1 x 10¹⁴ cm^"3 to about 1 x 10¹⁷-cm^"3. The second p-type silicon carbide layer 18 may preferably have a thickness of from about 0.01 to about 1.0 micrometers and is doped to provide a carrier concentration of from about 5 x 10¹⁸ cm^"3 to about 1 x 10²¹ cm^"3. In determining the thickness of p-type silicon carbide layer 18 and n-type silicon carbide layer 16, it is desirable to balance the need for minimum step height following mesa etching against the requirements for good emitter efficiency on vertical PNP transistor in region I. Therefore, in a preferred embodiment, the thickness of p-type epitaxial layer 18 will be about 0.08 micrometers.

In a preferred target configuration, thicknesses and doping levels may -be summarized as provided in the following table:

Referring now to FIG. 4, embodiments of a vertical PNP current source transistor are illustrated in region I and a multi-collector switch transistor in region II. Each of the illustrated devices are generally replicated in a unit cell. For ease of illustration, a single unit cell of each type will be described, however, it will be appreciated that additional unit cells may be incorporated into a design layout in order to implement a fully functional integrated circuit, while still benefiting from the advantages of the present invention. As illustrated in FIG. 4, p⁺ contact areas 22 may be formed by pattern and etch accomplishing removal of much of p-type silicon carbide layer 18 to provide access to underlying n-type silicon carbide layer 16. Etching techniques may be accomplished by any known applicable method, including reactive ion etch (RIE), masking with selective oxidation and removal of oxide, or wet electrochemical etching. The p⁺ contact areas 22 are preserved in areas where it is desired to form vertical PNP emitters. In a first embodiment, multiple n⁺ silicon -carbide contact areas 20, 23, 24, 25 and 27 are formed by patterning and ion implanting an n-type dopant such as phosphorous or nitrogen into n-type silicon >carbide layer 16. The ion implantation dose and energy is preferably tailored to allow for maximum surface concentration when the implant layer is fully activated. This in turn leads to relatively low resistance ohmic contacts.

In FIG. 4, region I illustrates an example of a vertical PNP unit cell; region Il illustrates an example of a multi-collector vertical NPN switching transistor unit cell; region III illustrates an example of a high-voltage device. It should be understood that the widths of each of these regions will preferably -be designed to meet the requirements of each separate device. In FIG. 4 region II, the n⁺ silicon carbide contact areas 23, 24 and 25 are provided by patterning and ion implanting an n-type dopant such as phosphorus or nitrogen into the n-type silicon carbide layer 16. In a final vertical NPN transistor, n⁺ silicon carbide contact areas 23, 24 and 25 in conjunction with islands formed by n-type silicon carbide layer 16 will serve as multiple collectors, p-type silicon carbide layer 14 will serve as the common base, and n-type silicon carbide layers 11 and 14 in conjunction with n-type silicon carbide islands 13 and n-type silicon carbide substrate 10 will collectively serve as the emitter. Notably, each metallurgical p-n junction is formed by epitaxial layers. The critical thickness and doping levels of the vertical NPN transistor base region are controlled by epitaxial growth, a highly controlled process. In addition, the overall collector series resistance of vertical NPN transistor is minimized by adjusting dopant concentrations and layer thicknesses appropriately.

In FIG. 4 region III, p-type silicon carbide layers 15 will serve as a gate for a SIC transistor, collar region 26 along with and contact area 27 serves as a source for a SIC transistor, and n-type silicon carbide layers 11 and 14 in conjunction with n-type silicon carbide substrate 10 will collectively serve as the emitter. In operation, a sufficiently large negative voltage applied to p-type layer 15 will result in pinch-off of the current flowing from source to drain. In a preferred embodiment, n⁺ silicon carbide contact areas 20 and n⁺ silicon carbide contact areas 23, 24, 25 and 27 are identical in dopant profiles, allowing for common fabrication steps, with resultant minimization of costs and complexity.

Optionally, collar regions 26 may be formed by an additional patterning and ion implantation step. The ion implantation of dopants phosphorous or nitrogen is adjusted to ensure that the n-type implanted region extends through p- type silicon carbide layer 15 and into n-type silicon carbide layer 14. For example, for an ion implant energy of 200 kEV the range of the implant is estimated to be 0.2 microns, with a range straggle of about 0.05 microns. Therefore, a reasonably high dopant concentration can be expected at about 0.3 microns below the surface.

Following patterning and ion implanting of regions 20, 23, 24, 25, 26 and 27, it is necessary to activate the ion implants. This is preferably accomplished by exposing the silicon carbide wafer to a high temperature anneal ranging from about 900° C to about 1600° C for several minutes. In a preferred embodiment, the temperature will not exceed about 1300° degree C. For example, if nitrogen is utilized as the n-type dopant, an anneal at about 1300° C for about 200 minutes may be utilized. If phosphorous is utilized as the n-type dopant, an anneal at about 1200° C for about 200 minutes may be utilized. Optionally, a cap layer may be applied to the top surface of the silicon carbide wafer prior to anneal, and removed following anneal.

Referring now to FIG. 5, dielectric layer 30 is formed across the top surface of silicon carbide substrate 10, preferably using the PECVD process. Dielectric layer 30 preferably has a thickness of between about 0.05 micrometers and 1.0 micrometers, and most preferably has a thickness of 0.15 - 0.5 micrometers. In a preferred embodiment, the material of dielectric layer 30 will be PECVD deposited silicon dioxide. Alternatively, dielectric layer 30 may be deposited by thermal oxidation of silicon carbide at an elevated temperature, or may be of deposited silicon nitride material. Many alternative dielectric materials as are known in the art will serve the intended purpose. Dielectric layer 30 may be patterned and etched to remove portions, forming contact area 32. €tch techniques may be, for example, wet chemical etch such as BOE, dry plasma or reactive ion etch.

Having described the fabrication of the basic structure of the various devices, formation of ohmic contacts, interconnection metal and passivation layers will now be described. As seen in FIG.6, ohmic contact metal 40, 41 , 42, 43, 44, 46 and 48 may be deposited, patterned and etched to form a series of connections to the contact area 32. In a preferred embodiment, ohrnic contact metal 40, 41 , 42, 43, 44, 46 and 48 may be formed of nickel or nickel alloys. Alternatively suitable ohmic contact materials include, but are not limited to, titanium alloy, platinum and aluminum. Yet other alternative ohmic -contact materials include Schottky metals such as cobalt suicide, platinum suicide, tantalum suicide or other known Schottky metals that may be applied, assuming that surface dopant concentrations are sufficiently high in each region to allow for resistive ohmic contact of metal 40, 41 , 42, 43, 44, 46 and 48 to each contact area 32. Following pattern and etch of ohmiαcontact metal 40, 41, 42, 43, 44, 46 W

18

and 48, a high temperature anneal step may be required. For example, anneal may be performed at temperature range from about 500° C to about 1100° C for several minutes so as to sinter the metal to the semiconductor and penetrate oxides or other contaminants in the contact areas. In a preferred embodiment, the temperature will not exceed about 1050° C. It is important to minimize temperature excursions due to the stress that may accumulate between silicon carbide and various components of the construction.

As seen in FIG. 6, expanded metal runner 49 may be deposited, patterned and etched to connect interconnect and bond pads as required. In a preferred embodiment, expanded metal runner 49 comprises an adhesion layer, preferably of TiW followed by a conductive layer, preferably Gold. The adhesion layer portion of expanded metal runner 49 preferably has a thickness of between about 0.01 micrometers and 0.5 micrometers, and most preferably has a thickness of 0.10 - 0.15 micrometers. Conductive layer portion of expanded metal runner 42 preferably has a thickness of between about 0.1 micrometers and 2.0 micrometers, and most preferably has a thickness of 0.8 - 1.2 micrometers. It should be understood that expanded metal runner 49 comprises a single example of the first level of interconnection between various circuit nodes, and that expanded metal runner 49 may be generally used as an interconnection metal.

An optional passivation layer of a deposited silicon nitride and/or other passivating material may be applied. Such a passivation layer may typically have a thickness of from about 0.01 micrometer to about 1 micrometer. In the event that the optional passivation layer is applied, a follow-on patterned and atch step will be required to open regions required for circuit bonding. As shown in FIG. 6, ohmic contact layer 45 may optionally be applied to the back surface of the wafer.

Referring now to FIG. 7, a physical layout of a logic gate 50 is illustrated. Isolated regions of n-type silicon carbide layer 16 form the base of the vertical PNP as well as the collectors of the multi-collector vertical NPN transistors. The n⁺ silicon carbide contact layers 22, 23, 24 and 25 are shown, with ohmic contact metal 46 overlaying each of the contact areas. Ohmic contact metal 44 forms contacts to exposed p-type silicon carbide layer 1θ. Optionally, contact layer 48 is placed over collar region 26 to make ohmic contact. Injection rail 40 is connected W 2

19

through a resistor (not shown) and hence to a voltage supply. Expanded metal 49 electrically connects injection rail 40 to other points. For example, in FIG. 8 is shown two logic gates 50 which are conveniently supplied by a single injection rail 40, with voltage distributed by expanded metal 49. Of course, it should be understood that many differing physical layouts may be made in applying the present invention, and the constructions illustrated in FIG. 7 and 8 are not intended to limit the possible variations.

FIG. 9 illustrates a variation in which an additional pattern and mesa etch is included in order to penetrate p-type silicon carbide layer 14 and to create isolation regions 60. Following dielectric deposition as previously discussed, openings 62 are obtained by pattern and etch methods. Metal 66 is applied to form both Schottky and ohmic contacts as needed.

FIG. 10 illustrates a variation in which implanted region 70 is formed beneath the base contact of the vertical NPN switch transistor. In this option, ohmic contact to base layer p-type silicon carbide layer 14 is improved. Implanted region 70 may optionally be incorporated into construction to improve ohmic contact to gate regions 72 of the high-voltage device.

FIG. 11 illustrates yet another variation in which n⁺ silicon carbide contact layers are omitted in the collector areas of the region Il multi-collector switch transistor. In this case, a Schottky contact will be created between Schottky metal 80 and the underlying n^" silicon carbide layer 16. The resultant transistor is known as a Schottky transistor. In many -cases, the-effect is desirable, since the voltage swing between saturation and cutoff is reduced, in turn resulting in higher frequency operation. Of course, simplification of fabrication may also be a desirable result.

Referring to FIG. 12, the second preferred method for electrical isolation of the various unit cells is illustrated, which comprises forming trench 90 in the silicon carbide layers, the trench 90 having a bottom wall and opposing side walls. Preferably, the width of trench 90 ranges from about 0.5 micrometers to about 5.0 micrometers, and more preferably will be about 2.0 micrometers.

Patterning and etching techniques are applied in forming trench 90. For example, Deep Reactive Ion Etch (DRIE) techniques, as known in the art, may be applied to anisotropically etch trench 90. Typical etchant gases for DRIE include nitrogen trifluoride (NF3) and sulfur hexafluoride (SF₆), among others. Notably, an n⁺ silicon carbide channel region 96 is included surrounding each trench 90. The purpose of such n⁺ silicon carbide channel region 96 surrounding each trench 90 is to prevent uncontrolled surface leakage currents from flowing along the edges of trenches 90.

Following the etching of trench 90, an oxide spacer layer 92 having a predetermined thickness is formed on the top surface, including the bottom wall and side walls of trenches 30. The oxide spacer layer 92 may be preferably deposited by CVD or PECVD techniques. Preferably, oxide spacer layer 92 may have a thickness of from about 0.01 to about 0.5 micrometers, and more preferably a thickness of about 0.15 micrometers.

Although oxide spacer layer 92 is described in reference to the preferred embodiments as an oxide layer, it will be understood that spacer layer 92 may be formed of any dielectric material that may be controllably deposited on a layer of silicon carbide (or other material used), which is suitably susceptible to polish and removal techniques subsequently described and has a reasonable match with the coefficient of thermal expansion to that of silicon carbide or other material employed.

After formation of the oxide spacer layer 92, fill layer 94 is applied. The thickness of fill layer 94 may range from about 0.5 microns to 10.0 microns, and will be determined in relationship to the width of trench 90. Preferably, the thickness of fill layer 94 will be about 2 - 3 times the width of trench 90, in order to adequately fill and overfill trench 90. In the preferred embodiment, the material of fill layer 94 may be polysilicon. However, it will be understood that fill layer 94 may be formed of any material that may be controllably deposited on a layer of silicon carbide and which is suitably susceptible to the described polish and removal techniques. One consideration in selection of material for fill layer 94 is the matching of its coefficient of thermal expansion to that of substrate 10 and spacer layer 92. Such materials are typically applied following the high temperature anneal steps, making material choice less important. However, device operation at temperatures of 200° -600° C are anticipated, and long term reliability of various semiconductor devices may depend upon minimization of stresses arising from mismatch in thermal expansion of various materials. After formation of fill layer 94, chemical-mechanical polishing {CMP) and etch techniques are preferably applied to remove all of layer 94 with the exception of the portion applied in trench 90. |n a preferred embodiment, no portion of fill layer 94 will remain on the exposed top surface of substrate 10. A further requirement for full implementation of NL is to form resistors.

Typically, a single resistor may be used to set the current to the injection rail, from which each individual logic gate vertical PNP emitter will be fed. In FIGS. 13A and 13B is shown a method of forming resistors in silicon carbide. FIG. 13A is a side cross-sectional view. In this case, a lightly-doped n^" silicon carbide layer 16 is applied as a resistive layer. Ohmic contact is accomplished by ion implantation regions 20 along with ohmic metal 42 and 82. Desirably, one side of the resistor is tied to the underlying p silicon carbide layer 14 -by mesa etch 84. Lateral electrical isolation is also completed by mesa etch 84. As with other portions of the circuitry, dielectric 30 coats the surface of silicon carbide wafer 10 and is penetrated locally by contacts 86. FIG. 13B is a plan view of the same resistor.

In FIGS. 14A and 14B is illustrated another method of forming resistors in silicon carbide. FIG. 14A is a side cross-sectional view. Thin-film resistor layer 95 may be deposited, patterned and etched to form resistor traces as required. Thin- film resistor material may desirably be chosen to have a temperature coefficient of resistance that is close to zero. In addition, the material should be tolerant of the full design temperature range with little or no change in resistance. Examples of acceptable materials are heavily-doped polysilicon or mixtures of chrome, silicon, oxygen and nitrogen (CrSiO_xNy). In this case, interconnection is accomplished by overlapping metal layers 97 and 99. The ends of resistor layer 95 may be freely tied to circuit points. FIG. 14B is a plan view of the same resistor, illustrating the simplicity of this approach.

Following now are theoretical conclusions of the inventor supporting the invention disclosure provided herein. The conditions for successful switching of a logic gate can be predicted by making use of certain relationships. For instance, for the vertical NPN transistor: β = α

1 - α

where β is the transistor current gain, and α is the base transport factor. The requirement that β have a minimum value of 3 leads to a requirement thatα be at least 0.75. Now, it may be considered that:

α = αT * γ

where αT is the base transistor factor and Y is the emitter efficiency. Further, it may be considered that:

1 + μ_eN_bW_b/μ_bN_eWe

where y is emitter efficiency, μ is mobility, N is the impurity concentration, and W is the width of base or emitter, respectively. Now it may be considered that:

αT = 1 - Wb' 1 + 2 ^* μ_b * kT * T / q

where μ_b is mobility in the base, k is Boltzmann constant, T is temperature in Kelvin, q is the charge of an electron, and T is the lifetime of minority carriers in the base region. By assuming that T = 1 X 10^"8 seconds for 4H silicon -carbide and W_b = 3 X 10^'5 cm, then αT can be estimated to be 0.996. This means that more than 99.5% of the minority carriers that are injected into the base will arrive at the collector.

In order to support a minimum fanout of 3, it is required that the minimum transistor current gain be roughly 3. Additional requirements, as known in the art, have been established as follows:

lsp

where I_3n is the saturation current of the NPN switch transistor, and l_sp is the saturation current of the corresponding PNP current drive transistor, Furthermore, in general:

Is —

N_bW_b

where q is the electronic charge, A is the emitter-base junction area, D is the diffusion coefficient of minority carriers in the base, rij is the intrinsic carrier concentration, N_b is the doping concentration of the base, and W_b is the base width. Finally, the requirement is for:

β > 1

1 - Isn / lsp

There is design latitude to meet these conditions by appropriate adjustment of N_b, Wb and the areas of the two transistors. For instance, with the target parameters listed above, the N_bW_b product for the NPN transistor is about 1O0 times that of the N_bW_b product of the PNP transistor. Diffusion coefficients of minority carriers are of the same order of magnitude in the two transistors. Therefore, for equal emitter-base areas, l_sn/l_Sp is greater than about 10 and the listed conditions are easily met.

For 4H silicon carbide, hole mobility will be taken as 90 cm²/V-sec, and electron mobility as 475 cm²Λ/-sec, giving due consideration to typical dopant concentrations. Therefore, the ratio of mobility for p-type and n-type material is about 0.19 at room temperature. Further defining the total emitter charge Q_e = N_eW_e and Q_b = N_bW_b, it can be easily shown that a high emitter efficiency exceeding 0.89 requires that Q_e > 40 Qb for an NPN transistor, and Q_e > 0.-65 Q_b for a PNP transistor. Choosing for convenience that W_e = 3 x 10^"4 cm and Wt = 2.0 x 1O^~5 cm for the vertical NPN transistor, then the impurity concentration ratio must be greater than or equal to 2. Setting N_b = 2 x 10¹⁷ then requires N_e = 4 x 10¹⁷ on average throughout the emitter region. This combination of variables results in αT = 0.9, Y > 0.93, α > 0.81 and β > 4, as required. It may be noted that an implicit assumption in this calculation is that adequate passivation has been completed in order to minimize base current losses at the edge of the mesas. Also, the impurity concentration in the emitter region is not constant, since the substrate along with lightly-doped n-type epitaxy form the emitter. Therefore, an average value of impurity concentration was used in the above calculation.

For the vertical PNP transistor, choosing for convenience that W_e = 8 x 10^"6 cm and W_b = 1.5 x 10^"5 cm, the impurity concentration ratio must be greater than or equal to 50. Setting N_e = 1 x 10¹⁹, then N_b = 2 x 10¹⁷ is required in order to achieve acceptable current gain. Since the n-type base region is in common with the epitaxially grown collector region for the vertical NPN transistor, the concentration will desirably set to 2 x 10¹⁷. This combination of variables results in αT > 0.99, y = 0.91 , α = 0.90 and β = 9, which is entirely adequate. In addition, the expected BVCEO breakdown voltage of the vertical PNP transistor is about 15 - 30 volts, based on an expected critical field of 2 MV/cm or more. Such intermediately high BVCEO breakdown voltage allows for more flexible application of the vertical PNP transistor in other circuit portions. It may be noted that the above calculations are relatively insensitive to minority carrier lifetime assumptions, as long as the lifetimes are equal to or better than about 5 x 10^"9 s. This is due to the relatively thin base regions being applied. It will be understood by those having skill in the art that the order of steps in forming the devices described above may be changed. Thus, for example, the trench, refill and planarization steps may precede ion implantation and anneal. Similarly, the sequence of completing ion implantation regions 20, 23, 24 and 25 and 26 may be interchanged. Schottky contacts 80 may be formed by, for example, depositing and patterning a metal layer, and then the dielectric layer 30 provided and openings in the dielectric layer formed to the contacts 32. Accordingly, the present invention should not be -construed as limited 4o the exact sequence of operations described herein but is intended to encompass other sequences of fabrication that will become apparent to those of skill in the art in light of the present disclosure.

It will also be understood by those having skill in the art that junction transistors may be fabricated with opposite conductivity types to those described. For example, any NPN transistor may be changed to a PNP transistor by replacing each n-type region with p-type and each p-type region with n-type, with due respect given to the design limitations described above.

The embodiments shown and described above are only exemplary. Many details are often found in the art such as variations in materials and connection of parts. Therefore many such details are neither shown nor described. Even though numerous characteristics and advantages of the present inventions have been set forth in the foregoing description, together with details of the structure and function of the inventions, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of arrangement of the functional parts within the principles of the inventions to the full extent indicated by the broad general meaning of the terms used in the attached claims.

Claims

CLAIMS:

1. A semiconductor device comprising a substrate and an integrated injection logic gate, said integrated logic gate comprising:

(a) a constant current source transistor formed on said substrate; and

(b) a multi-collector switch transistor sharing said substrate with said constant current source transistor, wherein said constant current source transistor and said multi-collector switch transistor further comprise epitaxially grown metallurgical p-n junctions.

2. The device of claim 1 , wherein said constant current source transistor comprises a vertical PNP transistor.

3. The device of claim 1 , wherein said multi-collector switch transistor comprises a vertical NPN transistor.

4. The device of claim 3, wherein said multi-collector switch transistor comprises a Schottky collector.

5. The device of claim 3, wherein said multi-collector switch transistor has at least three collectors.

6. The device of claim 1 , wherein said substrate comprises at least one of silicon carbide, a material in the ll-VI family, and a material in the IH-V family.

7. The device of claim 6, wherein said substrate comprises a material in the Ill-Nitride family.

8. The device of claim 6, wherein said substrate comprises gallium arsenide.

9. The device of claim 6, wherein said substrate comprises indium phosphide.

10. The device of claim 7, wherein said substrate comprises gallium nitride.

11. The device of claim 1 , wherein said -substrate comprises silicon germanium coated with an epitaxial layer.

12; The device of claim 1 , wherein said substrate comprises diamond.

13. The device of claim 1 , further comprising a high-voltage device formed on said substrate.

14. A semiconductor device, comprising: (a) a substrate; and

(b) an integrated injection logic gate comprising silicon carbide and situated on said substrate, said integrated logic gate comprising: (i) a constant current source transistor; and

(ii) a multi-collector switch transistor.

15. The device of claim 14, wherein said constant current source transistor comprises a vertical PNP transistor.

16. The device of claim 15, wherein said multi-collector switch transistor comprises a vertical NPN transistor.

17. The device of claim 16, wherein said multi-collector switch transistor comprises a Schottky collector.

18. The device of claim 16, wherein said multi-collector switch transistor comprises at least three collectors.

19. The device of claim 14, further comprising a high-voltage device comprising silicon carbide and formed on said substrate.

20. A semiconductor device, comprising:

(a) a silicon carbide substrate;

(b) a plurality of logic gates formed in silicon carbide and situated on said substrate; and

(c) a high-voltage device formed of silicon carbide and situated on said substrate, said high-voltage device being in electrical communication with said plurality of logic gates.

21. The device of claim 20, wherein one of said logic gates comprises a vertical PNP transistor.

22. The device of claim 21 , wherein one of said logic gates comprises a vertical NPN transistor.

23. The device of claim 22, wherein one of said logic gates comprises a Schottky collector.

24. The device of claim 22, wherein one of said logic gates comprises at least three collectors.

25. A semiconductor device comprising a substrate and an integrated injection logic gate, wherein said integrated injection logic gate comprises a vertical PNP transistor.

26. The device of claim 25, further comprising a high-voltage device situated at said substrate and in electrical communication with said integrated injection logic gate.

27. A semiconductor device comprising:

(a) a substrate;

(b) an integrated injection logic gate situated at said substrate; and

(c) a high-voltage device situated at said substrate and in electrical communication with said integrated injection logic gate.

28. A method for fabricating a semiconductor device, comprising the steps of:

(a) providing a substrate comprising a top surface and a bottom surface;

(b) forming a lightly-doped first n-type layer on the substrate top surface;

(c) forming a heavily-doped second n-type layer on the first n-type layer; and

(d) etching the second n-type layer to form at least one island, thereby exposing at least a portion of the first n-type layer.

29. The method of claim 28, wherein said step of forming the first n-type layer produces a layer with a thickness of about 1 X) to 50 microns.

30. The method of claim 29, wherein said step of forming the first n-type layer produces a layer with a carrier concentration of form about 1 x 10¹⁴ cm^"3 to about 1 x 10¹⁷ cm^"3.

31. The method of claim 30, wherein said step of forming the second n- type layer produces a layer with a thickness of about 0.02 to 0.5 microns.

32. The method of claim 31 , wherein said step of forming the second n- type layer produces a layer with a carrier concentration of form about 1 x 10¹⁸ cm^{" 3} to about 1 x 10²⁰ cm^"3.

33. The method of claim 28, further comprising the step of forming a lightly-doped third n-type layer on top of the second n-type layer island and exposed portion of the first n-type layer.

34. The method of claim 33, wherein said step of forming the third n-type layer produces a layer with a thickness of about 0.1 to 5.0 microns.

35. The method of claim 34, wherein said step of forming the third n-type layer produces a layer with a carrier concentration of form about 1 x 10¹⁴ cm^"3 to about 1 x 10¹⁷ cm^"3.

36. The method of claim 33, further comprising the step of forming a moderately-doped first p-type layer on top of the third n-type layer.

37. The method of claim 36, wherein said step of forming the first p-type layer produces a layer with a thickness of about 0.05 to 1.0 microns.

38. The method of claim 37, wherein said step of forming the first p-type layer produces a layer with a carrier concentration of form about 2 x 10¹⁶ cm^"3 to about 1 x 10¹⁸ cm^"3.

39. The method of claim 36, further comprising the step of forming a lightly-doped fourth n-type layer on top of the first p-type layer.

40. The method of claim 39, wherein said step of forming the fourth n-type layer produces a layer with a thickness of about 0.02 to O.5 microns.

41. The method of claim 40, wherein said step of forming the fourth n-type layer produces a layer with a carrier concentration of form about 1 x 10¹⁴ cm^"3 to about 1 x 10¹⁷ cm^"3.

42. The method of claim 39, further comprising the step of forming a heavily-doped second p-type layer on top of the fourth n-type layer.

43. The method of claim 42, wherein -said step of forming the second p- type layer produces a layer with a thickness of about 0.O1 to 1.0 microns.

44. The method of claim 43, wherein said step of forming the second p- type layer produces a layer with a thickness of about 0.08 microns.

45. The method of -claim 44, wherein said step of forming the second p- type layer produces a layer with a carrier concentration of form about 5 x 1O¹⁸cm^{" 3} to about 1 x 10²¹ cm^"3.

46. The method of claim 42, further comprising the step of performing a pattern etching at the second p-type layer to form at least one emitter region of a vertical PNP transistor.

47. The method of claim 46, further comprising the step of performing a pattern etching of the fourth n-type layer to at least partially form a base of the vertical PNP transistor.

48. The method of claim 47, further comprising the step of ion implantation of an n-type dopant at the base of the vertical PNP transistor to form at least one first contact area.

49. The method of claim 48, further comprising the step of etching the second p-type layer to form a collector island of a multicollector switching transistor.

50. The method of claim 49, further comprising the step of ion implantation of an n-type dopant at the collector island to form a plurality of second contact areas.

51. The method of claim 40, further comprising the step of ion implantation of an n-type dopant at the second n-type layer to form at least one third contact area.

52. The method of claim 51 , further comprising the step of forming at least one collar region beneath the contact area by means of ion implantation of n-type dopant through the first p-type layer and third n-type layer prior to said step of forming the third contact area.

53. The method of claim 52, further comprising the step of forming a high- voltage device in said layers, said high-voltage device being in electrical communication with the vertical PNP transistor and multicollector switching transistor.

54. The method of claim 47, further comprising the steps of:

(a) applying a dielectric layer over the substrate; and

(b) etching the dielectric layer to form contact area openings.

55. The method of claim 54, wherein said step of forming the dielectric layer produces a layer with a thickness of about 0.05 to 1.0 microns.

56. The method of claim 55, wherein said dielectric layer comprises at least one of silicon dioxide and silicon nitride.

57. The method of claim 55, further comprising the step of forming an ohmic contact metal region in contact with one or more contact areas.

58. The method of claim 57, wherein said step of forming at least one ohmic contact metal region comprises the application of one of nickel, nickel alloy, titanium alloy, platinum, aluminum, cobalt suicide, platinum suicide, and tantalum suicide.

59. The method of claim 57, further comprising the step of sintering of the ohmic contact metal and contact area connections.

60. The method of 57, further comprising the step of applying at least one expanded metal runner at one or more of said ohmic contact metal regions.

61. The method of claim 60, wherein said step of applying the expanded metal runner comprises the steps of applying an adhesion layer and a conductive layer.

62. The method of claim 61 , wherein said step of applying an adhesion layer comprises the step of applying TiW, and said step of applying a -conductive layer comprises the step of applying Au.

63. The method of claim 60, further comprising the steps of applying a passivation layer and etching openings in the passivation layer.

64. The method of claim Q3, wherein said step of applying a passivation layer comprises the step of applying silicon nitride.

65. The method of claim 41 , further comprising the step of applying an ohmic layer to the bottom surface of the substrate.

66. The method of claim 36, further comprising the step of etching the first p-type layer to divide said first p-type layer into a plurality of electrically isolated regions.

67. The method of claim 42, further-comprising the step of applying at least one implantation region in the first p-type layer each beneath a contact metal region.

68. The method of claim 49, further comprising the step of applying a Schottky contact at the collector island.

69. The method of claim 51 , further comprising the step of forming a trench through a plurality of said layers.

70. The method of claim 69, wherein the trench extends from the second p-type layer to the substrate.

71. The method of claim 70, wherein the trench is formed with a width of between 0.5 and 5 microns.

72. The method of claim 71 , wherein the trench is formed with a width of about 2 microns.

73. The method of claim 70, further comprising the formation of a channel region circumscribing the trench.

74. The method of claim 73, further comprising the application of a spacer layer within the trench.

75. The method of claim 74, wherein the spacer layer is formed with a thickness between 0.01 and 0.5 microns.

76. The method of claim 75, wherein the spacer layer is formed with a thickness of about 0.15 microns.

77. The method of claim 74, further comprising the step of applying a fill layer within the trench.

78. The method of claim 77, wherein said step of applying a fill layer comprises the step of applying polysilicon.

79. The method of claim 49, further comprising the step of forming a resistor, said step comprising the steps of:

(a) etching the fourth n-type layer at a first location on the fourth n-type layer to create an opening to the first p-type layer;

(b) performing ion implantation at a plurality of second locations on the fourth n-type layer;

(c) applying ohmic metal and interconnecting the first location with one of the second locations.

80. The method of claim 54, further comprising the step of forming a resistor, said step comprising the steps of:

(a) depositing a thin-film resistor layer over the dielectric layer;

(b) applying a plurality of metal contact layers over the thin-film resistor layer.

81. The method of claim 80, wherein step of depositing a thin-film resistor layer comprises the step of applying one of heavily-doped polysilicon and a mixture of chrome, silicon, oxygen and nitrogen.