WO2006046237A2

WO2006046237A2 - Coded binary content addressable memory

Info

Publication number: WO2006046237A2
Application number: PCT/IL2005/001111
Authority: WO
Inventors: Yoav Lavi
Original assignee: Yoav Lavi
Priority date: 2004-10-26
Filing date: 2005-10-26
Publication date: 2006-05-04
Also published as: WO2006046237A3

Abstract

A novel method for the implementation of binary content addressable memories (420-470) is disclosed, where data to be stored and data to be compared are pre-coded prior to storage and prior to comparison, using a special code where a fixed number of bits (U0-U5) is always at Logic High.

Description

Coded Binary Content Addressable Memory

Technical Field

The present invention relates to the field of content-addressable memories. Such memories compare an input data word to a plurality of stored data words, generating Match signals for every stored word which is identical to the input word. While for many CAM implementations the stored words as well as the input word may be ternary in nature, having, in addition to the logic-zero and logic-one states, a third "don't care" state which does not affect the comparison, the present invention is limited to binary content addressable memories with logic-zero and logic-one states, and allows don't care only for groups of bits. Such limitation is not critical in some of the applications, and allows the use of a special coding scheme, which is applied to both the stored words and the input word, and which allows use of simpler circuits, resulting, for a given CAM size, in smaller area, faster operation and lower power consumption.

Description of Related Art

A: Background of the Invention

US patent 6,339,540: Content Addressable Memory for Virtual Ground Flash Architectures describes how virtual ground Flash technology can be utilized to build Content-Addressable memories, using 3, 2 or 1 Flash devices per bit.

In their earlier work —A 1-Mb 2-Tr/b Nonvolatile CAM Based on Flash Memory Technologies (IEEE Journal of Solid State Circuits, VOL. 31, NO. 11, November 1966) Miwa et al describe how contact-ground (as opposed to virtual ground) floating gate Flash technology can be used to implement 2-bit-per-cell Content-Addressable memories.

In Flash based implementations of prior art, for every bit U to be stored, two storage elements are used — one stores the value U, and one stores the inverted value -LJ. The reader should note that for NOR-type Flash memories, a Flash device is defined to store Logic-One if it is Erased; such Erased device shall exhibit low source-drain resistance if a certain High voltage, which, in some devices, may be 2 volts, is applied to its control gate. A device is defined to store Logic-Zero if it is Programmed; such Programmed device will exhibit high source-drain resistance when a voltage less than or equal to said High voltage is applied to its control gate.

The abovementioned two storage devices are also used for the comparison operation. By presenting the value of the compared bit C to the gate of the of the device storing ~U, and the inverse of the value of the compared bit ~C to the gate of the device storing U, and then by wire ANDing the two devices, a compare operation of this particular bit is performed, as is next described.

A single Flash based CAM cell 100 according to the prior art is depicted in Figure 1. Designating the data bit to be stored by U, Flash device 110 store the complement of U, while Flash device 120 stores U. Node Y 150 may be precharged to High by applying a high voltage to gate 140 of precharge device 130. Such precharge may be done, for example, when the gates of both devices 110 and 120 are held at a low voltage.

Comparand data C is applied to gate 160 of device 110, which stores the value of the complement of U, while the complement of comparand data C is applied to gate 170 of device 120, which stores the value of U.

Subsequent to the precharge cycle described above, node Y 150 assumes the value:

Y = ~((~A)*U+A*(~U)) = A XNOR U

In other words, node Y 150, will get the value of Logic One if and only if comparand data C, which is presented at gate 160 of device 110, and the complement of which is presented at gate 170 of device 120, is equal to the stored value U, which is represented by a programmed device 110 and an erased device 120 if at logic one, and by an erased device 110 and a programmed device 120 if at logic zero.

As is well described in the literature, a CAM device usually comprises a plurality of CAM cells such as 100, arranged in rows and columns. C lines 160 of all cells of the same column are wired together. Similarly, ~C lines 170 of all cells of the same column are also wired together. Horizontally, Y nodes 150 of all cells of the same rows are wired together, to form a row Match lines. Figure 2 depicts a single row 200 of a 4-bit Flash-based CAM, according to prior art. The four bits are stored in device-pairs 210-215, 220-225, 230-235 and 240-245, where the first device of each such pair stores the logic value of a single bit, and the second device stores the complement of the logic value of said bit.

After being precharged to a high voltage by precharge device 290, Node 250 will remain at high if none of devices 210, 215, 220, 225, 230, 235, 240, or 24:5 will conduct.

Denoting the stored bits by Ao, Ai, A₂ and A₃, and the comparand bits by Uo, Ui, U₂ and U₃, the value of node Y 250 can be expressed by the equation:

Y = ~((~Ao)*Uo+Ao*(~Uo)+(~A,)*U₁+A,*(~U,)+(~A₂)*U₂+A₂ *(~U₂)+(~A₃)*U3+A₃*(~U₃))

In other words — Y equals 1 if and only if all four bits of U are equal to all four bits of A.

It should be noted that if both of the storage devices of a particular bit store logic zero, that bit would never conduct, and the comparison will always match, irrespective of the value of the corresponding U and ~U comparand bits. Similarly, if both U and ~U comparand lines for a particular bit are held low, that bit would always match, irrespective of the value stored in the corresponding A and ~A devices. Thus, such prior art CAM implementations are ternary in nature, and can compare not only logic low and logic high states, but also a Don't Care stored state and a Don't Care comparison state.

A typical prior art CAM cell based on dynamic-storage is described in US06320777, and depicted in Figure 3. All the transistors in CAM Cell 300, namely 310, 315, 320, 325, 330 and 555, are N-channel MOS devices, which conduct when the voltage applied to their gates is high.

Capacitors Cl 350 and C2 355 are used to store the data, while transistors 320, 330, 325 and 335 are used for the comparison operation, and transistors 310 and 315 are used to write data into capacitors 350, 355, respectively.

Cell 300 can operate in Binary or Ternary mode. In Binary mode, capacitor 350 holds the value of the stored bit and capacitor 355 holds the value of its complement, while compare - A -

lines SL2365 and SLl 360 hold the values of the bit to be compared and of its complement, respectively.

In Ternary operation, when a bit is masked off, both capacitors 350, 355 store a Low level; similarly, when a compared bit is masked off, both SLl 360 and SL2 365 lines will be at Low.

Write operation is achieved when Write line 380 is held at a high voltage. Transistors 310 and 315 charge capacitors 350, 355 to the values presented at the BLl 370 and BL2 375, respectively.

While both the Flash-based and the D-RAM based cells described above exhibit ternary operation, the same basic cell is used in the prior art for binary-CAM devices.

However, in many applications, Ternary structure is not a must, and when the same cell structure used for ternary CAM is embodied, inefficient binary-CAM circuits are obtained.

Description of the Current Invention

A: Brief Description

It is, therefore, an object of the current invention to implement a Flash or D-RAM based binary CAM in a way which is significantly more efficient than the one used in prior art Flash based and D-RAM based CAM circuits.

Towards that objective, the current invention employs a special coding mechanism which translates the data to be stored, from n bit binary representation to an m bit code (m>n), wherein the number of bits at logic high is constant. A similar mechanism, which may utilize the same circuit, translates the data to be compared to the same code.

Thereafter, the comparison of the incoming data to the stored data may be done with a simpler circuit than the one used in ordinary CAM circuits.

Specifically, while the comparison function in previous art CAM devices is an implementation of the function: Y = AND ((A, XNOR B,), (A₂ XNOR B₂), ...(A_n XNOR B_n))

According to the current invention it is replaced by the simpler function:

Y = AND ((A'_! AND B',), (A'₂ AND B'₂), ...(A'_n AND B'_n))

Where m-element vectors A' and B' are translation of n element vectors A and B respectively, to a code where a constant number of bits are at logic high.

B: Brief Description of the Drawings

Figure 1 depicts a prior art Flash-based CAM cell

Figure 2 depicts a prior art 4-bit Flash based CAM word

Figure 3 depicts a prior art DRAM based CAM cell

Figure 4 depicts a NOR-Flash based binary CAM word, according to the current invention.

Figure 5 depicts a NAND-Flash based binary CAM word, according to the current invention

Figure 6 illustrates in principle a full array of CAM memory, built according to embodiments of the current invention, and comprising a generic cell 65 O

Figure 7 illustrates four alternative embodiments of cell 650 of Figure 6, based on NOR Flash, NAND Flash, Virtual-Ground NOR Flash, and DR.AM technologies.

C: Detailed Description of the Invention

I. Simplifying the Comparison

Basic VLSI logic structures implement NAND and NOR functions using parallel and series connections of transistors. The logic operation of comparing two bits, that is -Exclusive-Or or Exclusive-Nor (XOR or XNOR) - cannot be directly implemented, as it takes more than a series or a parallel connection. This is the reason why in the prior art two storage devices are needed per bit. For binary operation, it is possible to map the from the 2ⁿ vector space to a subset of 2^m (m>n) vector space in a way so that Comparison operation will not consist of XOR or XNOR operation but, rather, of a basic VLSI operation like NAND or NOR.

One such subset of the 2^m vector space is a space where k of the bits are at logic-one and (m- k) of the bits are at logic-zero, k being a constant number. In order to test if two members of this subset are identical, suffice it to check if the bits at logic-one, or the bits at logic-zero, are identical. This checking can be done by elementary VLSI NAND or NOR structures.

Such 2^m vector space subset, whereas the number of bits at logic high is a constant k, will be referred to as k/m code below.

The following elementary example depicts how a four bit address space is represented by 3/6 code:

As there are 20 3-of-6 combinations, and, hence, four combinations are not used.

Figure 4 schematically depicts an implementation 400 of the single row Contact-Ground- Nor-Flash-Based Binary CAM according to the present invention. For more rows, the illustrated row is repeated, as will be shown below. The stored binary values have been pre- coded using the table above to a 3/6 code, and the complements of the bits have been stored in the Flash devices. When a new binary code is to be compared, it is first mapped to the 3/6 code by translator 490. Thereafter, the U bits are applied to the control gates of Flash devices 420, 430, 440, 450, 460 and 470, and a comparison is performed. Node 480 may be pre- charged by transistor 410 to a high voltage prior to the comparison, and will remain high after the comparison, indicating a Match, if and only if all U bits a_t Logic-One re applied to gates of programmed Flash devices.

As would be appreciated by those ordinarily skilled in the art, circuit 400 is readily expendable to CAM structures having a multitude of words, as well as to a different number of bits per word or to a virtual-ground NOR Flash CAM arra;y, with floating gate or with isolator gate. Moreover, Node 480 could be precharged to vo> ltages other than Logic-High, and Flash devices 420 through 470, when conducting, could drive Match line 480 to voltages other than Ground, all within the scope of the present invention.

Other embodiments of the current invention are based on NAJSID-Flash. Figure 5 schematically describes an implementation 500 of a single row of such NAND-Flash-Based Binary CAM. Node 550 may be precharged by precharge device 510 to Logic High. A Match is detected if all Flash devices 520, 521, 522, 523, 524 and 52,5 conduct, creating a full path from node 550 to a ground voltage connected to the end of the Flash-devices series. Such Match will be indicated by transition to Logic Low on Node 550.

As known in the industry, an Erased Flash device in a NA^"ND-Flash device conducts, irrespective of the voltage on its control gate; a Programmed NAND-Flash device conducts only if a Logic High is applied to its control gate. Hence, there will be path from Node 550 to ground if and only if all programmed Flash devices of the group 520, 521, 522, 523, 524 and 525 will have Logic High at their corresponding control gates.

Both stored data and comparand data are translated by translator 530 to a code with three set bits out of 6. Flash devices 520, 521, 522, 523, 524 and 525 Λvill be programmed for logic high, and erased for Logic Low. When a comparison is done, Translator 530 will translate the compared data to the same 3/6, and drive the gates of Flash devices 520, 521, 522, 523, 524 and 525 accordingly. Node 550 will be discharged if and only if all three programmed Flash devices will have Logic One at their control gates, indicated a full Match. As would be appreciated by those ordinarily skilled in the art, circuit 500 is readily expendable to CAM structures having a multitude of words, as well as to a different number of bits per word. Moreover, Node 480 could be precharged to voltages other than Logic- High, and the connection to ground at the end of the Flash devices series could be a connection to other voltage, all within the scope of the present invention.

IL Formal Proof

We will now formally prove that the comparison method described above for a k/m code is equivalent to prior art comparison. We will use the NOR-Flash exmaple

We denote:

• Uon - the set of indices for which the U lines are at 1 ; Uon G { 1 ,2,3...m} , and includes k elements

• Uoff - Same as Uon, for those U lines which are at 0

• Aon - the set of indexes for which trie A devices are programmed ON; Aon C { 1,2,3... m}, and includes k elements

• Aoff - Same as Aon, for those Flash, devices which are programmed OFF

Note that Uon, Uoff are mutually exclusive, and their union is the full space { 1,2,3... m}. The same is true for Aon and Aoff.

Now, if Uon=Aoff, it follows that Uoff=Aon. This means that all devices with logic-high at the control gate will have a stored logic-low, and all devices with logic-low at the control gate will have stored logic-one - hence no device will conduct, and Y will be on (match).

If Uon ≠ Aoff, it follows that Uoff ≠ Aon. This means that there will be at least one logic- one-programmed device with logic-one at the control gate. This device will conduct and pull Y down, indicating No Match.

The proof for the NAND-Flash is similar, as should be obvious to those ordinarily skilled in the art. III. Detailed Description

The simple example above will now be followed by a general description of the new invention. Reference is made to Figure 6, which depicts the general structure 600 of an embodiment of the present invention. Uncoded binary data to be stored in CAM array 640 is applied through bus 610 to Encoder 620, which translates the n bit binary representation to an m bit code, where a fixed number k of bits are at Logic High (k/m code).

The same Encoder 620 may be used when CAM information is written into the storage devices of array 640, and when information is to be compared with the stored information. However, in some embodiments, the code of the written information is logically inverted relative to the compared information.

Array 640 comprises r rows of m bit words, wherein each row comprises m identical cells 650, which may be i) a Contact-Ground-NOR-F lash-based cell, as depicted in Figure 7A, in a first group of embodiments; ii) a NAND-Flash-based cell, as depicted in Figure 7B, in a second group of embodiments; iii) a Virtual-Ground-NOR-Flash-based cell, as depicted in Figure 7C, in a third group of embodiments; and iv) a DRAM-based cell, as depicted in Figure 7D, in a fourth group of embodiments.

It should be noted that cells 650a, 650b, and 65Oc and 65Od are considerably smaller than their prior art counterparts, depicted in Figure 1 for the Contact-Ground-NOR-Flash-based cell and in Figure 3 for the DRAM base cell.

The Program and Erase mechanisms of cells 650a, 650b, 650c, as well as the Write and Refresh mechanisms of cell 65Od are omitted, for simplicity, but are in effect no different than what the practice is for Contact-Ground-NOR-Flash, NAND-Flash, Virtual-Ground- NOR Flash and DRAM cells, respectively.

In both the DRAM-CAM case and the two types of NOR-Flash-CAM case, any one of the plurality of common horizontal Match lines 660 will not be pulled low if and only if all paths to ground in all cells connected to such Match line will not conduct. When a comparison takes place, for every comparand generated by Encoder 620, exactly k of the m vertical lines 630 are at Logic One, and, consequently, if any of the storage elements 651, 654 corresponding to those vertical lines stores Logic One, a conduction path to ground through cell 650 will be formed, and the corresponding match line 660 will be pulled low.

One should note that, in the two NOR-Flash and the DRAM groups of embodiments, when information is stored in the CAM, the coded representation is inverted, and for a given k/m coed word, k of m stored bits will be at Logic One, while the same k of m comparand bits will be at Logic Zero, hence the line will be High if and only if the full code matches.

For the NAND-Flash-CAM, each horizontal Match line is divided to segments, interconnected by all Flash devices of the corresponding row. Match lines 660 will be pulled low if and only if the full path through all Flash devices of any particular Match line will conduct. When a comparison takes place, for every comparand generated by Encoder 620, exactly k of the m vertical lines 630 are at Logic One, and m-k lines are at Logic Low. If any of the storage elements 652 corresponding to vertical lines with Logic Low, is programmed and hence stores Logic Low, a conduction path to ground through cell 650 will not be formed, and the corresponding match line 660 will be remain high, indicating no match.

Sense amplifiers 670 amplify the voltage of the horizontal lines, and may also provide them with pre-charge mechanism, so that lines which, are not pulled Low will be at High.

It should be noted that the implementation details of Encoder 620 are not part of the invention, and methods to generate optimized implementation of translators from one binary space to another are well known in the art. Reference to some translators will be given below.

IV. Group Don't Care

Although the current invention is limited to binary CAM devices, and individual bits cannot be masked off from the comparison, it is possible to mask off groups of bits. Towards that end, the coding is done on groups of bits. In each group, if it is to be masked off the comparison, an all-zero code may be asserted on the vertical lines, or an all-one code for the NAND-Flash embodiments. If masking of the stored data is desired, all stored bits of that group may be at logic low, or at logic-high for the NAND-Flash embodiments. Thus that group will allow a Match, and will effectively be masked off the comparison. Moreover, by choosing different coding lengths to various parts of the word, with the division determined a priori or dynamically, one can fit the data structure ideally to the application.

For example, a record in a database may have the following fields:

Field A - 1 bit Field B - 12 bits Field C - 20 bits Field D - 1 bit Field E - 4 bits

This record can be encoded using the following groups:

Field A (I bit) - 1/2 Field B (12 bits) - 6/15 Field C (20 bits) - 11/23 Field D (I bit) - 1/2 Field E (4 bits) - 3/6

The total is 48 lines versus 76 for data and data complement in a full ternary implementation, with a Don't Care per field, where it may be desired..

V. Implementation of n bit to k-set-bit-of-m Translators

The implementation of n bit binary to m bits with k bits set can be done in a variety of ways, as described in numerous digital design text books, as well as by automatic synthesis programs. Those techniques constitute prior art, and are not claimed herein.

For several examples, the reader is referred to WO 2005/081629 (PCT/IL2005/000214) patent application.

While the invention has been particularly taught and described with reference to several embodiments, those versed in the art will appreciate that minor modifications in the form of detail may be made without departing from the spirit and scope of the invention. Accordingly, all such modifications are embodied within the scope of this patent as properly come within any contribution to the art, and are particularly pointed out by the following Claims.

Claims

ClaimsI claim:

1. A semiconductor Content Addressable Memory (C AM), comprising: a. A plurality of rows, wherein each row comprises i) a common match line, which may be segmented or continuous; ii) a plurality of Coded CAM cells, wherein each such cell comprises a storage section for a single bit of coded information, and a compare transistor, which may or may not be part of said storage section, connected to said coded information bit and to a single coded, bit of the information to be compared, and wherein anyone of said compare transistors may force said common match line to a logic state indicating No Match; and b. One or more translation circuits, wherein each such translating circuit, at least in some cases, translates the binary information to be stored, and/or the binary information to be compared, to a binary code wherein a fixed number of bits is at a certain logic level, and the remaining bits are at a complementary logic level thereof.

2. The semiconductor Content Addressable Memory of Claim 1 , wherein each said coded CAM cell may be realized by a. single Flash device, and wherein the plurality of such Flash devices in each, row may be connected to said common match line, i) in series, wherein the common compare line for each row is segmented; ii) in parallel, wherein for every such Flash device, the source terminal is connected to said common match line and the drain terminal to a power supply; or iii) in parallel, wherein for every such Flash device, the source terminal is connected to a common match line and the drain terminal to a neighbor common match line

3. The semiconductor Content Addressable Mtemory of Claim 1 , wherein the storage section of said CAM cells are dynamic type, relying on a capacitive node for storage of information.

4. The semiconductor Content Addressable Memory of Claim 1 , wherein one or more of said translation circuits may also generate a Group Don't Care code, forcing all coded bits in one or more groups, to a logic state, in response of which none of said Compare transistors will force said common match line to a logic state indicating No Match, irrespective of the state of the corresponding stored coded bit.

5. The semiconductor Content Addressable Memory of Claim 1 , wherein part or all of said translation circuit is replaced sometimes or at all times by an equivalent function being implemented by a software program.