WO2006042261A1 - Acces direct a la memoire multicanaux avec memoire fifo partagee - Google Patents

Acces direct a la memoire multicanaux avec memoire fifo partagee Download PDF

Info

Publication number
WO2006042261A1
WO2006042261A1 PCT/US2005/036629 US2005036629W WO2006042261A1 WO 2006042261 A1 WO2006042261 A1 WO 2006042261A1 US 2005036629 W US2005036629 W US 2005036629W WO 2006042261 A1 WO2006042261 A1 WO 2006042261A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
channel
write
storage area
read
Prior art date
Application number
PCT/US2005/036629
Other languages
English (en)
Inventor
Sivayya Ayinala
Praveen Kolli
Franck Seigneret
Nabil Khalifa
Original Assignee
Texas Instruments Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP04292404A external-priority patent/EP1645967B1/fr
Application filed by Texas Instruments Incorporated filed Critical Texas Instruments Incorporated
Publication of WO2006042261A1 publication Critical patent/WO2006042261A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • This invention relates in general to the field of electronics; and, more specifically, to a multi-channel Direct Memory Access (DMA) with shared First-In-First-Out (FIFO) memory.
  • DMA Direct Memory Access
  • FIFO First-In-First-Out
  • Direct Memory Access is a technique that allows for hardware in a computer to access system memory independently of the system processor. Because the processor is not involved in the transfer of data, DMA is usually fast. DMA is very useful for example in real ⁇ time applications and for making backups.
  • a few illustrative examples of hardware that use DMA circuits include sound cards, hard disk controllers and computer subsystems.
  • Traditional DMA circuits have one or more physical channels, wherein each physical channel is a point-to- point communication link connected from a source to a destination port. Although useful, the point-to-point links make the system inflexible and may limit the performance of the DMA for some applications.
  • Some traditional DMA circuits with multiple logical channels use several physical channels to perform concurrent transfers with each physical channel being associated to a separate data First-In-First-Out (FIFO) memory.
  • FIFO First-In-First-Out
  • Another problem with some DMA circuits is that their data FIFOs may be under utilized based on the channel transfer context. A need thus exists in the art for a storage circuit that can improve the reuse of the DMA and provide better flexibility and efficiency.
  • the invention provides a data storage area for use in a direct memory access circuit having a read port and a write port.
  • the data storage area comprises a data memory configured and adapted to be shared by a plurality of channels supported by the DMA circuit; a next read address storage area coupled to the data memory, the next read address storage area being configured and adapted to store the next address indicating a location from which to read the next data from a channel currently granted on the write port; and a next write address storage area coupled to the data memory, and configured and adapted to allocate the next address location to which to write the next data of a channel currently being serviced on the read port.
  • the data memory comprises a static random access memory (SRAM) or flip-flop based memory.
  • the data memory may be configured and adapted to be allocated dynamically in order to maximize the number of channels from among the plurality of channels to be scheduled and concurrently active.
  • the data storage area may include means, coupled to the data memory, for controlling the amount of memory in the data memory that each active channel can use.
  • the data memory may, optionally, be configured and adapted to store all data sent from the read port to the write port.
  • the data memory may also be adapted and configured to store the location of the next address from which to read the next data for the channel currently granted on the write port.
  • the data storage area is configured and adapted so that, if a requesting channel is granted access on the read port, a new next write address is retrieved from the next write storage area if the channel that has been granted has been scheduled by the DMA for the first time.
  • the data storage area may be configured and adapted so that the next read address storage area is integral to the data memory.
  • the next write address storage area comprises a First-In-First-Out (FIFO) circuit.
  • the data storage area may be configured and adapted, so that the next write address output value from the next write address First-In-First-Out (FIFO) circuit is written into the next read address storage area.
  • FIFO First-In-First-Out
  • a direct memory access (DMA) circuit comprises a read port; a write port; and a unified shared First-In-First-Out (FIFO) memory circuit coupled to the read and write ports.
  • the unified shared FIFO circuit may comprise a data memory which is shared amongst a plurality of channels supported by the DMA circuit; and a next write address storage area coupled to the data memory, the next write address storage area allocates the next address where to write the next data of a channel currently being serviced on the read port.
  • FIG. 1 is a system level block diagram in accordance with one embodiment of the invention.
  • FIG. 2 is a block diagram of a Direct Memory Access (DMA) in accordance with an embodiment of the invention.
  • FIG. 3 is a block diagram, giving additional details of an example of the DMA shown in FIG. 2.
  • DMA Direct Memory Access
  • FIG. 4 is a diagram, highlighting four threads received on a read port of a DMA in accordance with an embodiment of the invention.
  • FIG. 5 is a diagram, highlighting two threads in a write port of a DMA in accordance with an embodiment of the invention.
  • FIG. 6 is a block diagram of a DMA read port scheduler in accordance with an embodiment of the invention.
  • FIG. 7 is a block diagram of a DMA write port scheduler in accordance with an embodiment of the invention.
  • FIG. 8 is a block diagram of an example First-In-First-Out (FIFO) memory circuit in accordance with an embodiment of the invention.
  • FIFO First-In-First-Out
  • FIG. 9 is a functional block diagram, highlighting data alignment and endian conversion in accordance with an embodiment of the invention.
  • FIG. 10 is a graphic transparent color block diagram in accordance with an embodiment of the invention.
  • FIG. 11 is a constant color fill block diagram in accordance with an embodiment of the invention.
  • FIG. 12 is a functional graphic module implementation for a transparent copy in accordance with an embodiment of the invention.
  • FIG. 13 is a functional graphic module implementation for solid color fill in accordance with an embodiment of the invention.
  • the present invention provides for a DMA circuit that minimizes the relationship between the logical and physical channels.
  • a unified shared FIFO is provided in the DMA circuit which is shared by all of the logical channels and the depth of the FIFO is allocated dynamically.
  • Using a dynamic shared FIFO allows for the maximum number of channels to be scheduled and concurrently active and it also allows allocation of the entire FIFO to a single channel if there is only one logical channel active.
  • Using a dynamic shared FIFO increases the DMA's data transfer performance, including the capacity to pre-fetch and buffer data. It also allows for the maximum burst length to be used.
  • a per-channel FIFO depth budget can be set for one or more of the channels, including all of the channels if needed.
  • the description will first discuss an overview of the DMA circuit and will then discuss the FIFO aspects of the DMA in more detail.
  • the FIFO used in one embodiment of the invention relies on three memory resources:
  • a "2 FD X OCP_width" data FIFO that is shared with no restriction between all of the channels.
  • FD stands for the FIFO Depth, depth of storage area in FIFO
  • OCP_width are both RTL generic parameters.
  • the FIFO is implemented using a SRAM or flip-flop based memory.
  • a NextWriteAddress FIFO also of size "2 FD X FD", which allocates the next address where to write the next data of the channel currently serviced on the read port side. This is a true FIFO memory.
  • FIG. 1 shows a block diagram of an electronic system 100 in accordance with an example embodiment of the invention.
  • System 100 includes a Main Processor Unit (MPU) subsystem 106 coupled to an Open Core Protocol (OCP) bus or system interconnect 120.
  • the MPU subsystem 106 can include any one of a number of microprocessors or microcontrollers or similar control circuitry.
  • a Digital Signal Processing (DSP) subsystem 102, a camera subsystem 110, an internal memory 114, an external memory 116 and a peripheral interconnect 118 are also coupled to the OCP bus 120.
  • the peripheral interconnect 118 provides interconnection to any one of a number of peripheral devices such as timers, general purpose input/output (GPIO), etc.
  • GPIO general purpose input/output
  • the DSP subsystem 102 includes a DSP DMA (dDMA) 104, the camera subsystem 110 includes a camera DMA (cDMA) 112 and a system DMA (sDMA) 108 all in accordance with embodiments of the invention.
  • dDMA DSP DMA
  • cDMA camera DMA
  • sDMA system DMA
  • the DMA circuits used in the dDMA 104, cDMA 112 and sDMA 108 comprise multipoint-to-multipoint DMA circuits which function as multi-threaded initiators each having four threads (or m threads) on their read port and two threads (or n threads) on their write port.
  • the number of channels and the number of hardware requests can be changed at user configuration time. In one embodiment, the number of channels ⁇ 32 and the number of requests ⁇ 127.
  • FIG. 2 there is shown a block diagram of a DMA circuit 200 such as used in the dDMA 104, sDMA 108 and the cDMA 112 shown in FIG.l in accordance with an embodiment of the invention.
  • DMA 200 includes a read port 202, a write port 204, a configuration port 208 and a unified data first-in first-out (FIFO) 210.
  • FIFO 210 in FIG. 2 is presented in a logical format and is shown sharing between different channels (ChO-ChN) 212.
  • DMA events/requests such as hardware requests are received in port 206.
  • the DMA 200 can support in one embodiment up to 127 requests.
  • All DMA requests can be active low (or high depending on the design) and can be configured to be either edge sensitive or transition sensitive and can be either synchronous or asynchronous.
  • the DMA 200 includes two decoupled read and write contexts and schedulers (discussed below).
  • the read port 202 and write port 204 can support up to m threads and n threads respectively, where each thread can perform either a single access or a burst access.
  • a thread is associated to a service and a service can comprise a single or burst transaction. For example, if only one channel is scheduled, only one thread is associated to the channel and up to four bursts can be outstanding.
  • Each burst can for example be 4 X 32 bits.
  • DMA circuit 200 Some of the features of the DMA circuit 200 include:
  • Logical channels features: Software channel enabling, hardware channel triggering, edge/level hardware DMA request sensitive, programmable request/channel pair mapping, source/destination address generators (constant addressing, post-increment, single indexing and double indexing), different element/frame index for source and destination, unified memory buffer, shared between all channels, unified FIFO memory, size specified at design time, linked logical channel (LCH) support, speculative pre-fetch for synchronized channels, optional software controllable and capability to monitor the progress of the DMA transfer using element and frame counters.
  • LCH linked logical channel
  • All active channels can share ports based on arbitration and priority and can also support LCH (logical channel) first-come-first-served as well as fixed priority arbitration.
  • LCH logical channel
  • Security Per channel secure attributes set by a secure transaction and secure qualifier set on the master interface when a secure channel is scheduled.
  • DMA request synchronization Supports element, packet, frame and block synchronization.
  • Power management Standby mode and idle mode, auto-gating capability, auto-idle and software controlled power down.
  • Interrupts Some of the available interrupts include end frame, end block, end packet, half frame, last frame, transaction access error, secure access error and supervisor access error.
  • Debug Through the configuration port a user can check current channel status for all channels, FIFO status, channel transfer status, data integrity, etc.
  • FIFO draining When a channel is disabled and there is data in the corresponding FIFO, the data is drained onto the write port and transferred to a programmed destination. 11).
  • Buffering disable In case of source synchronized transfers, buffering can be enabled or disabled by setting a buffering disable bit (DMA4_CCR.buffering_disable) respectively to 0 or 1. When buffering is enabled, data fetched from the source side on a hardware request may not be flushed/transferred completely to the destination side until a subsequent hardware request fetches more data from the source side (to be able to pack/burst to the destination).
  • both the source and destination are synchronized (e.g., element/frame/packet/block synchronized) during transfer.
  • the last write transaction in the frame or in the block is non-posted write (WRJSfP) even if the write mode is set to 2 (WLNP).
  • WRJSfP non-posted write
  • WLNP write mode
  • there should be a WRNP at the end of the packet (even if write mode 2) only in case of destination synchronization.
  • the packet interrupt is not generated in the source synchronized case.
  • Table 1 highlights some generic parameters supported by the DMA circuit 200 in accordance with an embodiment of the invention.
  • the mentioned features are not meant to be all inclusive but are just some of the features that can be provided by the DMA circuit 200 (also referred to as DMA4) of the present invention.
  • the flexible nature of the DMA circuit 200 allows for its use in multiple areas of a design such as in a DSP subsystem, as a system DMA and in a camera subsystem as shown in FIG. 1.
  • FIG. 3 is a more detailed block diagram of the DMA circuit 200.
  • the DMA circuit 200 includes a read port (DMA4 Read Port) 202 and a write port (DMA4 Write Port) 204.
  • Coupled to the DMA4 read port 202 is a channel requests scheduler (DMA4 Read Port scheduler) 302, an OCP request generator 306 and a read port response manager 308.
  • the read port 202 is either a 32-bit or a 64-bit read-only OCP master interface, and the choice between 32-bit or 64- bit is preferably made at design time.
  • the DMA4 read port scheduler 302 is responsible for selecting the next channel to be serviced, and for allocating a thread identifier to be used on the OCP interface (MThreadID field).
  • a channel is granted access to the read port 202 by the arbitration logic, for one OCP service.
  • This can be either an OCP single transaction or an OCP burst transaction (4X32- bit/2X64-bit, 8X32-bit/4X64-bit, 16X32-bit/8X64-bit), in accordance with the channel programming for the DMA source.
  • the channel programming can be modified based on system design requirements.
  • a maximum of four thread IDs can be allocated in the read side, from 0 to 3 (ThO, ThI, Th2 and Th3).
  • the DMA circuit 200 can have up to four outstanding read transactions belonging to up to four channels in the system interconnect.
  • For an arbitration cycle to occur two conditions must be satisfied: (a) There is at least one channel requesting; and (b) there is at least one free thread ID available.
  • the scheduler 302 grants the highest priority channel that has an active request, allocates the thread ID, and tags this thread as Busy.
  • the channel read context is restored from the shared channel context memory 316.
  • a maximum of four thread IDs can be allocated in the read side, from 0 to 3 (ThO, ThI, Th2 and Th3).
  • the DMA circuit 200 can have up to four outstanding read transactions belonging to up to four channels in the system interconnect.
  • For an arbitration cycle to occur two conditions must be satisfied: (a), there is at least one channel requesting and (b) there is at least one free thread ID available.
  • the scheduler 302 grants the highest priority channel that has an active request, allocates the thread ID, and tags this thread as Busy.
  • the channel read context is restored from the shared channel context memory 316.
  • FCFS First Come First Serviced
  • channels can be given a high-priority attribute.
  • Non-synchronized channels will be put in the queue when the software sets the enable bit.
  • Synchronized channels will be put in the queue when the hardware DMA request comes in for them.
  • CHi has a higher priority than CHj if j>i.
  • the others will be processed in subsequent cycles.
  • This rule can of course be modified depending on system design requirements.
  • the top of each queue can be scheduled in each cycle.
  • a software configurable 8-bit priority counter is used to give weighting to the priority queue. For every N (1 to 256) schedules from the priority queue one will be scheduled from the regular queue. A channel that is scheduled will go to the end of the queue after it finishes its turn on the port. At a given time, a channel cannot be allocated more than one thread ID.
  • each channel is given a ThreadID for the current service only, not for the whole channel transfer.
  • the current channel number/ThreadID associations are stored, and made available to the read response manager 308.
  • one thread ID is allocated during the channel transfer and back to back service (Burst or single) can be done with a maximum of 4 consecutive bursts (e.g., 4x32) without rescheduling the channel at the end of each burst transfer. If non-burst alignment occurs at the beginning of the transfer, then the channel is rescheduled for each smaller access until burst aligned. Also, if the end of the transfer is not burst aligned, the channel is rescheduled for each one of the remaining smaller accesses.
  • the read port logic can generate the next OCP address sent to the OCP interface.
  • An OCP READ request is generated by the OCP request generator 306, and is then issued on the OCP interface.
  • the request can be qualified by sideband signals,, some of the sideband signals include: MThreadID field, based on the scheduler allocation; MReqSecure attribute, as read from the channel context; MReqSupervisor attribute, as read from the channel context; MReqEndianness, as read from the channel context; MReqDataType, as read from the channel context (element size);
  • MCmd/SCmdAccept handshaking is performed normally, as required by the . OCP protocol.
  • the read response manager 308 can identify the channel that "owns" the data. This data is submitted to the shared-FIFO control logic, and written into the FIFO 314 at the appropriate location. Once the data is written into the FIFO 314, if this is the last data of the channel service (i.e. single data service or last data of a burst service), the threadID becomes free again and its status is updated. The last data of a response is identified by a "SRespLast" qualifier. Table 1 Generic parameter list
  • circuitry 322 which includes four registers, one for each thread and the necessary selection and path set-up circuitry. Thread responses can be interleaved, even within bursts, on the read port 202.
  • the read port scheduler 302 and the write port scheduler 304 are mainly arbitrating between channels at a thread boundary.
  • One thread is associated to one DMA service, where a service can be a single or burst transaction as mentioned previously.
  • each channel context is composed of one read context and one write context, with the read and write contexts being scheduled separately.
  • the associated channel "i" is scheduled.
  • the channel context is loaded, then each time there is an OCP read request, one thread m (0 up to 3) is allocated during the whole read transaction. While there is a free thread, other channels can be scheduled according to the arbitration schema employed. One thread becomes free as soon as the corresponding channel read transaction (e.g., a single transaction, burst transaction of 4 X 32 or 8 X 32) is finished. Once a thread becomes free it can be allocated to another channel.
  • the configuration port 208 operates as a slave port and is not buffered.
  • the configuration port 208 is used for configuration and access to status registers found in the DMA circuit 200.
  • the configuration port 208 is a synchronous 32-bit data bus that supports 8, 16 and 32-bit aligned data and non-burst accesses.
  • the configuration port 208 can also access memory locations, logical channel context and hardware requests memory locations.
  • Coupled to the DMA4 write port 204 is a DMA4 write port scheduler 304, an OCP request generator (includes unpacking control) 310 and a response manager 312.
  • the write port 204 is driven from the requests coming from the data FIFO 314.
  • the OCP write port is either a 32-bit or a 64-bit write- only OCP master interface, the choice between 32-bit or 64-bit is made at design time, although other designs can have different bit sizes.
  • FD FD x OCP_width
  • OCP_width 2 FD x OCP_width.
  • the buffering budget, for one channel is preferably bounded using a programmable threshold specified in a register entitled "DMA4_GCR".
  • the write port scheduler 304 is responsible for selecting the next channel to be serviced, and for allocating a thread identifier to be used on the OCP interface (MThreadID field).
  • a channel is granted access to the write port 204 by the arbitration logic, for one OCP service, this can be either an OCP single transaction or an OCP burst transaction (4X32- bit/2X64-bit, 8X32-bit/4X64-bit, 16X32-bit/8X64bit), in accordance with the channel programming for the DMA destination.
  • a maximum of two thread IDs can be allocated, 0 or 1 (ThO and ThI on the write side).
  • DMA circuit 200 can have up to two outstanding write transactions belonging to up to two channels in the system interconnect in this embodiment using circuitry 320.
  • Any channel that is ready to be scheduled will be put at the end of the queue, either regular (low priority) or high priority depending on the priority bit.
  • Non-synchronized channels will be put in the queue when the software sets the enable bit.
  • Synchronized channels are put in the queue when the hardware DMA request comes in for them.
  • CHi has a higher priority than CHj if j>i. The others will be processed in subsequent cycles.
  • each burst can be for example 4x32-bit
  • the channel is rescheduled for each smaller access till it is burst aligned. Also, if the end of the transfer is not burst aligned, the channel is rescheduled for each one of the remaining smaller accesses.
  • each queue can be scheduled in each cycle.
  • a software configurable 4 bits priority counter is used to give weighting to the priority queue. For every N (1 to 256) schedules from the priority queue one will be scheduled from regular queue. A channel that is scheduled will go to the end of the queue after it finishes its turn on the port. Note that if more than channel is active, each channel is given a ThreadID for the current service only, not for the whole channel transfer. The current channel number/TlireadID associations are stored, and made available to the write port response manager 312. From the restored channel context, the write port logic can generate the next OCP address sent to the OCP interface. An OCP WRITE request is then issued by the OCP request generator 310 on the OCP interface, qualified by sideband signals.
  • the write command used on the OCP interface can be either a posted write (OCP WR command) or a non-posted write (OCP WRNP command):
  • OCP WR command a posted write
  • OCP WRNP command a non-posted write
  • the OCP write interface selects the write command to be used, based on the channel attributes as programmed by the user. There are three possibilities:
  • All DMA4 writes expect a response on the OCP interface.
  • the response is provided very quickly by the system interconnect, whereas a non-posted write transaction gets its response later, after the effective write has been completed at the destination target.
  • Handshaking is performed normally, as required by the
  • the write port response manager 312 can identify the channel that owns the response. Once the data is read from the FIFO 314, if this is the last data of the channel service (i.e. single data service or last data of a burst service), the threadID becomes free again and its status is updated. The context for the channel just serviced is saved back via circuitry 320 into the shared channel context memory 316. If should be noted that thread responses can be interleaved, even within bursts, on the write port 204.
  • the Configuration port 208 can access all global 318 and channel registers in either 8- bit, 16-bit or 32-bit. Four of the registers need a shadow register to be read correctly: DMA4_CSAC : Channel Source Address Counter; DMA4_CDAC : Channel Destination Address Counter; DMA4_CCEN : Channel Current transferred Element Number; and DMA4_CCFN : Channel Current transferred Frame Number
  • Packing is performed on the read port side 202 when the channel element type is narrower than the read port 202, and if this feature has been enabled by the DMA programmer.
  • the packing feature is enabled if the DMA source is qualified as a non-packed target, and the DMA destination is qualified as a packed target. Packing is not compatible with source burst transactions, only destination burst can be enabled when packing is selected.
  • Each time a channel requiring a packing operation is scheduled on the read port 202 only a partial write is done to the memory buffer on the appropriate byte lanes, with the valid bytes of the current OCP response.
  • the data memory must provide byte access granularity during a write operation in the data FIFO 314.
  • the byte enable memory must also be updated accordingly. No new NextWriteAddress from NextWriteAddress FIFO 336 is allocated until the memory word is complete, i.e. when the last byte of the memory word is effectively written.
  • the channel FIFO level is also updated on this event. This update event is triggered based on the current byte address of the read access, with respect to the element type and the transaction endianness. Based on address alignment and total transfer count, the first and last packed- words can be partial. This is reported to the write port side using the byte enable memory 332.
  • Unpacking is done on the write port side when the channel element type is narrower than the write port 204, and if this feature has been enabled by the DMA programmer.
  • the unpacking feature is enabled if the DMA source is qualified as a packed target, and the DMA destination is qualified as a non-packed target. Unpacking is not compatible with destination burst transactions, only source burst can be enabled when unpacking is selected. When both source and destination targets are packed or unpacked then packing and unpacking operations are disabled.
  • the DMA 200 targets can have different endianness type.
  • An endianness module 324 is used to match the endianness of the source target and the destination target.
  • more than one endianness module may have the capability to convert endianness if required. It is possible to inform the next module in the target of the read and write request paths to lock the endianness. This is qualified by an in-band signal (MreqEndiannessLock) when (DMA4_CSDP.Src_Endianness_lock) or
  • DMA4_CSDP.Dst_Endianness_lock is set to 1.
  • the DMA 200 generates an MReqDataType and MREqEndianness in-band qualifiers.
  • Address alignment control 328 is required so that any source byte on any read port byte lane can be transferred on any write port byte lane.
  • An optional two-dimensional (2-D) graphic module 330 provides hardware acceleration for two commonly used graphics operations: (1) Transparent Copy (also known as transparent- blit, or source color key copy), and (2) Constant Solid Color Fill. Transparent Copy:
  • DMA 200 supports a COLOR KEY (defined in a per channel register named DMA4_COLOR) feature for 8bpp, l ⁇ bpp and 24bpp from source to destination, i.e. each element of the channel source is compared to a color key value, and those data bits (pixels) that match the color key are not written to the destination.
  • DMA4_COLOR a per channel register
  • the data-type specified in the DMA4_CSDP register are respectively 8-bit, 16-bit and 32-bit.
  • 32-bit (24bpp) data transfer [31 :24] is O'.
  • the color pattern is written at the following bit field of a configuration register, DMA4_Color register which stores the COLOR KEY value as follows :
  • Burst/packed transactions can be used with no restriction. Each time there is a color key match, the write access is discarded using the write port byte enable pattern, but the write OCP transaction is performed normally. Thus, there is no performance penalty when this feature is enabled.
  • the address of each access has to be aligned with an ES (Element Size), which corresponds to the pixel size.
  • ES Element Size
  • DMA4_COLOR storing the COLOR KEY value and as previously mentioned, all of the channels have their own register.
  • the transparent copy is preferably performed before the data is put in the data FIFO 314.
  • a functional block diagram of a 2-dimensional graphic transparent color block diagram is shown in FIG. 10.
  • Solid Constant Color Fill This feature allows filling a region with a solid color or pattern, by repeating the data horizontally and vertically in the region. Since the solid color fill and the transparent copy functions are mutually exclusive in the same channel a "DMA4_C0L0R" register is shared to set the constant color value, based on its data type. For 8bpp, 16bpp and 24bpp, the data-type specified in a "DMA4_CSDP" register is respectively 8-bit, 16-bit and 32-bit. During the 32- bit (24bpp) data transfer, the data [31 :24] is "0". The color pattern is written at the following bit field of the DMA4_Color register:
  • the register data does not come from the read port 202; but is the source for solid fill data that goes out on the write port 204.
  • the solid constant color Fill feature allows filling a region with a solid color or a pattern, by repeating the data horizontally and vertically in the region. Since the solid color fill and the transparent copy functions are mutually exclusive, the DMA4_COLOR register is shared to set the constant color value, based on its data type. The pixel color (or pattern) is replicated so that the full register width is occupied. The address of each access has to be aligned with the ES (Element Size), which corresponds to pixel size.
  • the solid constant color fill is preferably performed at the output of the data FIFO.
  • a functional block diagram of a 2- D constant color fill is shown in FIG. 11.
  • the pixel element is compared through a comparator unit, to the content of the color register, if the two values match the corresponding byte enables (BEs) are forced to zero going into the data FIFO. However, if the two values do not match, the BEs are written into the data FIFO unchanged.
  • the solid color there is a bypass from the color register to the write port through a multiplexer unit, which is driven by the solid color signal.
  • the two graphic functions being mutually exclusive.
  • FIG. 12 there is shown a functional block diagram for the transparent copy implementation
  • FIG. 13 shows a functional block diagram for a solid fill implementation in accordance with embodiments of the invention.
  • the DMA circuit 200 can generate OCP bursts on both the read port 202 and the write port 204.
  • the burst model complies with the OCPIP2.0 with the following characteristics: 1). Incrementing, precise bursts:
  • the burst size can be 16 bytes, 32 bytes or 64 bytes.
  • a 32-bit DMA4 instance that means 4x32 or 8x32 bursts, 16x32-bit burst, for a 64-bit DMA4 instance that means 2x64 or 4x64 bursts or 8x64 bursts.
  • Smaller burst sizes than the programmed burst size is also allowed. This is usually used when the start address is not aligned to the programmed burst size or the data remaining to be transferred is less than the programmed burst size. Better performance is achieved than by performing single transactions till the address is aligned for programmed burst size. Because of this, 2x32 burst is allowed on 32 bit OCP interface.
  • AU bursts are aligned: A burst is always starting on the memory address aligned on the burst size. This does not mean the OCP parameter burst_aligned should be ON, as this parameter assumes the byte enable pattern is all l's and constant during the whole burst. This condition is not always met on the write port 204 operating in transparent-blit mode, as the byte enable pattern is used to eliminate pixels that must not be written into the memory (when there's a match with the color key). Even with the burst_enable option on, in the channel programming at the beginning of the transfer, DMA 200 can wait for the OCP address to reach a value aligned on the burst size, before issuing burst transactions. Therefore the first channel accesses can consist of single transactions.
  • DMA 200 does not generate non-completed bursts. At the end of a channel transfer, if there is not enough data (to be read or written) for filling a full burst, single transactions are issued on the OCP interfaces.
  • DMA 200 will automatically split this burst access into multiple smaller accesses (minimum number of aligned accesses) until address is aligned on the Burst boundary. If last transfer is not burst aligned, then the remaining data are split into minimum aligned smaller access.
  • FIG. 4 there is shown a diagram highlighting a read port 202 multi- threading scenario were the read port has four threads (ThreadIDO, ThreadIDl, ThreadID2 and ThreadID3) 402-408 in accordance with an embodiment of the invention.
  • the current status for each of the threads (0-3) is shown in time lines 410-416 respectively.
  • With the read requests (OCP_Read_Request) and read responses (OCP_Read_Responses) highlighted on time lines 418 and 420 respectively. As shown in 422, it takes one or two cycles to switch from a first logical channel (LCH(i)) to another logical channel (LCH(J)).
  • FIG. 5 there is shown a diagram highlighting a write port 204 multi ⁇ threading scenario in accordance with an embodiment of the invention.
  • OCP_Write_Request OCP write request
  • ThreadO and Threadl are shown. While there is a free thread, other channels can be scheduled according to the arbitration schema employed in the particular design.
  • One thread becomes free as soon as the corresponding channel write transaction (e.g., single transaction, burst transaction of 4 X 32 or 8 X 32) is finished. Once a thread becomes free, it can be allocated to another channel.
  • FIG. 5 shows four logical channels LCH ⁇ , LCH Q) , LCH (k) and LCH ( i ) , the current status of the two threads (ThreadO and Threadl) is also shown. As also shown, it takes one or two cycles from the end of a write request to start a new write request.
  • FIG. 6 there is shown a functional diagram of the read port scheduler 302.
  • Hardware 602 and software enabled channel requests 604 are received into the scheduler and go through a first level of arbitration in block 606.
  • the channel requests are split into high priority and low (regular) priority channels.
  • the logic for determining what characterizes a high priority and low priority channels are dependent on the system design requirements.
  • the high priority channels go to arbitration logic 606 were arbitration between concurrent channel requests occurs. For example, depending on the arbitration rules, Chi may have priority over Chj when i ⁇ j.
  • the low priority channels go through the low priority channel arbitration logic 612, High and low priority channel scheduling and rescheduling for the high priority channels occurs in 610, while the low priority channel scheduling and rescheduling occurs in 612. Another arbitration between the high and low priority channels occurs in 614 according to the weight (W) given to the high priority channels provided via block 616.
  • the available read threads 618 are allocated and provided to the read service request 620.
  • FIG. 7 there is shown a write port scheduler block diagram similar to the read port scheduler shown in FIG. 6.
  • FIG. 8 there is shown a block diagram of a data FIFO 800 used in accordance with an embodiment of the invention. Data FIFO is similar to the memory shown in FIG. 3 (314, 332 and 334).
  • Data FIFO 800 contains all the data transmitted from the read port 202 to the write port 204 in DMA 200.
  • the data FIFO 800 is shared with no restriction between all of the channels.
  • the data FIFO 800 has a memory size of 2FD X (OCP_width + byteen_width + FD) with the FD and the OCP_width being generic RTL parameters (byteen stands for byte enable).
  • the FIFO size will be 256 X (64 + 8 + 8).
  • the data FIFO relies on two main memory resources, the shared data FIFO memory 808 and the NextWrite address FIFO (NWA) 804.
  • the shared data FIFO memory 808 contains all of the data transmitted from the read port 202 to the write port 204. It should be noted that the term FIFO is used by reference to the functionality as seen from the user's perspective; the actual implementation uses random access memory (e.g., SRAM).
  • the data FIFO 808 also contains the byteen (byte enable) and the next read address (NRA) where to read the next data from the channel currently granted on the DMA write port side.
  • the NWA FIFO 804 (e.g., having a size of (2 F ⁇ X 2FD)) allocates the next address where to write the next data of the channel currently serviced on the read port side.
  • the NWA FIFO 804 is a true FIFO memory, preferably implemented using RAM memory such as SRAM.
  • the NWA and NRA are saved/restored in the read/write channel contexts 804. New locations are allocated to a channel only if the current allocated location(s) is full, or the channel is being scheduled for the first time.
  • a set of run- time registers 318 are associated with the memory resources such as a per channel counter that continuously monitors the number of data in the channel FIFO. These counters are used to limit the maximum number of entries any logical channel can use in the data FIFO 800.
  • the dynamic buffer allocation is based on a chaining mechanism, managed according to a set of rules.
  • CH(,thID) is used to designate channel i having been allocated thread thiD.
  • Some of the rules include: 1).
  • a bist like engine can be used to accomplish this which writes the values in the memory after reset. 2).
  • a requesting channel gets granted on the DMA read port, if the channel is scheduled for the first time, then a new NextWriteAddress is requested from the NWA memory 804 (the associated memory field) and loaded into the NextWriteAddress(th ⁇ D) register. If the channel is scheduled again after being suspended, then the NextWriteAddress(thID) register is loaded from the associated memory field in the channel context memory read during the restore operation.
  • NextWriteAddress FIFO output value is simultaneously written into the NextReadAddress memory (same address as NextWriteAddress) if the location in the data FIFO pointed to by the NextWriteAddress is full.
  • the channel context restore operation includes saving of the current NextWriteAddress(th ⁇ D) register into the associated memory field. 3). DMA Write Port (204) side:
  • the channel context restore operation includes loading the NextReadAddress(th ⁇ D) register from the associated memory field.
  • the NextReadAddress value is written into the NextWriteAddress FIFO (meaning the memory location is now free and can be used for a new data) if all the data at that location is processed.
  • the NextReadAddress(thID) is preferably updated simulataneously from the value read at that same address, from the NextReadAddress memory, if all the data at that location is processed. This provides the address of the next data for the current channel.
  • the channel context restore operation includes saving of the current NextReadAddress(th ⁇ D) register into the associated memory field.
  • the Read Port scheduler 302 must prevent the data FIFO from overflowing. For that purpose, there is a counter that continuously tracks the number of remaining free locations in the FIFO 802. When the FIFO 802 is almost full (full minus the longest burst supported on the read interface), the scheduler 302 stops scheduling the requests, until there is enough room in the FIFO 802. A similar protection mechanism exists on a per-channel basis; so that a channel is not scheduled if there isn't enough provision in its level status counter.
  • the system controller When a logical channel is disabled or aborted because of a transaction error, the system controller (not shown) must make sure that all memory locations used by that channel can be re-used. In case of an abort, if there is any channel data remaining in the FIFO (i.e. the channel status counter is not 0), all these data are extracted from the FIFO 802 but discarded, so that all addresses can be effectively re-allocated.
  • Some of the generic parameters used with the FIFO 800 include: N, the number of logical channels, OCP_wdith, which is the width of the data ports and of the internal data path, FIFO_depth, which is the depth of the data FIFO shared between all of the channels, the FIFO_depth can be chosen as a power-of-two as an example, in that case, the FIFO_depth can be expressed as 2 FD .
  • Some of the memory requirements include for a two-port main memory, 2 FD x (OCP_width + OCP_width/8 + FD) and for a two-port memory for the FIFO, 2 (FD' ° x (2*FD).
  • the data memory size is not directly linked to the number of logical channels.
  • the FIFO_depth is set to a value between 4xiVand 8xiV. If the FIFO_ depth is not a power-of-two, FD corresponds to the next power-of-two.
  • the information related to the scheduled channel is saved on a thread basis both for the read 202 and write 204 ports.
  • the incoming data from the read port 202 is saved in the data FIFO 800 based on the information saved during the schedule cycle. Before the data is put in the FIFO endian conversion 324 and transparent copy operations are performed on the data.
  • the write port side the data is taken out of the FIFO and aligned to the destination address for that channel. In case of a solid fill, the write data is provided based on a register value instead from the FIFO 800.
  • the schedule information if a channel abort bit has been set, the FIFO 800 is cleared up and all the locations used up by the aborted channel are restored.
  • the incoming data is first accumulated in a register (one for each thread) and when the register is full or when the end of the data transfer has occurred for the thread, then the data is written into the FIFO 800. This is done because a single read on the read port 202 can cause multiple writes to the FIFO. If this happens for all the threads at the same time, the FIFO 800 writes cannot keep up with the incoming data. When the FIFO memories are accessed during CPU BIST, the normal operation of the FIFO 800 will be interrupted (i.e., functional FIFO read and writes will be missed).
  • the FIFO operation includes the data alignment operation performed by the endianness conversion logic (see 324 in FIG. 3) and the address alignment control 328.
  • the endian conversion of the data is preferably performed at the input of the data FIFO while the alignment to the destination address is performed at the output of the data FIFO.
  • These functions are implemented as part of the data FIFO manager.
  • the address programming registers for the source target and the destination target it assumed that the start addresses are always aligned on an element (data type) boundary. If the data type is s8 (8 bit scalar data) for example, then the addresses can have any value.
  • the addresses must be aligned on 16 bits (lowest bit of the address is 0). If the data type is s32 (32 bit scalar data), then the addresses must be aligned on 32 bits (the lowest 2 bits of the address are 00).
  • the data read from the source side read port
  • the source data from the OCP read port is directly written into the data FIFO TABLE 1: Endian Conversion
  • the endianness conversion logic 324 which is implemented as part of the overall FIFO data manager function, if the source and destination endianness are different, then the source data has to be converted to the destination endianness.
  • the endianness conversion is done on the data type boundary and before the data is written into the data FIFO 314. Table 1 below shows all of the possible combinations.
  • FIG. 9 shows a functional block diagram highlighting the data alignment and endian conversion in accordance with an embodiment of the invention.
  • the DMA 200 with unified data FIFO of the present invention allows for the maximum number of channels to be active concurrently.
  • the DMA with unified data FIFO allows for maximum use of the data FIFO. Thereby increasing the DMA' s data transfer performance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

L'invention concerne un circuit d'accès direct à la mémoire (DMA) (200) qui comprend un accès lecture (202) et un accès écriture (204). Le circuit DMA (200) est un initiateur multitrajets, avec m trajets sur l'accès lecture (202) et n trajets sur l'accès écriture (204). Le circuit DMA (200) comprend une fonction FIFO pour données (210) pouvant être partagée par tous les canaux logiques, et la profondeur FIFO peut être attribuée de façon dynamique, permettant la programmation et l'activation simultanée du nombre maximum de canaux. On peut également affecter la fonction FIFO (210) à un canal unique s'il n'y a qu'un seul canal logique actif. La fonction FIFO (210) augmente la performance de transfert DMA, la capacité de pré-extraction et la mise en mémoire tampon, tout en optimisant le processus pipeline.
PCT/US2005/036629 2004-10-11 2005-10-11 Acces direct a la memoire multicanaux avec memoire fifo partagee WO2006042261A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP04292404A EP1645967B1 (fr) 2004-10-11 2004-10-11 DMA multicanal avec tampon PEPS partagé
EP04292404.3 2004-10-11
US11/080,277 2005-03-15
US11/080,277 US7373437B2 (en) 2004-10-11 2005-03-15 Multi-channel DMA with shared FIFO

Publications (1)

Publication Number Publication Date
WO2006042261A1 true WO2006042261A1 (fr) 2006-04-20

Family

ID=36148675

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/036629 WO2006042261A1 (fr) 2004-10-11 2005-10-11 Acces direct a la memoire multicanaux avec memoire fifo partagee

Country Status (1)

Country Link
WO (1) WO2006042261A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115833920A (zh) * 2023-02-14 2023-03-21 北京融为科技有限公司 一种解调数据的传输方法和装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182183B1 (en) * 1998-11-13 2001-01-30 Sonics, Inc. Communications system and method with multilevel connection identification
US6336150B1 (en) * 1998-10-30 2002-01-01 Lsi Logic Corporation Apparatus and method for enhancing data transfer rates using transfer control blocks
US6557052B1 (en) * 1999-06-07 2003-04-29 Matsushita Electric Industrial Co., Ltd. DMA transfer device
US20040028053A1 (en) * 2002-06-03 2004-02-12 Catena Networks, Inc. Direct memory access circuit with ATM support

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336150B1 (en) * 1998-10-30 2002-01-01 Lsi Logic Corporation Apparatus and method for enhancing data transfer rates using transfer control blocks
US6182183B1 (en) * 1998-11-13 2001-01-30 Sonics, Inc. Communications system and method with multilevel connection identification
US6557052B1 (en) * 1999-06-07 2003-04-29 Matsushita Electric Industrial Co., Ltd. DMA transfer device
US20040028053A1 (en) * 2002-06-03 2004-02-12 Catena Networks, Inc. Direct memory access circuit with ATM support

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115833920A (zh) * 2023-02-14 2023-03-21 北京融为科技有限公司 一种解调数据的传输方法和装置
CN115833920B (zh) * 2023-02-14 2023-04-25 北京融为科技有限公司 一种解调数据的传输方法和装置

Similar Documents

Publication Publication Date Title
US7373437B2 (en) Multi-channel DMA with shared FIFO
US7761617B2 (en) Multi-threaded DMA
US9032104B2 (en) Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling
US7496699B2 (en) DMA descriptor queue read and cache write pointer arrangement
USRE41849E1 (en) Parallel multi-threaded processing
US7523228B2 (en) Method for performing a direct memory access block move in a direct memory access device
KR101557090B1 (ko) 이종 소스들에 대한 계층적인 메모리 중재 기법
EP1247168B1 (fr) Memoire partagee entre processus elementaires de traitement
US7603490B2 (en) Barrier and interrupt mechanism for high latency and out of order DMA device
US10241946B2 (en) Multi-channel DMA system with command queue structure supporting three DMA modes
US6560667B1 (en) Handling contiguous memory references in a multi-queue system
US20050223131A1 (en) Context-based direct memory access engine for use with a memory system shared by devices associated with multiple input and output ports
JP2016536692A (ja) コンピュータ画像処理パイプライン
EP0908826A2 (fr) Protocole pour paquets de données et dispositif distribué fonctionnant en mode rafale
US9015376B2 (en) Method for infrastructure messaging
US20020059393A1 (en) Multicore DSP device having coupled subsystem memory buses for global DMA access
JPH0587854B2 (fr)
US10740256B2 (en) Re-ordering buffer for a digital multi-processor system with configurable, scalable, distributed job manager
CN108958903B (zh) 嵌入式多核中央处理器任务调度方法与装置
WO2006042108A1 (fr) Acces direct en memoire multitache
CN109426562B (zh) 优先级加权轮转调度器
US8996772B1 (en) Host communication device and method with data transfer scheduler
EP1564643A2 (fr) Modèle VHDL synthétisable d'un contrôleur DMA multicanal pour un système de bus intégré
WO2006042261A1 (fr) Acces direct a la memoire multicanaux avec memoire fifo partagee
WO2007039933A1 (fr) Dispositif de traitement de fonctionnement

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase