WO2006040720A2 - Controlling parasitic bipolar gain in a cmos device - Google Patents

Controlling parasitic bipolar gain in a cmos device Download PDF

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WO2006040720A2
WO2006040720A2 PCT/IB2005/053308 IB2005053308W WO2006040720A2 WO 2006040720 A2 WO2006040720 A2 WO 2006040720A2 IB 2005053308 W IB2005053308 W IB 2005053308W WO 2006040720 A2 WO2006040720 A2 WO 2006040720A2
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layer
semiconductor material
source
source region
mos transistor
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WO2006040720A3 (en
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Prabhat Agarwal
Jan W. Slotboom
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Koninklijke Philips Electronics N.V.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Definitions

  • CMOS device operates correctly.
  • thermal or over- voltage stress current can be injected into the PNP emitter-base junction, forward-biasing it and causing current to flow through the substrate 104 and into the P-well 108.
  • the NPN device 1 10b turns on, increasing the base drive to the PNP device 110a, and initiating a condition known as latch-up, which is a failure mechanism of CMOS integrated circuits characterized by excessive current drain coupled with functional failure, parametric failure and/or device destruction.
  • the present invention proposes the provision of a "virtual contact" to modify the gain of the parasitic bipolar transistor in CMOS devices by modifying the effective surface recombination rate at the source interface.
  • Surface recombination can be defined as the recombination of free charge carriers in a semiconductor via electrically active centres (defects) at its surface.
  • the term "a virtual contact” is used herein to denote a semiconductor surface that appears like a metallic contact to minority carriers, yet presents no significant electrical obstacle to majority carriers.
  • a preferred material for the virtual contact 120 in the case where the substrate 104 is of silicon, is doped SiGe as a layer on the source contact 122.
  • a Si / . ⁇ Ge ⁇ alloy (where x denotes the relative Ge concentration in the alloy) is relatively easy and cheap to incorporate into existing standard Si processes, making it a good choice in this case.
  • other materials are envisaged for use in the present invention, and the present invention is not necessarily strictly limited in this regard.
  • t is the thickness of the SiGe layer
  • N is the doping level of this layer
  • the exponent is the change in band-gap due to SiGe relative to Si. It will be seen, therefore, that the difference in bandgap between the Si substrate and the layer of SiGe can be exploited to increase the surface recombination velocity (as Equation 2) and thereby decrease the current gain of the respective parasitic bipolar transistor (as Equation 1).
  • the value of x can be controlled in respect of the SiGe layer in order to set the band-gap at the required value to achieve the desired current gain.
  • the virtual contact layer does not have to cover the whole of the contact surface/substrate interface.
  • the minority carriers (holes, in an N-type device) injected into the source will go to the sink created by the virtual contact layer, even if the whole source is not covered by that layer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A CMOS device comprising an n-channel MOS transistor (102) and a p­channel MOS transistor (100), defining a pair of parasitic bipolar transitors (110a, 110b) therebetween, wherein a layer (120) of doped SiGe is provided over the source region (106a) of at least one of the MOS transistors (100, 102), between the source region (106a) and the source contact (122). The layer (120) of material acts as a sink for minority carriers (holes in an N-type device) at the source, which has the effect of increasing surface recombination velocity (because the landgap of SiGe is lower than that of the Si substrate (104)), which, in turn, lowers the current gain of the respective parasitic bipolar device. As a result, the effects and/or occurrence of latch-up, and other breakdown instabilities associated with parasitic bipolar devices, can be limited.

Description

Controlling parasitic bipolar gain in a CMOS device
This invention relates to the control of parasitic bipolar gain in a CMOS (Complementary Metal Oxide Semiconductor) device and, more particularly, to the control of current gain of parasitic bipolar devices formed within a CMOS device structure, so as to limit the occurrence and/or effects of instabilities such as latch-up in respect thereof. Referring to Fig. 1 of the drawings, there is illustrated schematically, a cross- section through a CMOS structure comprising a P-channel MOS 100 and an N-channel MOS 102 diffused into an n-type substrate 104. As shown, the n-channel source and drain 106a, 106b have been diffused into a "well" 102 of p-type material which is isolated from the substrate 104 only by a (reverse biased) pn junction. This structure results in a pair of parasitic bipolar transistors: 110a (PNP) 110b (NPN). Normally, only a small leakage current flows between the substrate 104 and P-well 108, causing on a minute bias to be built up across the bulk due to the resistivity of the material. In this case, the depletion layer formed around the resultant reverse biased PN junction between the P-well 108 and the substrate 104 supports the majority of the Vcc-GND voltage drop. As long as the MOS source and drain junctions remain reverse-biased, a CMOS device operates correctly. However, in the presence of intense ionising radiation, thermal or over- voltage stress current can be injected into the PNP emitter-base junction, forward-biasing it and causing current to flow through the substrate 104 and into the P-well 108. At the point, the NPN device 1 10b turns on, increasing the base drive to the PNP device 110a, and initiating a condition known as latch-up, which is a failure mechanism of CMOS integrated circuits characterized by excessive current drain coupled with functional failure, parametric failure and/or device destruction.
As might be expected, latch-up is highly dependent on the characteristics of the bipolar devices 110a, 110b involved in the latch-up loop. Device current gains, emitter efficiencies /minority carrier life times and the degree of NPN-PNP circuit coupling are all important factors relating to both the sensitivity of the particular latch-up device and to the severity of the failure once it has been excited.
In fact, the high current gain of the parasitic bipolar device formed by the source/bulk/drain in MOS devices is responsible, not only for latch-up, but also other instabilities, such as BVCEO (Breakdown Voltage Collector to Emitter, base terminal open) breakdown in CMOS architectures, and these instabilities greatly affect the reliability and ESD protection properties of modern MOS transistors. Although the current gains of the parasitic bipolar transistors 1 10a, 110b are normally relatively very low, they can be made high if a large current is injected into the loop, even transiently. In addition, bipolar gains increase as CMOS channels become shorter.
Referring to Fig. 2 of the drawings, there is illustrated schematically the result of the parasitic bipolar instability referred to above. Electrons 112 injected into the channel accelerate as they travel toward the source 106a. In the high field region of the junction between the channel and the drain 106b, electron 112/hole 113/pairs are generated by impact ionisation. While electrons 112 travel into the drain 106b and cross the gate-oxide into the gate 116, holes 113 will diffuse to the substrate 104. However, some holes 113 will have enough energy to be back- injected into the source 106a, and it will be appreciated that the proportion of holes 113 that can enter the source 106a is expected to increase with more advanced CMOS generation. For every extra hole 113 in the source 106a, several extra electrons 112 will enter the channel, the relative factor being the gain of the bipolar device, and this leads to positive feed back and a resulting instability.
Traditionally, this type of instability has been addressed using isolation techniques. For example, one known solution is to completely isolate the MOS structures using a glassy insulation layer. This "dielectric isolation" prevents any form of parasitic interaction between the structures.
Japanese Patent Application No. JP-62266864A describes a CMOS device structure in which a high concentration diffused layer region, having a conductivity type which is the same as that of the semiconductor substrate, is formed in at least a source or drain region of the device. The diffused layer region absorbs holes which would otherwise be back- injected into the source, with the intention that the number of holes diffusing in the vicinity of the source is sufficiently decreased to prevent latch-up.
We have now devised an improved arrangement, and it is an object of the present invention to modify the gain of one or more of the parasitic bipolar devices formed within a CMOS integrated circuit structure, so as to limit the occurrence and/or effects of the above-mentioned instabilities, such as latch-up.
In accordance with the present invention, there is provided a CMOS device comprising an n-channel MOS transistor and a p-channcl MOS transistor on a semiconductor substrate, each MOS transistor comprising a gate electrode, a source region and a drain region, said source and drain regions being diffused within said semiconductor substrate, wherein a layer of semiconductor material is disposed over at least a portion of the source region of at least one of said MOS transistors, said semiconductor material being such that said layer forms a sink for minority carriers at said source region.
Also in accordance with the present invention, there is provided a method of manufacturing a CMOS device comprising an n-channel MOS transistor and a p-channel MOS transistor on a semiconductor substrate, the method comprising providing in respect of each MOS transistor a gate electrode, a source region and a drain region, said source and drain regions being diffused within said semiconductor substrate, the method further comprising forming a layer of semiconductor material over at least a portion of the source region of at least one of said MOS transistors, said semiconductor material being selected such that said layer forms a sink for minority carriers at said source region.
The present invention also extends to an integrated circuit die including at least one CMOS device as defined above.
Thus, the concept underlying the present invention is to modify the gain of the respective parasitic bipolar device created within a CMOS device by modifying the effective surface recombination rate at the source interface. Beneficially the layer of semiconductor material has a bandgap lower than that of the substrate. In a preferred embodiment, the layer of semiconductor material is disposed between at least a portion of the source region of the substrate and a source contact. Beneficially, the semiconductor material used to form the sink for minority carriers is SiGe because a Si/-ΛrGex alloy (where x denotes the relative Ge concentration in the alloy) is relatively easy and cheap to incorporate into standard Si processes. Furthermore, the bandgap of this alloy decreases with increasing x, so the bandgap of the resultant layer can be carefully controlled to achieve the desired reduction in the gain of the respective parasitic bipolar device, and a preferred method according to the present invention further comprises the step of selecting x accordingly.
The layer of semiconductor material may cover substantially all, or only one or more portions, of the source region of the MOS transistor.
These and other aspects of the invention will be apparent from, and elucidated with reference to, the embodiment described herein.
An embodiment of the present invention will now be described by way of example only, and with reference to the accompanying drawings, in which: Fig.l is a schematic cross-sectional view of a CMOS device; Fig. 2 is a schematic diagram illustrating the occurrence of parasitic bipolar instability in a CMOS device;
Fig. 3 is a simplified schematic cross-sectional view of a CMOS device according to an exemplary embodiment of the present invention; and
Fig. 4 illustrates measured Gummel plots for collector current Ic and base current IB of a parasitic bipolar transistor in a conventional CMOS process, whereby it can be seen that bipolar gains increase as CMOS channels become shorter.
As it has been established above, the parasitic bipolar device formed by the source/bulk/drain in MOS devices is responsible for latch-up and breakdown instabilities. These instabilities greatly affect the reliability and ESD protection properties of modern MOS transistors. Traditionally, these problems were addressed by isolation procedures. In contrast, the present invention employs the concept of controlling the gain of the parasitic bipolar device and thereby at least limiting the occurrence and/or effects that lead to the above-mentioned instabilities.
There are two components that control the current gain of the parasitic bipolar device. Firstly, the integrated charge in the base region controls the collector current. This is usually expressed in terms of the so-called "Base Gummel number" (see Figs. 4A and 4B). Secondly, recombination in the emitter controls the ideal base current level. In modern devices, this recombination is almost always controlled by surface recombination at a nearby contact.
The present invention proposes the provision of a "virtual contact" to modify the gain of the parasitic bipolar transistor in CMOS devices by modifying the effective surface recombination rate at the source interface. Surface recombination can be defined as the recombination of free charge carriers in a semiconductor via electrically active centres (defects) at its surface. The term "a virtual contact" is used herein to denote a semiconductor surface that appears like a metallic contact to minority carriers, yet presents no significant electrical obstacle to majority carriers. Consider the following: The gain for a one-dimensional bipolar device is:
Figure imgf000006_0001
where Ns and w are the doping level and width, respectively, of the source, D is the bulk diffusion constant, and S is the effective surface recombination velocity. In order to limit the effects and/or occurrence of latch-up and other breakdown instabilities of a CMOS device, it is an object of the invention to control the gain of the parasitic bipolar devices present therein. Referring to Fig. 3 of the drawings, this is achieved, in accordance with the invention, by providing (by growing) a layer of semiconductor material over the source region of a MOS device, which layer 120 is formed of a material having a lower bandgap than that of the substrate material so as to provide a "virtual contact" to modify the gain of the parasitic bipolar transistor(s) in a CMOS device by modifying the effective surface recombination rate at the source interface. The source contact 122 may then be provided over the virtual contact layer 120, which acts as a sink for minority carriers (holes, in the case of an NMOS) device and, as a result, the base current of the respective parasitic bipolar transistor will be increased and the gain will drop.
A preferred material for the virtual contact 120, in the case where the substrate 104 is of silicon, is doped SiGe as a layer on the source contact 122. A Si/.^Ge^ alloy (where x denotes the relative Ge concentration in the alloy) is relatively easy and cheap to incorporate into existing standard Si processes, making it a good choice in this case. However, other materials are envisaged for use in the present invention, and the present invention is not necessarily strictly limited in this regard.
Si^Gex has the same lattice structure as Si, but its lattice constant increases as x increases, and the bandgap decreases as x increases.
The surface recombination velocity at the source interface can be controlled by the SiGe layer 120 according to the following relationship:
Figure imgf000006_0002
where t is the thickness of the SiGe layer, N is the doping level of this layer and the exponent is the change in band-gap due to SiGe relative to Si. It will be seen, therefore, that the difference in bandgap between the Si substrate and the layer of SiGe can be exploited to increase the surface recombination velocity (as Equation 2) and thereby decrease the current gain of the respective parasitic bipolar transistor (as Equation 1). The value of x can be controlled in respect of the SiGe layer in order to set the band-gap at the required value to achieve the desired current gain.
It will be appreciated that the virtual contact layer does not have to cover the whole of the contact surface/substrate interface. The minority carriers (holes, in an N-type device) injected into the source will go to the sink created by the virtual contact layer, even if the whole source is not covered by that layer.
It will be appreciated that the limiting case of infinite SE is that of a perfect metal contact, and the virtual contact layer (and particularly the SiGe alloy layer) can be used in a more controlled way to form a contact having similar properties. This is because SiGe alloy layers are typically formed by epitaxy, with near-perfect interfaces on the atomic scale. It should be noted that the above-mentioned embodiments illustrate rather than ■ limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:
1. A CMOS device comprising an n-channel MOS transistor and a p-channel MOS transistor on a semiconductor substrate, each MOS transistor comprising a gate electrode, a source region and a drain region, said source and drain regions being diffused within said semiconductor substrate, wherein a layer of semiconductor material is disposed over at least a portion of the source region of at least one of said MOS transistors said semiconductor material being such that said layer forms a sink for minority carriers at said source region.
2. A device according to claim 1, wherein said semiconductor material has a bandgap lower than that of said substrate.
3. A device according to claim 1, wherein the layer of semiconductor material is disposed between at least a portion of the source region of the substrate and a source contact.
4. A device according to claim 1, wherein the layer of semiconductor material comprises doped SiGe.
5. A device according to claim 1, wherein said layer of semiconductor material covers substantially all of the source region of the respective MOS transistor.
6. A device according to claim 1, wherein said layer of semiconductor material covers only one or more portions of said source region of the respective MOS transistor.
7. A method of manufacturing a CMOS device comprising an n-channel MOS transistor and a p-channel MOS transistor on a semiconductor substrate, the method comprising providing in respect of each MOS transistor a gate electrode, a source region and a drain region said source and drain regions being diffused within said semiconductor substrate, the method further comprising forming a layer of semiconductor material over at least a portion of the source region of at least one of said MOS transistors, said semiconductor material being selected such that said layer forms a sink for minority carriers at said source region.
8. A method according to claim 7, wherein said semiconductor material is selected to have a bandgap lower than that of said substrate.
9. A method according to claim 7, wherein said layer of semiconductor material comprises a Sii_xGex alloy, where x denotes the relative Ge concentration in the alloy.
10. A method according to claim 9, further comprising the step of selecting x accordingly to control the bandgap of said layer of semiconductor material.
11. An integrated circuit die including at least one CMOS device according to any one of claims 1 to 6.
12. An integrated circuit die including at least one CMOS device manufactured in accordance with the method of any one of claims 7 to 10.
PCT/IB2005/053308 2004-10-11 2005-10-10 Controlling parasitic bipolar gain in a cmos device WO2006040720A2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch
US5142641A (en) * 1988-03-23 1992-08-25 Fujitsu Limited CMOS structure for eliminating latch-up of parasitic thyristor
JPH0613561A (en) * 1992-06-25 1994-01-21 Seiko Epson Corp Semiconductor device and manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch
US5142641A (en) * 1988-03-23 1992-08-25 Fujitsu Limited CMOS structure for eliminating latch-up of parasitic thyristor
JPH0613561A (en) * 1992-06-25 1994-01-21 Seiko Epson Corp Semiconductor device and manufacture thereof

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* Cited by examiner, † Cited by third party
Title
KUMAR M J ET AL: "Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET" IEEE TRANSACTIONS ON RELIABILITY IEEE USA, vol. 51, no. 3, September 2002 (2002-09), pages 367-370, XP002370025 ISSN: 0018-9529 *
KUN-MING CHEN ET AL: "High-frequency characteristics of PMOS transistors with raised SiGe source/drain" 2001 IEEE TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS. DIGEST OF PAPERS (IEEE CAT. NO.01EX496), 2001, pages 92-95, XP002370024 PISCATAWAY, NJ, USA ISBN: 0-7803-7129-1 *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 213 (E-1538), 15 April 1994 (1994-04-15) -& JP 06 013561 A (SEIKO EPSON CORP), 21 January 1994 (1994-01-21) *
SIDEK R M ET AL: "Reduction of parasitic bipolar transistor action and punchthrough susceptibility in MOSFETs using Si/Si 1-x Ge x sources and drains" ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 32, no. 3, 1 February 1996 (1996-02-01), pages 269-270, XP006004699 ISSN: 0013-5194 *
SIM J-J ET AL: "ELIMINATION OF PARASITIC BIPOLAR-INDUCED BREAKDOWN EFFECTS IN ULTRA-THIN SOI MOSFET'S USING NARROW-BANDGAP-SOURCE (NBS) STRUCTURE" IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 42, no. 8, 1 August 1995 (1995-08-01), pages 1495-1502, XP000540983 PISACATAWAY, NJ, US ISSN: 0018-9383 *
WU Z Y ET AL: "Reverse heterojunction engineering: a novel technique for the suppression of the parasitic bipolar transistor in deep sub-micron MOSFETs" IEE COLLOQUIUM ON ADVANCED MOS AND BI-POLAR DEVICES, 14 FEB. 1995, LONDON, UK, 1995, pages 12-1, XP006528840 *
YOSHIMI M ET AL: "SUPPRESSION OF THE FLOATING-BODY EFFECT IN SOI MOSFET S BY THE BANDGAP ENGINEERING METHOD USING A SI1-XGEX SOURCE STRUCTURE" IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 44, no. 3, March 1997 (1997-03), pages 423-430, XP000688255 PISACATAWAY, NJ, US ISSN: 0018-9383 *

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