WO2006040682A3 - Process of and apparatus for encoding a digital input - Google Patents

Process of and apparatus for encoding a digital input Download PDF

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Publication number
WO2006040682A3
WO2006040682A3 PCT/IB2005/003371 IB2005003371W WO2006040682A3 WO 2006040682 A3 WO2006040682 A3 WO 2006040682A3 IB 2005003371 W IB2005003371 W IB 2005003371W WO 2006040682 A3 WO2006040682 A3 WO 2006040682A3
Authority
WO
WIPO (PCT)
Prior art keywords
type
operations
logical
inverse
cryptographic process
Prior art date
Application number
PCT/IB2005/003371
Other languages
French (fr)
Other versions
WO2006040682A2 (en
WO2006040682A9 (en
Inventor
Sean O'neil
Original Assignee
Synaptic Lab Ltd
Sean O'neil
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2004905897A external-priority patent/AU2004905897A0/en
Application filed by Synaptic Lab Ltd, Sean O'neil filed Critical Synaptic Lab Ltd
Publication of WO2006040682A2 publication Critical patent/WO2006040682A2/en
Publication of WO2006040682A9 publication Critical patent/WO2006040682A9/en
Publication of WO2006040682A3 publication Critical patent/WO2006040682A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation

Abstract

A cryptographic process (10) that receives input (11) and produces output (2). The cryptographic process (10) produces each block of output (20) by performing on a block of input (11), in any order, at least one operation (15) of a first type; at least one operation (19) of a second type; at least one operation (13, 17) of a third type; and at least one operation (12) of a fourth type. The operations of the first type (15) are swapping (SWAP) and bit order reversal. The operations of the second type (19) are bitwise rotation to the left (ROTL) and bitwise rotation to the right (ROTR). The operations of the third type (13, 17) are addition (ADD), subtraction (SUB) and negation (NEG). The operations of the fourth type (12) are exclusive-or (XOR), inverse exclusive-or (XNOR), logical AND, inverse logical AND (NAND), logical OR, inverse logical OR (NOR) and logical inverse (NOT). When both the first operation and the last operation in the cryptographic process (10) are swap operations (15), the cryptographic process includes a further swap operation (15).
PCT/IB2005/003371 2004-10-13 2005-10-12 Process of and apparatus for encoding a digital input WO2006040682A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AU2004905897 2004-10-13
AU2004905897A AU2004905897A0 (en) 2004-10-13 Process of and apparatus for encoding a digital input

Publications (3)

Publication Number Publication Date
WO2006040682A2 WO2006040682A2 (en) 2006-04-20
WO2006040682A9 WO2006040682A9 (en) 2006-06-08
WO2006040682A3 true WO2006040682A3 (en) 2006-07-27

Family

ID=36118193

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/003371 WO2006040682A2 (en) 2004-10-13 2005-10-12 Process of and apparatus for encoding a digital input

Country Status (2)

Country Link
TW (1) TW200637317A (en)
WO (1) WO2006040682A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9128698B2 (en) * 2012-09-28 2015-09-08 Intel Corporation Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999066669A2 (en) * 1998-06-15 1999-12-23 Rsa Security, Inc. Block ciphers with integer multiplication, data-dependent and fixed number of rotations in each round
WO2000075750A2 (en) * 1999-06-09 2000-12-14 Microsoft Corporation Parameter generation using elementary register operations
US6199162B1 (en) * 1997-09-17 2001-03-06 Frank C. Luyster Block cipher method
US20020114451A1 (en) * 2000-07-06 2002-08-22 Richard Satterfield Variable width block cipher

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6199162B1 (en) * 1997-09-17 2001-03-06 Frank C. Luyster Block cipher method
WO1999066669A2 (en) * 1998-06-15 1999-12-23 Rsa Security, Inc. Block ciphers with integer multiplication, data-dependent and fixed number of rotations in each round
WO2000075750A2 (en) * 1999-06-09 2000-12-14 Microsoft Corporation Parameter generation using elementary register operations
US20020114451A1 (en) * 2000-07-06 2002-08-22 Richard Satterfield Variable width block cipher

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
VERBAUWHEDE I ET AL: "SECURITY AND PERFORMANCE OPTIMIZATION OF A NEW DES DATA ENCRYPTION CHIP", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 23, no. 3, 1 June 1988 (1988-06-01), pages 647 - 656, XP000112776, ISSN: 0018-9200 *

Also Published As

Publication number Publication date
WO2006040682A2 (en) 2006-04-20
WO2006040682A9 (en) 2006-06-08
TW200637317A (en) 2006-10-16

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