WO2006040165A2 - Method for production of charge-trapping memory cells - Google Patents

Method for production of charge-trapping memory cells Download PDF

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Publication number
WO2006040165A2
WO2006040165A2 PCT/EP2005/011039 EP2005011039W WO2006040165A2 WO 2006040165 A2 WO2006040165 A2 WO 2006040165A2 EP 2005011039 W EP2005011039 W EP 2005011039W WO 2006040165 A2 WO2006040165 A2 WO 2006040165A2
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WO
WIPO (PCT)
Prior art keywords
layer
source
oxide
silicon
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2005/011039
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French (fr)
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WO2006040165A3 (en
Inventor
Martin Verhoeven
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of WO2006040165A3 publication Critical patent/WO2006040165A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Definitions

  • the invention concerns the fabrication of charge-trapping memory cells comprising an oxide-nitride-oxide memory layer sequence and being intended to store two bits of information.
  • Non-volatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materi ⁇ als with a memory layer between confinement layers of dielec ⁇ tric material having a larger energy band gap than the memory layer.
  • the memory layer sequence is arranged between a chan ⁇ nel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied elec ⁇ tric voltage.
  • Charge carriers moving from source to a drain through the channel region are accelerated and gain enough energy to be able to penetrate the lower confinement layer and to be trapped within the memory layer.
  • the trapped charge carriers change the threshold voltage of the cell transistor structure.
  • Different programming states can be read by apply ⁇ ing the appropriate reading voltages.
  • charge- trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon.
  • Typical applications of memory products require a steady miniaturization of the memory cells.
  • a reduction of the area that is required by an individual memory cell can be obtained by shrinking the cell structure or by an increase of the num ⁇ ber of bits that can be stored within one memory cell tran ⁇ sistor structure.
  • the oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers.
  • the oxide layers are specified to have a thickness of more than 5 nm. Two bits of informa ⁇ tion can be stored in every memory cell.
  • the method according to this invention comprises the steps of applying an oxide layer, a nitride layer, and a layer of amorphous silicon onto a main surface of a semiconductor sub ⁇ strate, applying a resist mask with openings and performing an implantation of doping atoms to form doped regions of source and drain.
  • the layer of amorphous silicon is provided with a dopant in areas lo- cated above the regions of source and drain.
  • the resist mask and parts of the silicon layer that have not been implanted are subsequently removed and the remaining parts of the sili ⁇ con layer are used as a silicon mask in further process steps.
  • the nitride layer beneath the layer of amorphous sili ⁇ con is partly etched back in the areas that are not covered by the silicon. Then, the silicon layer is removed and the nitride is oxidized until only parts of the nitride layer re ⁇ main within areas above the source and drain regions. In this manner, oxide-nitride-oxide memory layer sequences are formed that are laterally restricted to the areas of source and drain and formed in self-aligned fashion with respect to the source and drain regions.
  • a preferred alternative comprises a further method step, by which the resist mask is laterally reduced or trimmed between the implantation steps to form the source and drain regions and to form the doped regions within the amorphous silicon layer so that the produced ONO layer slightly extends over the lateral boundaries of the source and drain regions .
  • Figure Ia shows a cross-section of a first intermediate prod ⁇ uct of an example of the inventive method after the applica ⁇ tion of the amorphous silicon layer and resist mask.
  • Figure Ib shows the cross-section according to figure Ia af ⁇ ter the implantation steps.
  • Figure Ic shows the cross-section according to figure Ib af ⁇ ter the removal of the resist mask and non-implanted parts of the silicon layer.
  • Figure Id shows the cross-section of figure Ic after the etching of the nitride layer.
  • Figure Ie shows the cross-section according to figure Id af ⁇ ter an oxidation step.
  • Figure If shows the cross-section of figure Ie after the ap ⁇ plication of the gate conductor.
  • Figure 2a shows a cross-section according to figure Ia.
  • Figure 2b shows the cross-section according to figure 2a af ⁇ ter the implantation of the source and drain regions.
  • Figure 2c shows the cross-section of figure 2b after a pull- back step to widen the openings in the resist mask.
  • Figure 2d shows the cross-section according to figure 2c af ⁇ ter a further implantation step.
  • Figure 2e shows the cross-section of figure 2d after the re ⁇ moval of the resist mask and non-implanted regions of the silicon layer.
  • Figure 2f shows the cross-section of figure 2e after an etch ⁇ ing of the nitride layer.
  • Figure 2g shows the cross-section according to figure 2f af ⁇ ter an oxidation step.
  • Figure 2h shows the cross-section according to figure 2g af ⁇ ter the application of the gate conductor.
  • a substrate 1 of semiconductor material preferably silicon
  • a layer sequence comprising an oxide layer 2 that is ap ⁇ plied on a main surface of the substrate, a nitride layer 3 and a layer of amorphous silicon 4.
  • a resist mask 5 is ap ⁇ plied, which has openings in the areas of the regions of source and drain to be formed by a subsequent implantation step.
  • Figure 1 "Ib shows the cross-section of the intermediate product according to figure Ia after the performance of two implanta ⁇ tion steps. This is indicated in figure Ib by the arrows pointing downwards into the regions in which a dopant is im ⁇ planted to form doped regions.
  • a deep implantation forms the regions of source and drain 6.
  • a shallow implantation forms doped regions within the layer of amorphous silicon 4 in ar ⁇ eas that are located above the source/drain regions 6.
  • the sequence of implantation steps is not fixed / it is preferred to perform the deep implantation first and the shallow im ⁇ plantation afterwards .
  • Figure Ic shows a further intermediate product in a cross- section according to figure Ib after the removal of the re ⁇ sist mask 5 and of those parts of the amorphous silicon layer which have not been implanted.
  • Figure Id shows the cross-section according to figure Ic for a subsequent etching step, indicated by the arrows in figure Id, by which the nitride layer 3 is partly removed in a ver ⁇ tical direction.
  • the silicon mask 7 is applied to restrict the etching to areas between the source/drain regions 6. Above the source/drain regions 6, the nitride layer 3 remains in its original thickness.
  • Figure Ie shows a further intermediate product after the re ⁇ moval of the silicon mask 7 and an oxidation step to form a second oxide layer 8.
  • This second oxide layer 8 comprises the original oxide layer 2 and parts of the nitride layer 3 which are completely converted into oxide, thus forming the second oxide layer 8..
  • the thickness of the nitride layer 3 and the depth of the etching step shown in figure Id are adapted so that the oxidation step forms a thorough oxide layer 8 in the areas between the source/drain regions 6, while thin remain ⁇ ing layer parts of the nitride layer 3 are left above the source s /drain regions 6.
  • an oxide-nitride-oxide layer ⁇ sequence is formed above the source/drain regions 6 in a self-aligned manner with respect to the source/drain re ⁇ gions 6.
  • the memory layer sequence can be arranged ex ⁇ actly above the source and drain regions and completely in ⁇ terrupted above the channel region provided between source and drain.
  • Figure If shows the cross-section according to figure Ie af ⁇ ter the application of a gate conductor 9 to form gate elec ⁇ trodes above the channel regions and wordlines to connect the gate electrodes along rows of memory cell arrays.
  • Figures 2a to 2h show cross-sections of intermediate products of an alternative of the inventive method, which is espe ⁇ cially preferred. It may be desired to have memory layer se ⁇ quences above the pn junctions of the source and drain re ⁇ gions adjacent to the channel. This can be accomplished by the following method, which comprises an additional method step between the two implantation procedures.
  • Figure 2a shows the cross-section according to figure Ia, showing that the point of departure is the same as in the general method.
  • Figure 2b shows the subsequent implantation step to form the source/drain regions 6.
  • This alternative embodiment comprises a further method step after the deep implantation indicated in figure 2b.
  • Figure 2c shows this further method step, which is a pull- back step to widen the. openings of the resist mask 5. This is indicated in figure 2c by the arrows in the form of triangles and the broken lines representing the original contours of the resist mask 5.
  • the larger openings, which are produced in this way, define the area of the later oxide-nitride-oxide layer sequence, which is intended as storage means.
  • Figure 2d shows the cross-section according to figure 2c for the further implantation step, by which those regions of the amorphous silicon layer 4 are doped which are left free by the widened openings of the resist mask 5.
  • These doped re ⁇ gions are self-aligned to the source/drain regions 6 at least as far as the pull-back step according to figure 2c can be controlled, but slightly extend over the lateral boundaries of the source/drain regions.
  • Figure 2e shows the cross-section of figure 2d after the re ⁇ moval of the resist mask 5 and the undoped regions of the layer 4 of amorphous silicon.
  • a silicon mask 7 is formed, which has slightly smaller openings as compared to the silicon mask 7 which is applied in the first embodiment of the method described above.
  • Figure 2f shows the cross-section according to figure 2e for the subsequent etching step, by which those parts of the ni ⁇ tride layer 3 which are not covered by the silicon mask 7 are removed to a certain predefined depth.
  • Figure 2g shows the cross-section according to figure 2f af ⁇ ter the removal of the silicon mask 7 and the performance of an oxidation step to form the second oxide layer 8 according to the first embodiment of the method.
  • a comparison between figures 2g and Ie shows the difference in the lateral exten ⁇ sion of the formed ONO layer.
  • Figure 2h shows the cross-section of the product that is ob ⁇ tained after the application of the gate conductor 9. Further standard process steps which are known per se can follow to complete this device.

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  • Semiconductor Memories (AREA)

Abstract

An oxide layer (2), a nitride layer (3), and a layer of amorphous silicon (4) are applied to a surface of a semiconductor substrate (1). A resist mask (5) is applied and implantations are performed to form doped regions (6) of source and drain and doped regions within the amorphous silicon layer. The resist mask and undoped parts of the amorphous silicon are removed to form a silicon mask (7). The silicon mask is applied to etch back the nitride layer (3). After a removal of the silicon mask (7), the nitride (3) is oxidized to form an oxide-nitride-oxide layer sequence which is laterally restricted to the area above the source/drain regions (6).

Description

Description
Method for production of charge-trapping memory cells
Technical field
The invention concerns the fabrication of charge-trapping memory cells comprising an oxide-nitride-oxide memory layer sequence and being intended to store two bits of information.
Background of the invention
Non-volatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materi¬ als with a memory layer between confinement layers of dielec¬ tric material having a larger energy band gap than the memory layer. The memory layer sequence is arranged between a chan¬ nel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied elec¬ tric voltage. Charge carriers moving from source to a drain through the channel region are accelerated and gain enough energy to be able to penetrate the lower confinement layer and to be trapped within the memory layer. The trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by apply¬ ing the appropriate reading voltages. Examples of charge- trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon. Typical applications of memory products require a steady miniaturization of the memory cells. A reduction of the area that is required by an individual memory cell can be obtained by shrinking the cell structure or by an increase of the num¬ ber of bits that can be stored within one memory cell tran¬ sistor structure.
A publication by B. Eitan et al., "NROM: a Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" in IEEE Electron De¬ vice Letters, volume 21, pages 543 to 545 (2000), describes a charge-trapping memory cell with a memory layer sequence of oxide, nitride and oxide which is especially adapted to be operated with a reading voltage that is reverse to the pro¬ gramming voltage (reverse read) . The oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers. The oxide layers are specified to have a thickness of more than 5 nm. Two bits of informa¬ tion can be stored in every memory cell.
In order to provide a better two-bit separation in charge- trapping memory cells, several different structures of an ar¬ rangement of separate memory layers of dielectric 'material or floating gate electrodes at both Bides of the gate electrode above the source and drain junctions at the channel ends have been proposed. During the write operation to program the mem¬ ory cell, channel-hot electrons are injected predominantly in the ONO area just above the pn-junction at the tdrain. A re¬ versal of the electric voltage between source and drain en¬ ables the storage of a second bit at the other channel end.
In the course of further miniaturization of the memory cell, the problem of a precise arrangement and localization of the memory layer with respect to the gate electrode and the re¬ gions of source and drain is of increasing importance. The further shrinking of the cell dimensions will imply a greater difficulty to separate the two bits that are stored in the same memory cell. This derives from the fact that electrons are to some extent injected also in the area between the re¬ gions of source and drain. Therefore, memory layer structures have been proposed, in which the memory layer is interrupted above the channel region.
Summary of the invention
It is an object of the present invention to provide an im¬ proved fabrication method for charge-trapping memory cells that are intended for two-bit storage.
It is a further object of the invention to provide a method for the fabrication of charge-trapping memory cells with, im¬ proved two-bit separation that is suitable for a shrinkage of the device structures.
It is still a further object of"this invention to provide the aforementioned methods with standard process steps of semi¬ conductor technology.
The method according to this invention comprises the steps of applying an oxide layer, a nitride layer, and a layer of amorphous silicon onto a main surface of a semiconductor sub¬ strate, applying a resist mask with openings and performing an implantation of doping atoms to form doped regions of source and drain. By a further implantation step, the layer of amorphous silicon is provided with a dopant in areas lo- cated above the regions of source and drain. The resist mask and parts of the silicon layer that have not been implanted are subsequently removed and the remaining parts of the sili¬ con layer are used as a silicon mask in further process steps. The nitride layer beneath the layer of amorphous sili¬ con is partly etched back in the areas that are not covered by the silicon. Then, the silicon layer is removed and the nitride is oxidized until only parts of the nitride layer re¬ main within areas above the source and drain regions. In this manner, oxide-nitride-oxide memory layer sequences are formed that are laterally restricted to the areas of source and drain and formed in self-aligned fashion with respect to the source and drain regions.
A preferred alternative comprises a further method step, by which the resist mask is laterally reduced or trimmed between the implantation steps to form the source and drain regions and to form the doped regions within the amorphous silicon layer so that the produced ONO layer slightly extends over the lateral boundaries of the source and drain regions .
These and other objects, features and advantages of the in¬ vention will become apparent from the following brief de¬ scription of the drawings, detailed description and appended claims and drawings.
Brief description of the drawings
Figure Ia shows a cross-section of a first intermediate prod¬ uct of an example of the inventive method after the applica¬ tion of the amorphous silicon layer and resist mask. Figure Ib shows the cross-section according to figure Ia af¬ ter the implantation steps.
Figure Ic shows the cross-section according to figure Ib af¬ ter the removal of the resist mask and non-implanted parts of the silicon layer.
Figure Id shows the cross-section of figure Ic after the etching of the nitride layer.
Figure Ie shows the cross-section according to figure Id af¬ ter an oxidation step.
Figure If shows the cross-section of figure Ie after the ap¬ plication of the gate conductor.
Figure 2a shows a cross-section according to figure Ia.
Figure 2b shows the cross-section according to figure 2a af¬ ter the implantation of the source and drain regions.
Figure 2c shows the cross-section of figure 2b after a pull- back step to widen the openings in the resist mask.
Figure 2d shows the cross-section according to figure 2c af¬ ter a further implantation step.
Figure 2e shows the cross-section of figure 2d after the re¬ moval of the resist mask and non-implanted regions of the silicon layer.
Figure 2f shows the cross-section of figure 2e after an etch¬ ing of the nitride layer. Figure 2g shows the cross-section according to figure 2f af¬ ter an oxidation step.
Figure 2h shows the cross-section according to figure 2g af¬ ter the application of the gate conductor.
Detailed description
The general method according to this invention is first de¬ scribed with reference to figures Ia to If, which show dif¬ ferent intermediate products of an example of the method. Ac¬ cording to the cross-section shown in figure Ia, a substrate 1 of semiconductor material, preferably silicon, is provided with a layer sequence comprising an oxide layer 2 that is ap¬ plied on a main surface of the substrate, a nitride layer 3 and a layer of amorphous silicon 4. A resist mask 5 is ap¬ plied, which has openings in the areas of the regions of source and drain to be formed by a subsequent implantation step.
Figure1"Ib shows the cross-section of the intermediate product according to figure Ia after the performance of two implanta¬ tion steps. This is indicated in figure Ib by the arrows pointing downwards into the regions in which a dopant is im¬ planted to form doped regions. A deep implantation forms the regions of source and drain 6. A shallow implantation forms doped regions within the layer of amorphous silicon 4 in ar¬ eas that are located above the source/drain regions 6. The sequence of implantation steps is not fixed/ it is preferred to perform the deep implantation first and the shallow im¬ plantation afterwards . Figure Ic shows a further intermediate product in a cross- section according to figure Ib after the removal of the re¬ sist mask 5 and of those parts of the amorphous silicon layer which have not been implanted. The remaining parts of the silicon layer 4, which are doped, form a silicon mask 7 above the areas of the source/drain regions 6.
Figure Id shows the cross-section according to figure Ic for a subsequent etching step, indicated by the arrows in figure Id, by which the nitride layer 3 is partly removed in a ver¬ tical direction. The silicon mask 7 is applied to restrict the etching to areas between the source/drain regions 6. Above the source/drain regions 6, the nitride layer 3 remains in its original thickness.
Figure Ie shows a further intermediate product after the re¬ moval of the silicon mask 7 and an oxidation step to form a second oxide layer 8. This second oxide layer 8 comprises the original oxide layer 2 and parts of the nitride layer 3 which are completely converted into oxide, thus forming the second oxide layer 8.. The thickness of the nitride layer 3 and the depth of the etching step shown in figure Id are adapted so that the oxidation step forms a thorough oxide layer 8 in the areas between the source/drain regions 6, while thin remain¬ ing layer parts of the nitride layer 3 are left above the sources/drain regions 6. In this way, an oxide-nitride-oxide layer ^sequence is formed above the source/drain regions 6 in a self-aligned manner with respect to the source/drain re¬ gions 6. Thus, the memory layer sequence can be arranged ex¬ actly above the source and drain regions and completely in¬ terrupted above the channel region provided between source and drain. Figure If shows the cross-section according to figure Ie af¬ ter the application of a gate conductor 9 to form gate elec¬ trodes above the channel regions and wordlines to connect the gate electrodes along rows of memory cell arrays.
Figures 2a to 2h show cross-sections of intermediate products of an alternative of the inventive method, which is espe¬ cially preferred. It may be desired to have memory layer se¬ quences above the pn junctions of the source and drain re¬ gions adjacent to the channel. This can be accomplished by the following method, which comprises an additional method step between the two implantation procedures.
Figure 2a shows the cross-section according to figure Ia, showing that the point of departure is the same as in the general method.
Figure 2b shows the subsequent implantation step to form the source/drain regions 6. This alternative embodiment comprises a further method step after the deep implantation indicated in figure 2b.
Figure 2c shows this further method step, which is a pull- back step to widen the. openings of the resist mask 5. This is indicated in figure 2c by the arrows in the form of triangles and the broken lines representing the original contours of the resist mask 5. The larger openings, which are produced in this way, define the area of the later oxide-nitride-oxide layer sequence, which is intended as storage means.
Figure 2d shows the cross-section according to figure 2c for the further implantation step, by which those regions of the amorphous silicon layer 4 are doped which are left free by the widened openings of the resist mask 5. These doped re¬ gions are self-aligned to the source/drain regions 6 at least as far as the pull-back step according to figure 2c can be controlled, but slightly extend over the lateral boundaries of the source/drain regions.
Figure 2e shows the cross-section of figure 2d after the re¬ moval of the resist mask 5 and the undoped regions of the layer 4 of amorphous silicon. In this way, a silicon mask 7 is formed, which has slightly smaller openings as compared to the silicon mask 7 which is applied in the first embodiment of the method described above.
Figure 2f shows the cross-section according to figure 2e for the subsequent etching step, by which those parts of the ni¬ tride layer 3 which are not covered by the silicon mask 7 are removed to a certain predefined depth.
Figure 2g shows the cross-section according to figure 2f af¬ ter the removal of the silicon mask 7 and the performance of an oxidation step to form the second oxide layer 8 according to the first embodiment of the method. A comparison between figures 2g and Ie shows the difference in the lateral exten¬ sion of the formed ONO layer.
Figure 2h shows the cross-section of the product that is ob¬ tained after the application of the gate conductor 9. Further standard process steps which are known per se can follow to complete this device.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims .
List of reference numerals
1 substrate
2 oxide layer
3 nitride layer
4 layer of amorphous silicon
5 resist mask
6 source/drain region
7 silicon mask
8 second oxide layer
9 gate conductor

Claims

We claim:
1. Method for production of charge-trapping memory cells with separate memory layers for two-bit separation, comprising: providing a semiconductor substrate; applying an oxide layer on said substrate; applying a nitride layer on said oxide layer; applying a layer of amorphous silicon on said nitride layer; applying a resist mask with openings on said layer of amor¬ phous silicon; applying said resist mask in a subsequent implantation to form doped regions of source and drain and to provide said layer of amorphous silicon with doped regions that are lo¬ cated above said doped regions of source and drain; removing said resist mask; removing part of said layer of amorphous silicon that has not been provided with a doping, to form a silicon mask; applying said silicon mask to etch back said nitride layer; removing said silicon mask; performing an oxidation to convert all of said nitride layer into oxide, except for parts of said nitride layer that are located in areas above said doped regions of source and drain, thus forming an oxide-nitride-oxide layer sequence above these areas; and applying a gate conductor provided as gate-electrode and wordline.
2. Method according to claim 1, further comprising: widening the openings of said resist mask after the formation of said doped regions of source and drain and before the for¬ mation of said doped regions in said layer of amorphous sili¬ con.
3. Method according to claim 1 or 2, further comprising: providing the layers within said oxide-nitride-oxide layer sequence with thicknesses that are suitable for a storage by charge trapping.
PCT/EP2005/011039 2004-10-15 2005-10-13 Method for production of charge-trapping memory cells Ceased WO2006040165A2 (en)

Applications Claiming Priority (2)

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Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US5434109A (en) * 1993-04-27 1995-07-18 International Business Machines Corporation Oxidation of silicon nitride in semiconductor devices
JP3078720B2 (en) * 1994-11-02 2000-08-21 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US6720627B1 (en) * 1995-10-04 2004-04-13 Sharp Kabushiki Kaisha Semiconductor device having junction depths for reducing short channel effect
JP3146962B2 (en) * 1995-12-14 2001-03-19 日本電気株式会社 Semiconductor storage device and method of manufacturing the same
JPH11297863A (en) * 1998-04-10 1999-10-29 Nec Corp Non-volatile memory having contactless array configuration and method of manufacturing the same
FR2819633B1 (en) * 2001-01-18 2003-05-30 St Microelectronics Sa METHOD FOR INTEGRATING A DRAM MEMORY
JP3930256B2 (en) * 2001-02-07 2007-06-13 スパンション エルエルシー Semiconductor device and manufacturing method thereof
US6538292B2 (en) * 2001-03-29 2003-03-25 Macronix International Co. Ltd. Twin bit cell flash memory device
US6503845B1 (en) * 2001-05-01 2003-01-07 Applied Materials Inc. Method of etching a tantalum nitride layer in a high density plasma
US6440797B1 (en) * 2001-09-28 2002-08-27 Advanced Micro Devices, Inc. Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory
US6828199B2 (en) * 2001-12-20 2004-12-07 Advanced Micro Devices, Ltd. Monos device having buried metal silicide bit line
US7105899B2 (en) * 2002-01-17 2006-09-12 Micron Technology, Inc. Transistor structure having reduced transistor leakage attributes
JP3745297B2 (en) * 2002-03-27 2006-02-15 Ｎｅｃエレクトロニクス株式会社 Method for manufacturing nonvolatile semiconductor memory device
KR100480645B1 (en) * 2003-04-01 2005-03-31 삼성전자주식회사 Method for manufacturing SONOS memory device with twin-ONO by reverse self-aligning process
JP3976703B2 (en) * 2003-04-30 2007-09-19 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
US6979613B1 (en) * 2003-11-16 2005-12-27 Nanya Technology Corp. Method for fabricating a trench capacitor of DRAM

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DE102004052910B4 (en) 2006-07-20
WO2006040165A3 (en) 2006-06-08
US20060084268A1 (en) 2006-04-20

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