WO2006028159A3 - Reconfigurable circuit-containing electronic device - Google Patents

Reconfigurable circuit-containing electronic device Download PDF

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Publication number
WO2006028159A3
WO2006028159A3 PCT/JP2005/016478 JP2005016478W WO2006028159A3 WO 2006028159 A3 WO2006028159 A3 WO 2006028159A3 JP 2005016478 W JP2005016478 W JP 2005016478W WO 2006028159 A3 WO2006028159 A3 WO 2006028159A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic circuit
operable
unit
electronic device
circuit
Prior art date
Application number
PCT/JP2005/016478
Other languages
French (fr)
Other versions
WO2006028159A2 (en
Inventor
Yoshiteru Tanaka
Original Assignee
Matsushita Electric Ind Co Ltd
Yoshiteru Tanaka
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd, Yoshiteru Tanaka filed Critical Matsushita Electric Ind Co Ltd
Publication of WO2006028159A2 publication Critical patent/WO2006028159A2/en
Publication of WO2006028159A3 publication Critical patent/WO2006028159A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Abstract

A reconfigurable circuit-containing electronic device including a reconfigurable logic circuit unit (21) operable to reconfigure a logic circuit, a calculation unit (22) operable to calculate a value of permissible electrical power for the reconfigurable logic circuit unit (21), a determination unit (23) operable to determine a circuit specification in accordance with the value of the permissible electrical power and a predetermined initial restriction (25), in which the circuit specification is used to reconfigure the logic circuit in the reconfigurable logic circuit unit (21), and a reconfiguration unit (24) operable to reconfigure the logic circuit in the reconfigurable logic circuit unit (21) in accordance with the circuit specification. The above electronic device is operable to accommodate posterior changes in standard and specification.
PCT/JP2005/016478 2004-09-08 2005-09-01 Reconfigurable circuit-containing electronic device WO2006028159A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004-260735 2004-09-08
JP2004260735 2004-09-08

Publications (2)

Publication Number Publication Date
WO2006028159A2 WO2006028159A2 (en) 2006-03-16
WO2006028159A3 true WO2006028159A3 (en) 2006-11-09

Family

ID=35789107

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/016478 WO2006028159A2 (en) 2004-09-08 2005-09-01 Reconfigurable circuit-containing electronic device

Country Status (1)

Country Link
WO (1) WO2006028159A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6086629A (en) * 1997-12-04 2000-07-11 Xilinx, Inc. Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers
US6086628A (en) * 1998-02-17 2000-07-11 Lucent Technologies Inc. Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6086629A (en) * 1997-12-04 2000-07-11 Xilinx, Inc. Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers
US6086628A (en) * 1998-02-17 2000-07-11 Lucent Technologies Inc. Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BHARAT P DAVE ET AL: "COHRA: Hardware-Software Cosynthesis of Hierarchical Heterogeneous Distributed Embedded Systems", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 17, no. 10, October 1998 (1998-10-01), pages 900 - 919, XP011007607, ISSN: 0278-0070 *
PO-XUN CHIN ET AL: "Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint", ISCAS 2001. PROCEEDINGS OF THE 2001 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. SYDNEY, AUSTRALIA, MAY 6 - 9, 2001, IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, NEW YORK, NY : IEEE, US, vol. VOL. 1 OF 5, 6 May 2001 (2001-05-06), pages 519 - 522, XP010542146, ISBN: 0-7803-6685-9 *

Also Published As

Publication number Publication date
WO2006028159A2 (en) 2006-03-16

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