WO2006023696A2 - Integrated circuit packaging using electrochemically fabricated - Google Patents
Integrated circuit packaging using electrochemically fabricated Download PDFInfo
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- WO2006023696A2 WO2006023696A2 PCT/US2005/029494 US2005029494W WO2006023696A2 WO 2006023696 A2 WO2006023696 A2 WO 2006023696A2 US 2005029494 W US2005029494 W US 2005029494W WO 2006023696 A2 WO2006023696 A2 WO 2006023696A2
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1605—Process or apparatus coating on selected surface areas by masking
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
- C23C18/1651—Two or more layers only obtained by electroless plating
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D1/00—Electroforming
- C25D1/003—3D structures, e.g. superposed patterned layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H01L2924/30—Technical effects
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates generally to the field of Electrochemical Fabrication and the associated formation of three-dimensional structures (e.g. microscale or mesoscale structures).
- it relates to electrochemical fabrication methods for fabricating packages for Integrated Circuits where at least a portion of the package is formed using electrochemical fabrication techniques.
- a technique for forming three-dimensional structures (e.g. parts, components, devices, and the like) from a plurality of adhered layers was invented by Adam L. Cohen and is known as Electrochemical Fabrication. It is being commercially pursued by Microfabrica Inc. (formerly MEMGen® Corporation) of Burbank, California under the name EFABTM. This technique was described in US Patent No. 6,027,630, issued on February 22, 2000.
- This electrochemical deposition technique allows the selective deposition of a material using a unique masking technique that involves the use of a mask that includes patterned conformable material on a support structure that is independent of the substrate onto which plating will occur.
- the conformable portion of the mask When desiring to perform an electrodeposition using the mask, the conformable portion of the mask is brought into contact with a substrate while in the presence of a plating solution such that the contact of the conformable portion of the mask to the substrate inhibits deposition at selected locations.
- these masks might be generically called conformable contact masks; the masking technique may be generically called a conformable contact mask plating process. More specifically, in the terminology of Microfabrica Inc. (formerly MEMGen® Corporation) of Burbank, California such masks have come to be known as INSTANT MASKSTM and the process known as INSTANT MASKINGTM or INSTANT MASKTM plating.
- the electrochemical deposition process may be carried out in a number of different ways as set forth in the above patent and publications. In one form, this process involves the execution of three separate operations during the formation of each layer of the structure that is to be formed:
- one or more additional layers may be formed adjacent to the immediately preceding layer and adhered to the smoothed surface of that preceding layer. These additional layers are formed by repeating the first through third operations one or more times wherein the formation of each subsequent layer treats the previously formed layers and the initial substrate as a new and thickening substrate.
- At least a portion of at least one of the materials deposited is generally removed by an etching process to expose or release the three-dimensional structure that was intended to be formed.
- the preferred method of performing the selective electrodeposition involved in the first operation is by conformable contact mask plating.
- one or more conformable contact (CC) masks are first formed.
- the CC masks include a support structure onto which a patterned conformable dielectric material is adhered or formed.
- the conformable material for each mask is shaped in accordance with a particular cross-section of material to be plated. At least one CC mask is needed for each unique cross-sectional pattern that is to be plated.
- the support for a CC mask is typically a plate-like structure formed of a metal that is to be selectively electroplated and from which material to be plated will be dissolved.
- the support will act as an anode in an electroplating process.
- the support may instead be a porous or otherwise perforated material through which deposition material will pass during an electroplating operation on its way from a distal anode to a deposition surface.
- the entire structure is referred to as the CC mask while the individual plating masks may be referred to as "submasks".
- the individual plating masks may be referred to as "submasks".
- the conformable portion of the CC mask is placed in registration with and pressed against a selected portion of the substrate (or onto a previously formed layer or onto a previously deposited portion of a layer) on which deposition is to occur.
- the pressing together of the CC mask and substrate occur in such a way that all openings, in the conformable portions of the CC mask contain plating solution.
- the conformable material of the CC mask that contacts the substrate acts as a barrier to electrodeposition while the openings in the CC mask that are filled with electroplating solution act as pathways for transferring material from an anode (e.g. the CC mask support) to the non-contacted portions of the substrate (which act as a cathode during the plating operation) when an appropriate potential and/or current are supplied.
- FIGS. 1 A - 1 C An example of a CC mask and CC mask plating are shown in FIGS. 1 A - 1 C.
- FIG. 1 A shows a side view of a CC mask 8 consisting of a conformable or deformable (e.g. elastomeric) insulator 10 patterned on an anode 12.
- the anode has two functions.
- FIG. 1 A also depicts a substrate 6 separated from mask 8.
- One is as a supporting material for the patterned insulator 10 to maintain its integrity and alignment since the pattern may be topological ⁇ complex (e.g., involving isolated "islands" of insulator material).
- the other function is as an anode for the electroplating operation.
- CC mask plating selectively deposits material 22 onto a substrate 6 by simply pressing the insulator against the substrate then electrodepositing material through apertures 26a and 26b in the insulator as shown in FIG. 1 B. After deposition, the CC mask is separated, preferably non-destructively, from the substrate 6 as shown in FIG. 1 C.
- the CC mask plating process is distinct from a "through-mask" plating process in that in a through-mask plating process the separation of the masking material from the substrate would occur destructively. As with through-mask plating, CC mask plating deposits material selectively and simultaneously over the entire layer.
- the plated region may consist of one or more isolated plating regions where these isolated plating regions may belong to a single structure that is being formed or may belong to multiple structures that are being formed simultaneously.
- CC mask plating as individual masks are not intentionally destroyed in the removal process, they may be usable in multiple plating operations.
- FIGS. 1 D - 1 F Another example of a CC mask and CC mask plating is shown in FIGS. 1 D - 1 F.
- FIG. 1 D shows an anode 12' separated from a mask 8' that includes a patterned conformable material 10' and a support structure 20.
- FIG. 1 D also depicts substrate 6 separated from the mask 8'.
- FIG. 1 E illustrates the mask 8' being brought into contact with the substrate 6.
- FIG. 1 F illustrates the deposit 22' that results from conducting a current from the anode 12' to the substrate 6.
- FIG. 1 G illustrates the deposit 22' on substrate 6 after separation from mask 8'.
- an appropriate electrolyte is located between the substrate 6 and the anode 12' and a current of ions coming from one or both of the solution and the anode are conducted through the opening in the mask to the substrate where material is deposited.
- This type of mask may be referred to as an anodeless INSTANT MASKTM (AIM) or as an anodeless conformable contact (ACC) mask.
- CC mask plating allows CC masks to be formed completely separate from the fabrication of the substrate on which plating is to occur (e.g. separate from a three-dimensional (3D) structure that is being formed).
- CC masks may be formed in a variety of ways, for example, a photolithographic process may be used. All masks can be generated simultaneously, prior to structure fabrication rather than during it. This separation makes possible a simple, low-cost, automated, self-contained, and internally-clean "desktop factory" that can be installed almost anywhere to fabricate 3D structures, leaving any required clean room processes, such as photolithography to be performed by service bureaus or the like.
- FIGS. 2A - 2F An example of the electrochemical fabrication process discussed above is illustrated in FIGS. 2A - 2F. These figures show that the process involves deposition of a first material 2 which is a sacrificial material and a second material 4 which is a structural material.
- the CC mask 8 in this example, includes a patterned conformable material (e.g. an elastomeric dielectric material) 10 and a support 12 which is made from deposition material 2.
- the conformal portion of the CC mask is pressed against substrate 6 with a plating solution 14 located within the openings 16 in the conformable material 10.
- An electric current, from power supply 18, is then passed through the plating solution 14 via (a) support 12 which doubles as an anode and (b) substrate 6 which doubles as a cathode.
- FIG. 2A illustrates that the passing of current causes material 2 within the plating solution and material 2 from the anode 12 to be selectively transferred to and plated on the cathode 6.
- the CC mask 8 is removed as shown in FIG. 2B.
- FIG. 2C depicts the second deposition material 4 as having been blanket-deposited (i.e. non-selectively deposited) over the previously deposited first deposition material 2 as well as over the other portions of the substrate 6.
- the blanket deposition occurs by electroplating from an anode (not shown), composed of the second material, through an appropriate plating solution (not shown), and to the cathode/substrate 6.
- the entire two-material layer is then planarized to achieve precise thickness and flatness as shown in FIG. 2D.
- the multi-layer structure 20 formed of the second material 4 i.e. structural material
- first material 2 i.e. sacrificial material
- the embedded structure is etched to yield the desired device, i.e. structure 20, as shown in FIG. 2F.
- FIGS. 3A - 3C Various components of an exemplary manual electrochemical fabrication system 32 are shown in FIGS. 3A - 3C.
- the system 32 consists of several subsystems 34, 36, 38, and 40.
- the substrate holding subsystem 34 is depicted in the upper portions of each of FIGS. 3A - 3C and includes several components: (1) a carrier 48, (2) a metal substrate 6 onto which the layers are deposited, and (3) a linear slide 42 capable of moving the substrate 6 up and down relative to the carrier 48 in response to drive force from actuator 44.
- Subsystem 34 also includes an indicator 46 for measuring differences in vertical position of the substrate which may be used in setting or determining layer thicknesses and/or deposition thicknesses.
- the subsystem 34 further includes feet 68 for carrier 48 which can be precisely mounted on subsystem 36.
- the CC mask subsystem 36 shown in the lower portion of FIG. 3A includes several components: (1 ) a CC mask 8 that is actually made up of a number of CC masks (i.e. submasks) that share a common support/anode 12, (2) precision X-stage 54, (3) precision Y-stage 56, (4) frame 72 on which the feet 68 of subsystem 34 can mount, and (5) a tank 58 for containing the electrolyte 16.
- Subsystems 34 and 36 also include appropriate electrical connections (not shown) for connecting to an appropriate power source for driving the CC masking process.
- the blanket deposition subsystem 38 is shown in the lower portion of FIG. 3B and includes several components: (1) an anode 62, (2) an electrolyte tank 64 for holding plating solution 66, and (3) frame 74 on which the feet 68 of subsystem 34 may sit. Subsystem 38 also includes appropriate electrical connections (not shown) for connecting the anode to an appropriate power supply for driving the blanket deposition process.
- the planarization subsystem 40 is shown in the lower portion of FIG. 3C and includes a lapping plate 52 and associated motion and control systems (not shown) for planarizing the depositions.
- Formation of a second layer may then begin by applying a photoresist layer over the first layer and then repeating the process used to produce the first layer. The process is then repeated until the entire structure is formed and the secondary metal is removed by etching.
- the photoresist is formed over the plating base or previous layer by casting and the voids in the photoresist are formed by exposure of the photoresist through a patterned mask via X-rays or UV radiation.
- a process for fabricating a packaged electronic component includes: providing a substrate having conductive vias; forming routing elements on the substrate which have first and second ends, where at least some of the first ends are connectable to a first electronic component and at least some of the second ends are electrically connected to vias on the substrate; and connecting the first electronic component to the at least some of the first ends.
- a process for fabricating a packaged electronic component includes: providing a substrate having conductive vias; forming routing elements which have first and second ends, where at least some of the first ends are connectable to a first electronic component and at least some of the second ends are connectable to vias on the substrate; electrically connecting the at least some of the second ends to the vias comprising a bonding operation; and electrically connecting the first electronic component to the at least some of the first ends.
- a process for fabricating a plurality of packaged electronic components includes: providing a substrate; forming routing elements on the substrate which have first and second ends, where at least some of the first ends are electrically connectable to a first electronic component and at least some of the second ends are electrically connectable to a second electronic component; and attaching the first and second electronic components to the at least some of the first ends and second ends, respectively.
- a process for fabricating a plurality of packaged electronic components includes: providing a substrate; forming routing elements which have first and second ends, where at least some of the first ends are electrically connectable to a first electronic component and at least some of the second ends are electrically connectable to a second electronic component; establishing a thermally conductive connection between the substrate and routing elements; and electrically connecting the first and second electronic components to the at least some of the first ends and second ends, respectively.
- a fabrication process for fabricating a package for holding an electronic component includes: (a) forming and adhering a layer of material to a previously formed layer and/or to a substrate, wherein the layer comprises a desired pattern of at least one material; and (b) repeating the forming and adhering operation of (a) a plurality of times to build up a configuration of conductive interconnect elements, wherein the plurality of layers are adhered to one another and comprise at least one of (i) at least one structural material and at least one sacrificial material or (ii) at least two structural materials one of which is a conductor and one of which is a dielectric; and wherein at least one of the following is true: (1) the package comprises metal electrodeposited or electroless deposited on a layer-by-layer basis where the height of at least some layers is set by a planarization operation that planarizes an interconnect material and at least one other material; (2) the package comprises vias and traces that coexist on at least some
- FIGS. 1A - 1C schematically depict side views of various stages of a CC mask plating process
- FIGS. 1 D - G schematically depict a side views of various stages of a CC mask plating process using a different type of CC mask.
- FIGS. 2A - 2F schematically depict side views of various stages of an electrochemical fabrication process as applied to the formation of a particular structure where a sacrificial material is selectively deposited while a structural material is blanket deposited.
- FIGS. 3A - 3C schematically depict side views of various example subassemblies that may be used in manually implementing the electrochemical fabrication method depicted in FIGS. 2A - 2F.
- FIGS. 4A - 41 schematically depict the formation of a first layer of a structure using adhered mask plating where the blanket deposition of a second material overlays both the openings between deposition locations of a first material and the first material itself.
- FIGS. 5A - 5D schematically depict side views of various stages in a process for attaching an example IC to an example package where interconnects from the IC to at least one other component include vias that extend through a substrate on which electrochemically fabricated routing elements are formed.
- FIG. 6 schematically depicts a side view of two example ICs attached to and at least partially electrically interconnected to one another via an example package and where at least a portion of the interconnects extend through routing elements formed via electrochemical fabrication methods.
- FIG. 7 schematically depicts a side view of an example IC attached to an alternative example package configuration, where the package configuration includes a conductive substrate, routing elements that provide interconnect paths from a surface of the package to the IC, and which includes optional passive components such as inductors and capacitors.
- FIG. 8 schematically depicts a side view of an example IC attached to a package configuration similar to that of FIG. 7 with the exception that the substrate includes a passage for allowing a cooling fluid to pass through the substrate.
- FIG. 9 schematically depicts a side view of two example ICs and a package with routing elements and which further includes an added packaging element that takes the form of a heat sink that is located above one of the ICs and which includes a passage through which a cooling liquid may flow.
- FIG. 10 schematically depicts a side view of routing elements formed via electrochemical fabrication where a substrate on which the layers were formed has been removed and an IC attached.
- FIGS. 1 A - 1 G, 2A - 2F, and 3A - 3C illustrate various features of one form of electrochemical fabrication that are known.
- Other electrochemical fabrication techniques are set forth in the '630 patent referenced above, in the various previously incorporated publications, in various other patents and patent applications incorporated herein by reference, still others may be derived from combinations of various approaches described in these publications, patents, and applications, or are otherwise known or ascertainable by those of skill in the art from the teachings set forth herein. All of these techniques may be combined with those of the various embodiments of various aspects of the invention to yield enhanced embodiments. Still other embodiments may be derived from combinations of the various embodiments explicitly set forth herein.
- FIGS. 4A-4I illustrate various stages in the formation of a single layer of a multi-layer fabrication process where a second metal is deposited on a first metal as well as in openings in the first metal where its deposition forms part of the layer.
- FIG. 4A a side view of a substrate 82 is shown, onto which pattemable photoresist 84 is cast as shown in FIG. 4B.
- FIG. 4C a pattern of resist is shown that results from the curing, exposing, and developing of the resist.
- the patterning of the photoresist 84 results in openings or apertures 92(a) - 92(c) extending from a surface 86 of the photoresist through the thickness of the photoresist to surface 88 of the substrate 82.
- a metal 94 e.g. nickel
- FIG. 4E the photoresist has been removed (i.e. chemically stripped) from the substrate to expose regions of the substrate 82 which are not covered with the first metal 94.
- FIG. 4F depicts the completed first layer of the structure which has resulted from the planarization of the first and second metals down to a height that exposes the first metal and sets a thickness for the first layer.
- FIG.4H the result of repeating the process steps shown in FIGS. 4B - 4G several times to form a multi-layer structure are shown where each layer consists of two materials. For most applications, one of these materials is removed as shown in FIG.41 to yield a desired 3-D structure 98 (e.g. component or device).
- Various embodiments of various aspects of the invention are directed to formation of three-dimensional structures from materials some of which may be electrodeposited or electroless deposited. Some of these structures may be formed form a plurality of layers of deposited materials (e.g. two or more layers, more preferably five or more layers, and most preferably ten or more layers). In some embodiments structures having features positioned with micron level precision and minimum features size on the order of tens of microns are to be formed. In other embodiments structures with less precise feature placement and/or larger minimum features may be formed. In still other embodiments, higher precision and smaller minimum feature sizes may be desirable.
- the various embodiments, alternatives, and techniques disclosed herein may form multi-layer structures using a single patterning technique on all layers or using different patterning techniques on different layers.
- different types of patterning masks and masking techniques may be used or even techniques that perform direct selective depositions without the need for masking.
- Various embodiments of the invention may perform selective patterning operations using conformable contact masks and masking operations, proximity masks and masking operations (i.e. operations that use masks that at least partially selectively shield a substrate by their proximity to the substrate even if contact is not made), non-conformable masks and masking operations (i.e.
- Adhered mask may be formed in a number of ways including (1 ) by application of a photoresist, selective exposure of the photoresist, and then development of the photoresist, (2) selective transfer of pre-pattemed masking material, and/or (3) direct formation of masks from computer controlled depositions of material.
- Patterning operations may be used in selectively depositing material and/or may be used in the selective etching of material.
- Selectively etched regions may be selectively filled in or filled in via blanket deposition, or the like, with a different desired material.
- the layer-by-layer build up may involve the simultaneous formation of portions of multiple layers.
- depositions made in association with some layer levels may result in depositions to regions associated with other layer levels. Such use of selective etching and interlaced material deposited in association with multiple layers is described in US Patent Application No.
- FIGS. 5A - 5D schematically depict side views of various stages in a process for attaching an example IC to an example package where interconnects from the IC to at least one other component include vias that extend through a substrate on which electrochemically fabricated routing elements are formed.
- FIG. 5A depicts a substrate 102 for use with some embodiments of the invention.
- the substrate includes a plurality of conductive vias 104 through a dielectric material 106 (e.g. a ceramic, glass, polymer) that extend from a lower surface 108 to an upper surface 1 10 of the substrate.
- the vias may be uniformly spaced with a desired pattern while in other embodiments they may be spaced in an irregular pattern.
- the vias may extend along straight paths perpendicular to the top and bottom surfaces while in other embodiments, the paths may form more complex patterns including merging and/or diverging configurations and/or they may not extend perpendicular to the surfaces.
- the top and bottom surfaces may not be planar and/or the surfaces may not be parallel to one another.
- the substrate 102 may be formed in a variety of ways such as by low temperature co-fired ceramic (LTCC) formation methods, multi-layer ceramic (MLC) formation methods, electrochemical fabrication methods, drilling vias in a dielectric material and filling the vias with conductive material, and the like.
- LTCC low temperature co-fired ceramic
- MLC multi-layer ceramic
- electrochemical fabrication methods drilling vias in a dielectric material and filling the vias with conductive material, and the like.
- FIG. 5B depicts the state of the process after a plurality of layers 120 have been formed with each having a desired configuration so as to form routing elements 122 via an electrochemical fabrication process.
- the routing elements 122 may be partially encapsulated by a dielectric material 124 while in other embodiments the routing elements may be separated by air or even vacuum or other gas after packaging.
- the electrochemical fabrication process may be one of those shown and described in association with FIGS. 2A - 2F or 4A - 4F or as described in the various other patent applications incorporated herein by reference.
- the electrochemical fabrication process may involve the deposition of a conductive material and a dielectric material during the formation of each layer (e.g.
- each layer may be formed with a structural material (e.g. a material used in forming routing elements) and a sacrificial material (e.g.
- the electrochemically fabricated structure may include various electronic components such as inductor 126 and capacitor 128.
- other passive or active devices may be included in the structure while in still other embodiments such «electronic devices need not be formed as part of, or otherwise included in, the structure.
- added components may not be embedded in dielectric material but may instead be located within voids in the dielectric material.
- the formation of layers 120 may occur one after another with the first being adhered to the substrate 102.
- the layers 120 may be formed on a sacrificial substrate or on a temporary substrate on which a release layer exists and after formation (and potentially testing) the structure defined by layers 120 may be transferred and bonded to substrate 102 and released from the sacrificial or temporary substrate and release layer. Examples of the transfer and release of structures may be found in U.S. Patent Application No. 11/173,241 , filed Jun. 30, 2005, by Kumar, et al., and entitled Probe Arrays and Method for Making; and U.S. Patent Application No.
- FlG. 5C shows the state of the process after an IC 132 is moved along arrow 134 and brought into contact with the electrochemically fabricated layers 120, after which they may be bonded or otherwise connected to one another (e.g. via flip- chip attachment). Such bonding may occur, for example, using solder bumps 136 which are located on the bottom of IC 132. In other embodiments, solder bumps may be additionally or alternatively located on selected portions of the structure 120.
- FIG. 5D shows the state of the process after additional components, such as spring elements 142, have been added to the assembly.
- various pads on the IC make electric contact with elements 122 (or to pads connected to elements 122) some of which electrically connect various pads of the IC to one another while others connect electric pads of the IC to the vias which in turn may electrically connect to other circuit elements (not shown).
- some routing elements may be in the form of simple conductive leads 122' while others may be in the form of shielded 122" conductive leads (e.g.
- coaxial elements while still others may be in the form of waveguides, microstrip, or stripline (not shown), or the like.
- the routing elements may change dimensions, orientation, and the like for making desired electrical connections, avoiding inappropriate contact with other routing elements, enhancing electrical conductivity, electrical current carrying capacity, thermal conductivity, and/or other attributes of the package. For example, ground (GND) and voltage (VDD) connections may be made with arbitrarily wide for better current supply and lower inductance.
- Conductive traces in structure 120 may touch selected spots or areas on an IC or on other components to spread heat and/or conduct heat away. These selected spots or areas may be those areas which would otherwise form hot spots or cold spots.
- the substrate 102 of FIGS. 5A - 5D may be bonded to or made to electrically contact electrical leads on or extending from other components. In different embodiments, such attachment may be made prior to forming layers 120 on the substrate 102 or after transferring IC 132 to the substrate 102 or at some point between these states.
- FIG. 6 schematically depicts a side view of two example ICs attached to and at least partially electrically interconnected to one another via an example package where at least a portion of the interconnects extend through routing elements formed via electrochemical fabrication.
- some routing elements conduct signals from each IC to the vias in the substrate, and/or from one IC to the other IC.
- the conducted signals may be shielded (e.g. via coaxial routing elements) or non-shielded, they may be power or ground signals, data signals, clock signals, or the like.
- a shielded e.g. coaxial connection, ultra-high bandwidth connection
- Such shielded interconnect elements may provide: (1) non-dispersive signal transmission, (2) little or no cross-talk, (3) low loss ( ⁇ 0.5 dB/cm), (4) vastly improved routing flexibility for shortest point-to-point connections, (5) arbitrary thickness and low-inductance GND & VDD connections, (6) routing of the main clock tree connections off the die for die size savings and power savings, and/or (7) desired impedance matching or signal filtering functions.
- FIG. 7 schematically depicts a side view of an example IC attached to an alternative example package configuration, where the package configuration includes a conductive substrate, routing elements that provide interconnect paths from a surface of the package (i.e. an upper surface of the package in this example) to the IC, and which includes passive components such as inductors and capacitors.
- the routing elements of the electrochemically fabricated structure 140 do not feed signals from the IC 142 to vias that extend through the substrate but instead to pads 146 located on upper surface 144 of structure 140.
- the pads 146 are covered with solder bumps (in this example) which may be used in establishing electrical and possibly mechanical bonding to another circuit element (not shown). In other embodiments, electrical connections may be established via other elements (e.g.
- the substrate in the example of FIG. 7 is made of a solid block of conductive material (e.g. copper) which may be useful in helping conduct heat away from IC 142. In some alternative embodiments some insulated vias may pass through the substrate. In other alternative embodiments, the substrate may include ridges or ridges may be cut into the substrate to enhance thermal convection and/or radiative properties.
- the IC 142 is located within an indentation in the electrochemically fabricated structure so that appropriate positioning of the upper surface 144 relative to the IC 142 is obtained. In other embodiments, the IC may have an upper surface (after attachment) that is not below surface 144 but is coincident with it or which is above it.
- the opening in the structure 140 into which IC 142 is placed may be formed in a variety of ways, for example, via an electrochemical fabrication process by forming routing elements from a conductive structural material, the opening 148 from a sacrificial material that is eventually removed, and the other regions from a desired dielectric material. Methods allowing such three material formation processes are set forth in a plurality of the patent applications incorporated herein by reference, for example in US Patent Application 10/434,519. In other embodiments, more than one opening may exist. Each opening may be configured to receive one or a plurality of ICs or other components.
- the electrochemically fabricated structure may be substantially formed from conductive material which is located in different regions by relative thin or narrow locations of dielectric material such that the dielectric material provides appropriate isolation and impedance characteristics but such that the structure as a whole has improved thermal conductive properties for removal or redistribution of heat from an IC or other electronic component that is mounted on it.
- the substrate on which the layers of electrochemically fabricated structures are formed or transferred to may be a dielectric or a composite structure including conductive and dielectric regions.
- FIG. 8 schematically depicts a side view of an example IC attached to a package whose configuration is similar to that of FIG. 7 with the exception that the substrate 150 includes a passage 152 for allowing a cooling fluid to pass through the substrate as indicated by arrows 154.
- the cooling fluid may be in the form of a liquid or a gas.
- connection lines and a pump may be provided to supply fluid to and remove fluid and heat from the substrate.
- the connection lines, with or without added fins or the like may offer sufficient cooling of the fluid while in other embodiments a radiator or radiative structures may be specifically added to a selected location or locations along the feed lines to aid in the removal of heat.
- a fan may be used to direct or draw air over the radiative elements to help remove heat.
- the substrate or a portion of a substrate may be made using electrochemically fabricated layers.
- Fluid passages may form channels in a heat pipe. These channels may provide paths for enhanced conductivity of heat away from selected areas or paths (e.g. wicking paths) for drawing cooled fluid back to a location from which heat is to be removed.
- the paths may be uniformly distributed while in other cases they may be designed to provide tailored heat extraction from selected locations.
- heat pipe elements may exist within the substrate and/or they may be formed within the electrochemically fabricated layers. After formation of the layers, a desired fluid may be added to the passages and the structure sealed.
- substrates may be formed from two or more separately formed structures which are bonded together after formation so as to allow formation of selected passages and/or trenches in the various pieces. Separate formation and/or open formation then folder over and bonding may allow for easier removal of sacrificial material. Filling and sealing of fluid into the passages of a heat pipe may occur in a variety of ways. Sealing may be performed by pinching off a fill tube that is formed as part of the structure. Sealing may be performed blocking an opening with a solder ball Filling may occur after removal of a sacrificial material and before or after bringing separately formed pieces together. Teachings concerning open formation are provided in U.S. Provisional Patent Application No.
- FIG. 9 schematically depicts a side view of two example ICs and a package with routing elements and which further includes an added packaging element that takes the form of a heat sink 160 that is located above one of the ICs and which includes a passage 162 through which a cooling fluid (e.g. a liquid or gas) may flow as indicated by arrows 164.
- a cooling fluid e.g. a liquid or gas
- substrates shown in FIGS. 5A - 5D, FIG. 6, FIG. 7, and FIG. 9 may be removed after formation of the patterned layers, as shown in FIG. 10.
- solder bumps may be placed on the bottom surface of the routing structure that may be used in making electrical contacts to other elements.
- the packaging may include separately or integrally formed mechanically active devices (e.g. accelerometers, photonics alignment structures, pressure sensors, other sensors, and the like). Some such devices are disclosed in the various patent applications incorporated herein by reference.
- a second material is blanket deposited to fill in the voids
- the two depositions are planarized to a common level and then a portion of the first or second materials is removed (e.g. by etching) and a third material is sprayed into the voids left by the etching operation.
- the resulting depositions are planarized to a desired layer thickness in preparation for adding additional layers.
- the formation of the integrated circuit packages may involve a use of structural or sacrificial dielectric materials which may be incorporated into embodiments of the present invention in a variety of different ways. Additional teachings concerning the formation of structures on dielectric substrates and/or the formation of structures that incorporate dielectric materials into the formation process and possibility into the final structures as formed are set forth in a number of provisional and non-provisional patent applications. These filings include US Patent Application Nos. 60/534,184, 11/029,216, and 11/028,957, filed Dec. 31 , 2003, Jan. 3, 2005, and Jan.
- Various other embodiments of the present invention exist. Some of these embodiments may be based on a combination of the teachings herein with various teachings incorporated herein by reference. Some embodiments may not use any blanket deposition process and/or they may not use a planarization process. Some embodiments may involve the selective deposition of a plurality of different materials on a single layer or on different layers. Some embodiments may use selective deposition processes or blanket deposition processes on some or all layers that are not electrodeposition processes (e.g. electroless deposition processes.
- Some embodiments may use nickel, nickel titanium, nickel cobalt, titanium, stainless steel, gold, copper, tin, silver, zinc, solder, various alloys of these and other and/or dielectric materials as structural materials while other embodiments may use different materials.
- Some embodiments may use copper, tin, zinc, solder or other materials and/or dielectric materials as sacrificial materials. Some embodiments may remove a sacrificial material while other embodiments may not.
- Some embodiments may use photoresist, polyimide, glass, ceramics, other polymers, and the like as dielectric structural materials.
Abstract
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US60303004P | 2004-08-19 | 2004-08-19 | |
US60/603,030 | 2004-08-19 | ||
US61008304P | 2004-09-14 | 2004-09-14 | |
US60/610,083 | 2004-09-14 | ||
US11/028,945 US7640651B2 (en) | 2003-12-31 | 2005-01-03 | Fabrication process for co-fabricating multilayer probe array and a space transformer |
US11/028,945 | 2005-01-03 |
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US4649990A (en) * | 1985-05-06 | 1987-03-17 | Hitachi, Ltd. | Heat-conducting cooling module |
US5756395A (en) * | 1995-08-18 | 1998-05-26 | Lsi Logic Corporation | Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures |
US6027630A (en) * | 1997-04-04 | 2000-02-22 | University Of Southern California | Method for electrochemical fabrication |
US6525414B2 (en) * | 1997-09-16 | 2003-02-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device including a wiring board and semiconductor elements mounted thereon |
-
2005
- 2005-08-19 WO PCT/US2005/029494 patent/WO2006023696A2/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US4649990A (en) * | 1985-05-06 | 1987-03-17 | Hitachi, Ltd. | Heat-conducting cooling module |
US5756395A (en) * | 1995-08-18 | 1998-05-26 | Lsi Logic Corporation | Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures |
US6027630A (en) * | 1997-04-04 | 2000-02-22 | University Of Southern California | Method for electrochemical fabrication |
US6525414B2 (en) * | 1997-09-16 | 2003-02-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device including a wiring board and semiconductor elements mounted thereon |
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