WO2006021827A1

WO2006021827A1 - Single-ended optically biased three transistor fully static ram cell

Info

Publication number: WO2006021827A1
Application number: PCT/IB2004/002739
Authority: WO
Inventors: Goran Krilic
Original assignee: Goran Krilic
Priority date: 2004-08-23
Filing date: 2004-08-23
Publication date: 2006-03-02

Abstract

A single ended three transistor static RAM cell comprises two cross coupled MOS transistors and one select MOS transistor connected to drain of one of the aforementioned MOS transistors wherein drains of both cross coupled MOS transistors are each connected to anode of one of two PN diodes functioning as constant current loads when exposed to continuous light from LED diode.

Description

Single Ended Optically Biased Three Transistor Fully Static RAM Cell

Abstract - Single ended static memory scheme is proposed combining advantages of both one transistor DRAM cell and 6 transistor SRAM cell For the first time optical bias is introduced converting the classical CMOS RAM to optoelectronic device The cell structure is highly scalable and cost effective

I INTRODUCTION

Various approaches and schemes were applied to combine advantages of static and dynamic RAM memories striving for shortening of access times , lowering of power dissipation and decreasing cell area This is particularly true for SoC [ 1 ] and embedded memories [ 2 ] , [ 3 ] Here the novel approach towards the same goal is proposed and simulated , introducing standard CMOS technology Single ended three transistor fully static RAM cell is demonstrated

II MEMORY CELL SCHEME

Figure Ie shows proposed static random access memory cell consisting of only 3 NMOS transistors and 1 PMOS transistor One NMOS transistor act as select transistor , two NMOS transistors are connected in cross coupled fashion and generate positive feedback necessary for bistabihty Instead of PMOS loads two PN photodiodes , which are almost ideal current sources , see fig Ic , are connected to drains of cross coupled transistors Photodiodes are parasitic P+N diodes representing Nwell - P+ drain(source) of unactive PMOS transistor Similar photodiode stru' tures exist in a chip form Photodiode arrays in CMOS^' (0,6 urn) are com mer ,ially used for spatially distributed light detection f >r th i use in optical storage systems [ 4 ]

Memory cell (the whole chip) is exposed to low wavelength ijed - 650nm) light from LED diode aligned on top of chip Introduction of light to chip surface is not new In UV EPROMs UV light is used to erase memory cells through window on top jf chip Figure Id shows equivalent circuit of parasitic >hotodiode Series resistance(Rs) is equal to PMOS drain(source)ohmic resistance and junction capacitance(Cj) is equal to zero-bias B-D(B-S) PMOS junction capacitances It vanes with voltage applied in nonlinear fashion (determined by PMOS parameters MJ bulk junction bottom grading coeffϊcient)and MJSW (bulk junction sidewall grading coefficient) Figure Ib shows typical spectral responsivity characteristic (in A/W) for photodiodes Figure Ic shows typical current/voltage curves for a photodiode for different light levels Photoconductive (linear) and photovoltaic (nonlinear) modes exist for reverse and forward voltages respectively in. SIMULATION SETUP AND RESULTS

Memory cell has two stable states which is shown on Figures 2a and 2b which shows computer simulation ,using INTUSOFT ICAP/4 SPICE software , of write and retention of "1" and "0" in memory cell .Following NMOS model parameters were used : ICAP/4 LEVELl NMOS :

VTO=0.5V/ϊCP=3.1E_5A/V^t2/GAMMA=0.37VO.5/PHI=0.65V/LAMBDA=0.02V/ RD=3E+lW/RS =3E+lW,CBD=5fF/CBS=5fF/Is=lE-15A/PB=0.87V/CGSO=lE- 1 lF/m/CGDO=lE-l lF/m/CGBO=5E-l lF/m /MJ=0.5/TOX=lE-7m/TNOM=50 oC/CJSW =2.5E-8/MJSW=0.5

L=lum , Vdd=3,3V , bit line capacitance C3 was chosen to be moderate 20OfF (short bit lines) .Level 3 and level 6 models should be more appropriate for simulating integrated devices . However , due to complexity of circuit (including photodiodes and bit line precharge circuitry equivalents) and several pulse generators ,LEVELl enables much faster transient analysis and better immunity to convergence problems , although NMOS model itself is not so accurate .Nevertheless , feasibility of proposed memory cell at an integrated level is proved . Photodiodes were replaced by electrical equivalent which is high resistance shunt (lOOGOhms) in parallel with constant current source(300nA) . Bit line precharge and discharge circuitry is simulated by constant current source and NMOS voltage clamping circuit using gate-drain connected , (negative) voltage pulsed source NMOS transistor .Output capacitance Cl was calculated from current and voltage simulation diagrams . It is approximately 10 fF .

Proposed cell , although static , is operated (read and write) completely different from standard 6 transistor CMOS SRAM cell . It has only one select transistor thus it operate single ended .

Write and read operation are performed exactly as in one transistor dynamic RAM cell .Power consumption in read and write , without optical power which will be considered later , is identical as in DRAM cell . Computer simulation of write I/retention and write O/retention operations shows feasibility of the single ended operation .Fig. 5 shows alternating write 1 and write 0 operations .After first write '0' operation both Cl and C2 are at zero voltage , which results in abrupt increase of output voltage in all subsequent write T operations . Normally it takes several cycles for photocurrent to charge C2 to 3,3V - logical '0' , output (Cl) is OV , see fig. 2b . In write 1 small boost above Vdd at word line , as in standard DRAMs , would be required to enable cell output charging to full logical 1 level (3,3V) .However , it is not necessary because photocurrent from Dl will charge cell output capacitance to full log. 1 level after only a few cycles , see Fig. 2a . Simulations also show that , due to nonsymmetric cell , after voltage and light switch on output state becomes logical ¹O¹. Read operation is particularly interesting because voltage difference on precharged bit line is detected by sense amplifier as in DRAM cell .Voltage change also result from charge redistribution between output( acting storage)NMOS gate- source capacitance and much larger bit line capacitance. In read word line is pulsed to 1,5 V and bit line is precharged to 0,5 V . When reading logical 0 , select transistor charges corregjpøffding output capacitance of the cell (Cl on Fig. Ie) .Output transistor , .M 4 see Fig. Ie , has gate on 3,3V (C2 charged to 3,3V in log. 0 output)and draws large current when output capacitance is even slightly charged ,thus keeping output low (100m V max.) during reading , see Fig. 3 where voltage vs. time diagram for cell output capacitance and bit line capacitance is shown. After initial precharge to 0,5 V in 10 ns ,bit line is being discharged resulting in voltage swing of 20OmV in 10ns which is sufficient to drive sense amplifier.

When reading logical 1 select transistor (M3) draws current from the cell output (Cl) which is high (3,3 V) and thus discharges output capacitance simultaneously charging bit line capacitance .After initial precharge to 0,5V , see diagram on Fig.4 , bit line capacitance voltage increases for 10OmV in the next 10ns . Cell output capacitance (Cl) is temporarily discharged to approx. 2,6V . After reading , constant photocurrent from photodiode Dl is linearly charging Cl back to 3,3V and full level logical 1 is automatically restored in next 20-40ns .Small over- voltage results from photodiode photovoltaic mode operation , that is rapidly decreasing photocurrent existing in small forward voltages . Considering that NMOS threshold voltages are 0,5 V , NMOS 5 will not switch off and will continue to keep gate of NM0S4 low despite constant charging from photodiode D2 . Both Figures 3 and 4 show nondestructive read operation as in standard 6 transistor CMOS cell .Small bit line precharge voltage is advantageous due to fast precharge and discharge of bit line .Depletion mode or low threshold enhancement mode transistors are suitable in sense amplifiers to match low voltage operation . Read operation simulation was also performed with Vdd word line and Vdd/2 bit line voltages , as in most standard DRAMs , and the results are almost identical although larger photocurrents were required .Simulations also show that bit line precharge voltages from 0.5 V- Vdd/2 are applicable . Word line voltages 1-1,5 V larger than bit line voltage were required for proper operation. However , consideration on precharge voltage selection in relation to optimization of sense amplifier , as regards sensitivity and its speed of operation , is not subject of this paper .

Considering again technology issues , photodiodes are incorporated as P+ areas (anodes substitute drain/source function of PMOS transistor) in N well .Thus , technology for cell manufacturing is 100% standard CMOS technology . The only difference from standard 6 transistor CMOS static cell is that one select (NMOS) and one load (PMOS) transistors are removed .In remaining PMOS (load) transistor N well (N+) is connected to Vdd and P+ regions (drain and source) are connected to drains of cross-coupled NMOS transistors . When illuminated they function as photodiodes .Between metal contacts and poly(gate) light penetrates to P+ drain and source (photodiodes' anodes)region only , causing photocurrent , see Fig. 7 .Light penetration of low wavelength (red) light in silicon is only few um ,see diagram on Fig. Ia which shows light attenuation according to Beer-Lambert law ,which corresponds with shallow and thin P+N depletion layer .Figure 6 shows chip cross-section incorporating classical CMOS inverters connection and Figure 7 shows 2 cross-coupled NMOS transistors and two photodiodes of the proposed cell . Everything is technologycally identical except on Fig.7 N+ (guard ring) is connected (metalisation) to Vdd and drain(anode) of unactive PMOS to drain of opposite NMOS transistor , without forming new metal layer . Gate can be left floating or connected to Vdd .Since the PMOS transistors are standard enhancement mode (standard CMOS) it will not operate under positive gate-source voltage .

IV. OPTICAL POWER AND TECHNOLOGY CONSIDERATION

In standby power dissipation is bellow 1 nW/cell which corresponds to photocurrents having strength in pA-nA range , equal to leakage currents . However in active mode , due to read operation particularly in case of reading logical 1 , photocurrents have to be few hundred nA (30OnA here) to maintain nondestructive read or automatic refresh after read cycle .Thus , in active mode power dissipation per cell is 0,75 uW . Considering that photodiodes occuppy only 25% of chip area which is 100% exposed to LED diode light , required optical power is , for 288kb(32K-byte) memory , 860 mW in active and 0,1 mW in standby mode ,0,8 A/W responsivity is presumed .Leakage is 40 pA , see fig. 8 .Proper scaling of memory elements would give much better results regarding access speed and power dissipation .Considering relatively low (15%-30% max.) standard LED external quantum efficiency , proper LED - RAM chip (silicon dioxide) alignment and LED sizing is essential in minimizing electrical power dissipation .Optimizing of electrical-optical parameters requires substantial experimental work .However , analysis of alignment is similar to that of optocouplers except transparent medium is ultrathin compared to optocouplers where thick layer is required for galvanic insulation up to few thousand volts . Fresnel losses resulting from refractive index mismatch and causing internal reflections are described using equation

T ' = 4/[2+n2/nl + nl/n2] , where T is fraction of light transmitted and nl is semiconductor (3,6 for AlGaAs) and n2 oxide (approx. 1,5) refractive index .Thin film having larger refractive index would increase T . The same equation is used for oxide-silicon (silicon refractive index is 3,5) interface . If that fraction of light is marked T " then totally transmitted light is T = T ' x T " . Considering external quantum efficiency there are special patterned thin film LED diodes which exhibit high external efficiency up to 70% , see [ 5 ] .However they are not suitable for application herein .

Aforedescribed memory cell can operate in pulsed mode . Light source can be pulsed at low frequency (< IkHz) in standby and write modes to save energy . Information will not be lost , it will be kept dynamically between two light pulses , see fig. 8 which shows optical refreshing with lus (2OnA) pulses applied each 500us (duty 1/500). Without light applied photodiodes act as decoupling diodes and memory cell function as dynamic cell . Hence , term self-refreshing DRAM would be more appropriate in pulsed mode . The most important feature is that in optical refreshing light can be applied independently and simultaneously with other cycle pulses . LED diode (red) which is necessary for light input (bias) is cheap compared to the price of memory chip .Average prices for large volumes rate from 10-30 cents .The price should be even lower without unnecessary plastic encapsulation and lense .Low price is a result of LEDs mass production for micro displays .Small rectangular or square LED diodes' sizes matches typical chip sizes (few square mm) . LED diodes operate at 1,5V-2,5V which perfectly matches RAM chip source voltages .Maximum optical output powers are in 50-15OmW range whereas DC forward currents are 20-40 mA . Peak forward currents can reach sevenfold values usually for 1/10 duty cycle 0,1 ms pulse width . Optical power is linearly proportional to the photocurrent . In pulsed mode optical power is larger , which is inversely proportional to the pulse width .Some mega bright miniature red LEDs exhibit luminous intensity of 7000 mcd (lOOOmcd per square mm) with drive currents of 20 mA only .For 650 nm ,1000mcd =13,698 mW optical power per steradian.

Using special drivers to generate overshoots and undershoots LEDs can be pulsed to 300 Mb/s and even 1000 Mb/s . It would enable bias LED diode to be pulsed by clock signal in read mode .Consequently read operation would remain nondestructive whereas the optical power would be considerably reduced compared to continuous operation .Further (optical) power saving can be achieved if LED diode is replaced with active LED matrix (x-y array) which can be activated (pulsed) only for addressed sections of memory chip in read mode .For example 10 segments LED would decrease optical and electrical power tenfold . In the CMOS process , after gate oxide growth , poly layer (gate) should not be deposited on P channel transistor thus leaving large transparent area for light penetration in the N well .After photogeneration of electron-hole pairs in the N well , they will diffuse to P+N photodiodes' depletion layers and separate by electrical field generating photocurrent . This significantly increases photodiodes' photocurrents particularly in relation to parasitic-unwanted photocurrents which are generated in drain (N+)-substrate (P) junctions of active NMOS transistors .

V. CONCLUSIONS

The memory cell operation is simulated to show feasibility of write , retention and read operations . It is shown for 3,3V logic (3,3V power supply) . However it can work with 2V or less as well .Increased speed and avoiding of external refresh are advantageous to dynamic RAMs while reduced cell area and yet keeping low power dissipation , particularly in standby and pulsed mode , are advantageous towards static RAM schemes .If destructive read Rewriting after read of logical 1 required , is acceptable penalty power dissipation per cell is only several hundred pW which allowes gigabit SRAM .Some DRAM schemes , see ref. [ 3 ] , solve the problem of write-back impact on cycle time through multibanking and write-back buffers .

REFERENCES

[1] Wingyu Leung , Fu-Chieh Hsu , Marc-Eric Jones : " The Ideal SoC Memory IT-

SRAM : MoSys paper

[2] Zhigang Hu , Philo Juang , Phil Diodato et al. : " Managing Leakage for Transient

Data - Decay and Quasi-Static 4T Memory Cells " : ISLPED'02 August 12-14

Monterey CA USA

[3] Chorng-Lii Hwang , Toshiaki Kirihata , Matthew Wordenan et al. : "A 2,9 ns

Random Access Cycle Embedded DRAM with a Destructive-Read Architecture "

2002 Symposium on VLSI Circuits Digest of Technical Papers

[4] I. Hehemann , E. Ozkan , H. Hofmann , A. Kemna , W. Brockherde, and B. J

Hosticka : " A CMOS Photodiode Array with Linearized Spectral Response and

Spatially Distributed Light Intensity Detection for the Use in Optical Storage

Systems ." ESSDERC 2002 paper .

[5] M. Boroditsky , T.F. Krauss , R. Coccioli et al. : " Light extraction from optically pumped Light-Emitting Diode by thin slab photonic crystals ." , Applied Physics

Letters . FIGURE CAPTIONS

Fig I a Absorption coefficient of photons in silicon

Fig 1 b Typical specti al responsivity

Fig 1 c Chai acteristic I-V curves of a typical photodiode

Fig 1 d Equivalent circuit for the silicon photodiode Iph is photocurrent , whereas Cj , RSH , and Rs are junction capacitance , shunt resistance , and series resistance respectively

Fig 1 e Thi ee transistor static cell circuit

Fig 2 a Wi ite of logical 1 and retention Photocurrent charges full level to the memory cell aftei 10 ns write cycle and initial charging to 2,2 V (logical 1 ) Lower graph v(3) shows discharging of C2 to OV

Fig 2 b Wi ite of logical 0 and retention Lower graph v(3) shows charging of C2 to 3,5V Photocuirent linearly charges C2 until photodiode photovoltaic mode

Fig 3 Read of logical 0 After 10ns bit line precharge to 0,5 V (v6-gι aphl ) , charge redistribution decreases bit line voltage for 20OmV in 10ns i ead time without affecting cell charge which remains low (yl-graph2) Graph3 -v4 shows word line voltage

Fig 4 Read of logical 1 After 10ns bit line precharge to 0,5 V (v6-graphl ) , charge redistribution increases bit line voltage for 100m V in 10ns read time without change of stored logical 1 (yl-graph2) Graph3 - v4 shows word line voltage Photocurrent charges cell to full logical level 1 in just two cycles

Fig 5 Alternating wnte 1 and write 0 operations Graph4 -v6 and graph3 -v4 represent bit line and word line write pulses respectively Giaph l -y 1 shows cell output in wi ite 1 -pause- wnteO multiple streams , graph2 - v3 shows C2 voltage

Fig 6 Chip cross-section of standard inverter (CMOS)

Fig 7 Cross-section of three transistor SRAM cell (CMOS) LED diode on top not shown

Fig 8 Optical pulse refreshing , graph shows C l voltage change Leakage current linearly discharges C l which is refreshed with l us ( 1/500 duty) light pulses

Claims

What is claimed is :

1 . A single ended three transistor fully static RAM cell comprising : Two cross coupled MOS transistors and one select MOS transistor connected to drain of one of the aforementioned cross coupled MOS transistors wherein drains of both cross coupled MOS transistors are connected to different anodes of two PN diodes functioning as loads .

2. The device of claim 1 further comprising a light source optically coupled to PN diodes

, said PN diodes generating constant photocurrents due to large dynamic resistance .

3. The device of claim 2 wherein light is generated by large light emitting diode or laser diode optically coupled to RAM memory chip containing aforementioned RAM cells , said light emitting diode or laser diode being operated in constant or preferably pulsed mode .

4. The device of claim 1 wherein reading is performed by precharging bit line of select MOS transistor to low voltage and word line to voltage larger for at least value of aforementioned MOS transistor threshold voltage causing small positive or negative drain current of aforementioned select MOS transistor without significantly changing output voltage level of cross coupled transistors representing stored data , said stored data being represented during reading by direction of drain current , said drain current being detected by current or voltage sense amplifier .

5. The device of claim 1 being manufactured by standard CMOS technology , said device being physically different from standard CMOS memory cell by not having one select NMOS transistor and one PMOS load transistor .

6. The device of claim 5 wherein aforementioned PN diodes' anodes and cathodes are drain-n well and source- n well structures of remaining unactive PMOS load transistor

7. The device of claim 6 wherein n wells are connected by metalisation to voltage source and drain and source of unactive PMOS load transistor are connected to different drains of cross coupled MOS transistors .

8. The device of claim 1 wherein total capacitance connected to drain of cross coupled MOS transistor connected to select MOS transistor is larger than total capacitance connected to gate of the same cross coupled transistor .