WO2006018873A1

WO2006018873A1 - Data processor, and equipment and method for evaluating electronic equipment system

Info

Publication number: WO2006018873A1
Application number: PCT/JP2004/011850
Authority: WO
Inventors: Katsuaki Saotome
Original assignee: Usc Digiark Corporation
Priority date: 2004-08-18
Filing date: 2004-08-18
Publication date: 2006-02-23

Abstract

A data processor, electronic equipment system verifying equipment and a method thereof are provided for high-speed, low-cost and easy operation. The data processor operating based on design specifications of the electronic equipment system to be verified is provided with a dynamic reconfigurable device which performs operation verification and an input/output control means which is configured with a field programmable gate array (FPGA)which is connected to the dynamic reconfigurable device and controls input/output signals to and from external equipment. The equipment and method for verifying electronic equipment system are provided by using the data processor.

Description

Specification

Data processing apparatus, electronic device system evaluation apparatus and evaluation method

Technical field

TECHNICAL FIELD [0001] The present invention relates to a data processing device, an electronic device system verification device, and a verification method, and in particular, an electronic device system verification device that can perform operation verification of an electronic device system inexpensively and at high speed with actual hardware operation. And a verification method.

Background art

[0002] Data processing apparatuses are used in electronic device systems to perform image processing, communication processing, and other various processes. In such a data processing apparatus, the data format and the like are specific to each electronic device system and vary, so hardware and software dedicated to the electronic device system may be used.

[0003] In developing an electronic device system, it is necessary to verify its operation. Such electronic device systems are required to be large-scaled, complicated and diversified, and to shorten the development period of electronic device systems. In addition to image processing systems, there are similar demands in broadcasting equipment systems, communication systems, and other systems.

[0004] Further, with regard to such verification work, function verification work for confirming whether a prototype produced from a design specification can be correctly realized, and whether or not a required specification can be realized. It is also necessary to verify the architecture from the algorithm.

[0005] That is, in addition to the verification work to confirm whether the mounted circuit element satisfies the design specification, it is desirable to perform the verification work to verify what hardware and software the design specification can be realized. It is rare.

[0006] As such a verification device, Patent Document 1 discloses performance verification that maintains an abstraction level that enables cache analysis, and does not require an ISS (instruction set simulator), but a single verification platform. As a simulation device that can be performed at high speed, a software-implemented function is generated as a verification environment platform (a software model that runs on a processor), and a hardware-implemented function is created using an RTL / RTC model or higher. As an operation model with a high degree of abstraction, performance verification is performed on processor B and An interface model that exchanges input / output data between models has been proposed.

Patent Document 1: Japanese Patent Application Laid-Open No. 2004-13227

Disclosure of the invention

Problems to be solved by the invention

[0008] Currently, the data processing device of the electronic device system described above is not versatile. As described above, it is necessary to develop and manufacture dedicated ICs, boards, and dedicated software, and devices are developed for each electronic device system. It needs to be manufactured, takes a long development period, and is expensive.

[0009] The verification of the electronic device system is performed by a modeling 'simulation method. In this method, an electronic device system is built in software on a PC or workstation and its operation is verified. However, the signal speed of an electronic device system that can be emulated by such a method is slower than the actual electronic device system (for example, 1 / 100,000 or less). For this reason, there is a problem that it takes too much time to verify a large-scale and complicated electronic device system, and the development period is prolonged.

[0010] Furthermore, as a means for verifying an electronic device system, there is a method of emulating a hardware system of the electronic device system. This hardware emulation is faster than the soft emulation described above, but slower than the actual speed of an actual electronic system (for example, 1/100 or less). ) In addition, it is difficult to handle and expensive (for example, tens of millions of yen or more). For this reason, the verification time is long and the verification cost is enormous.

[0011] The present invention provides a data processing apparatus capable of handling various data processing at high speed, and using this data processing apparatus, a prototype environment of an electronic device system is performed by real-time processing at high speed and at low cost. Another object of the present invention is to provide a data processing device, an electronic device system verification device, and a verification method that are easy to handle.

Means for solving the problem

[0012] The present invention relates to a dynamically reconfigurable device (DynamicReconfi) in a data processing apparatus that processes input data from an external apparatus and outputs processed data to the external apparatus. gurabledevice) and input / output control means for controlling input / output signals connected to the dynamically reconfigurable device and external devices.

[0013] Further, according to the present invention, the dynamically reconfigurable device includes a Neumann type processor and a non-Neumann type dynamic arithmetic unit that dynamically switches a circuit configuration and performs data processing and arithmetic processing. Device.

[0014] Further, according to the present invention, the processor core of the dynamically reconfigurable device is a DAP (Digital

Application Processor) and dynamic computation unit is DNA (Distributed Network)

Architecture) A data processing device comprising a matrix.

[0015] In the present invention, the input / output control means controls the signal format and timing so that the signal to be processed by the dynamically reconfigurable device and the processed signal can be input / output to / from the outside. It is a processing device.

[0016] The present invention is the data processing device in which the input / output control means is configured by an FPGA (Field Programmable Gate Array).

The present invention is also a data processing device including an extended input / output connector for connecting an external function device.

[0018] Further, according to the present invention, the extended input / output connector is provided on at least one of a front surface and a back surface of a substrate to which the dynamically reconfigurable device and the input / output control device are attached. It is.

The present invention is also a data processing device configured by stacking a plurality of data processing devices and electrically connecting them.

[0020] Further, the present invention relates to a dynamic reconfigurable device that performs an operation verification operation in an electronic device system verification apparatus that performs an operation verification based on a design specification of an electronic device system to be verified. And an input / output control means for controlling input / output signals to / from an external device connected to the dynamically reconfigurable device.

[0021] In addition, the present invention provides an electronic device system verification in which a dynamically reconfigurable device includes a Neumann processor and a non-Neumann dynamic arithmetic unit that dynamically switches a circuit configuration and performs data processing and arithmetic processing. Device. In addition, the present invention provides an electronic device system verification apparatus in which a processor core of a dynamically reconfigurable device includes a DAP (Digital Application Processor), and a dynamic operation unit includes a DNA (Distributed Network Architecture) matrix. It is.

[0023] Further, according to the present invention, the input / output control means controls the signal format and timing so that the signal to be processed by the dynamically reconfigurable device and the processed signal can be input / output to / from an external device. The electronic device system verification apparatus.

[0024] Further, according to the present invention, the input / output control means includes an FPGA (Field Programmable Gate).

This is an electronic device system verification apparatus configured as an (Array).

[0025] The present invention is an electronic device system verification apparatus including an extended input / output connector for connecting an external function device necessary for verification of the electronic device system.

In the present invention, the extended input / output connector is provided on at least one of a front surface and a back surface of a substrate on which the dynamically reconfigurable device and the input / output control device are attached.

The electronic device system verification apparatus.

In addition, the present invention is an electronic device system verification apparatus configured by stacking and electrically connecting a plurality of electronic device system verification apparatuses.

The present invention also relates to an electronic device system verification apparatus provided with verification control means connected to a dynamically reconfigurable device and performing operation control including data rewriting from the outside to the dynamically reconfigurable device. It is.

[0029] Further, the present invention is a verification control unit that is connected to the input / output control unit and performs operation control including data rewriting to the dynamically reconfigurable device from the outside via the input / output control unit. The electronic device system verification apparatus provided with

[0030] Further, the present invention is the electronic device system verification apparatus in which the verification control means is connected to the dynamically reconfigurable device by serial connection or parallel connection.

[0031] The present invention is the electronic device system verification apparatus that monitors the electrical operation of the dynamically reconfigurable device in the input verification control apparatus.

[0032] Further, the present invention can be dynamically reconfigured to perform an operation verification operation to be verified in accordance with an electronic device system verification method for performing operation verification based on a design specification of the electronic device system to be verified. A positive device (Dynamic Reconfigurable Device) and a reconfigurable tenor An electronic device system verification method including input / output control means for controlling input / output signals to / from an external device connected to a chair.

[0033] Further, the present invention is an electronic device system verification method, wherein information for verification of an electric device system is input from the verification control device to the dynamically reconfigurable device, and a verification result is obtained. .

The present invention is also an electronic device system verification method for verifying a dynamically reconfigurable device built in an electronic device system to be verified.

[0035] Further, the present invention is an electronic device system verification method performed for an execution program for operating a dynamically reconfigurable device built in an electronic device system to be verified.

[0036] Further, the present invention provides an electronic device system verification method characterized by emulating hardware and software incorporated in an electronic device system to be verified by the dynamically reconfigurable device. is there.

The invention's effect

[0037] According to the data processing apparatus of the present invention, a data processing apparatus that performs various processes can be processed at a high speed by a dynamically reconfigurable device, and data processing that differs for each electronic device system can be handled. All you have to do is change the settings for the dynamically reconfigurable device and the I / O control means.

[0038] Further, according to the electronic device system verification apparatus and the verification method, the electronic device system verification apparatus that is fast, inexpensive, and easy to handle by realizing the prototype environment of the electronic device system with hardware capable of processing in real time. And can provide verification method

[0039] That is, according to the present invention, a wide range of support is possible, such as evaluation of dynamically reconfigurable devices, early algorithm verification of development applications, principle prototyping, and incorporation into the final product as a solution board. For applications that require high-speed processing, such as processing, that requires a dedicated custom IC (ASIC), development and mounting can be started quickly and easily before IC design.

Brief Description of Drawings FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention.

FIG. 2 is a block diagram showing a verification system using the electronic device system verification apparatus according to the present invention.

Explanation of symbols

[0041] 10 Data processing device (electronic device system verification device)

20 Dynamically reconfigurable devices (Reconfigurable.

21 DAP Department

22 DNA part

30 I / O control means (combination device)

41 DDRSDRAM

42 LCD

51 SerialROM

52 FlashROM

54 Parallel terminal

55 Parallel terminal

60 Expansion I / O connector

61 Extended input / output terminals

62 I / O terminals

70 I / O control means (companion device)

80 Expansion I / O connector

81 Extended input / output terminals

82 Extended input / output terminals

91 RS232C terminal

92 SSI terminal

93 EDU— Slave terminal

94 EDU— Master terminal

110 TV camera

111 A / D converter 120 Image display device

121 D / A converter

300 Host computer

400 Soft program verification controller

500 Hard logic verification controller

700 option 'board

900 Electronic system verification system

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention, and FIG. 2 is a block diagram showing a verification system using the electronic device system verification apparatus according to the present invention.

First, an embodiment of the data processing apparatus according to the present invention will be described. In this example, the data processing device 10 is an image processing device, and processes the image data captured by the imaging device 110 and displays it on the image display device 120. In this example, the data processing apparatus 10 is mounted on one board as shown in FIG. The data processing apparatus 10 of this example is a dynamically reconfigurable device 20 that is a reconfigurable processor, input / output control means 30 that is a companion device, DDRSRAM 41, and internal information display, which can be removed, for example. 20-character 4-string LCD42, dynamically reconfigurable device 20 dynamically reconfigurable device SDRAM43 to hold reconfiguration data, FlashROM52, 100-pin PCI interface terminal 54, 80-pin parallel Terminal 55, 84-pin extended input / output terminals 61 and 62 (extended input / output connector 60) for connecting external function devices, input / output control means 70, which is another companion device, and extended input / output terminal 81 , 82 (expansion I / O connector 80), RS232C terminal 91, which is an asynchronous serial terminal, and SS, which is a synchronous serial terminal, as input / output terminals of the dynamically reconfigurable device 20 An I terminal 92, an EDUSlave terminal 93, and an EDUMaster terminal 94 are provided. Here, the companion device acts as an auxiliary element of the dynamically reconfigurable device 20 which is a reconfigurable 'processor. The EDUSlave terminal 93 and the EDUMaster terminal 94 are debug interfaces dedicated to the dynamically reconfigurable device 20. In this example, the extended input / output connector 60 , 80 are provided on both the front and back surfaces of the board on which the dynamically reconfigurable device 20 and the input / output control means 30 are mounted. For this reason, the external device can be placed on top and bottom of the electronic device system verification device 10.

[0044] In addition, the dynamically reconfigurable device 20 is a DAPDNA_2 (Climbing! ^) Vote (Digital Application Processor Z Distributed Network Arc hitecture: Dynamic 'Reconfigurable. Processor: Dynamically chip. A processor capable of switching the internal circuit configuration was used. The dynamically reconfigurable device 20 includes a DAP part 21 and a DNA part 22 as shown in FIG. Here, the dynamically reconfigurable device 20 according to this example is a dual-core processor having a high-performance DAP (RISC core) and a dynamically reconfigurable DNA unit 22 (two-dimensional matrix). As a result, the dynamically reconfigurable device 20 can realize software flexibility and high-speed hardware processing.

[0045] In this example, in the DAP unit 21, dynamic 'reconfiguration control is performed, and a portion requiring high-speed processing is executed in a DNA matrix if parallel' pipeline processing development is possible. Is done. 376 PEs (operator 'memory' synchronizer 'counter) are arranged in the DNA section 22, and it is possible to freely reconfigure the optimum circuit according to each application.

In this example, DDRSRAM41, RS232C terminal 91, SSI terminal 92, EDUSlave terminal 93, and EDUMaster terminal 94 are connected to the dynamically reconfigurable device 20, and input of execution program and data of external data are performed. Input / output is possible.

[0047] In addition, the input / output control means 30 and 70 are configured by FPGA (Field Programmable Gate Array) in this example, and the signals to be processed and processed by the dynamically reconfigurable device 20 are expanded. In addition to controlling the signal format and timing so that input / output can be performed from the input / output connectors 60 and 80, it is also possible to monitor the electrical operation at predetermined terminals of the dynamically reconfigurable device 20 from the outside. Yes. In addition, the input / output control means 30 is provided with an I / F unit 31 that converts the input operation program and data and changes the timing so that the dynamically reconfigurable device 20 can process them. In addition, it is assumed that data input from outside 61 can be processed by the dynamically reconfigurable device 20. Alternatively, the output signal processed by the dynamically reconfigurable device 20 can be output from the extended input / output terminal 61.

Hereinafter, the input / output control means 30 will be described. In this example, the input / output control means 30 manages the input / output data of the dynamically reconfigurable device 20 based on the interface circuit information stored in the S ROM 51.

[0049] In this example, the TV input / output terminal 61 is connected to the TV power camera 110 via the AZD converter 111, and the extension input / output terminal 62 is connected to the CRT display via the D / A converter 121. An image display device 120 composed of a liquid crystal display, a plasma display or the like is connected. In this example, the processing of the image data input from the imaging device 110 such as a television camera is processed with the hardware and software set in the dynamically reconfigurable device 20 in advance, and the result is displayed on the image display device 120. It is supposed to be displayed on the screen.

In this example, the data processing device 10 is used as an image data processing device. Other data such as industrial image data, medical image data processing device, communication data processing device, It can be used as a telephone exchange.

[0051] In the above example, the data processing device 10 is used as a data processing device. However, it is possible to use a system having the same configuration as an electronic device system verification device, that is, an emulator. When used as an emulator, the external devices connected to the extended input / output terminals 61 and 62 are not limited to the above examples, and network, USB, level conversion, etc. are required according to the electronic device system to be verified. You can connect what you want to do.

[0052] When the data processing device 10 is used as an electronic device system verification device in this way, the result of the emulation is obtained from the dynamically reconfigurable device 20 directly via the EDU terminal 93 or the RS232C terminal 91. Via the parallel terminal 54 via the input / output control means 30.

[0053] In the above example, a case where one data processing device or electronic device system verification device is used alone has been described. However, two data processing devices or electronic device system verification devices according to the present invention are used. Overlay more than that, and use EDUSlave terminal 93, E DUMaster terminal 94 can be used as a single data processing device with multiple dynamically reconfigurable devices or an electronic equipment system verification device by connecting them electrically, for example by cross-connecting them.

[0054] Since the data processing apparatus and the electronic device system verification apparatus configured as described above can process a large amount of data in a distributed manner, the data processing speed and the emulation speed are extremely high. can do.

Next, a verification system 900 using the electronic device system verification apparatus 10 according to this example will be described. In this example, as shown in FIG. 2, the electronic device system verification device 10 includes a soft program verification control device connected to the host computer 300 to the LAN 200 and connected to the EDU terminal 93 of the electronic device system verification device 10. 400 or hard logic verification controller 500 connected to parallel terminal (EMUSE) 55 can be connected, and the execution program can be downloaded. In this example, the host computer 300 can also download the execution program and data from the host computer 300 serially connected from the RS232C terminal 91 and the parallel interface connected to the host computer 300 and connected to the parallel terminal 55. it can.

In this example, the expansion input / output connector 60 of the electronic device system verification apparatus 10 includes the video input / output camera, the image display device, the network, the USB, the A / D comparator, and the D Equipment (option 'Board 700) necessary for the emulation of electronic system such as / A converter and level converter can be installed. In this example, the extended input / output connectors are provided on both the front surface and the back surface of the board on which the dynamically reconfigurable device and the input / output control device are attached. Therefore, the option 'Board 700 is configured so that it can be placed on top and bottom of the electronic device system verification apparatus 10 to save space.

When verifying an electronic device system using the above-described verification system, first, an execution program and data are installed in the electronic device system verification apparatus 10 based on the specifications of the electronic device system. These execution programs and data can be input and processed from any of the host computer 300, the soft program verification control device 400, and the hard logic verification control device 500 described above. [0058] At this time, the execution program and data input from the hard logic verification control device 500 are changed to a format and timing executable by the dynamic reconfigurable device 20 in the input / output control means 30, and dynamically Input to reconfigurable device 20.

[0059] The execution program and data to be input are selected by hardware and software to be verified by the user.

The electronic device system verification apparatus 10 performs dynamic reconfiguration control in the DAP unit 21 of the dynamically reconfigurable device 20 according to the execution program, and the part that requires high-speed processing is If parallel 'pipeline processing deployment is possible, it will be executed in the DNA matrix. The 376 PEs (calculator “memory“ delay ”counter) in the DNA section 22 can freely reconfigure the optimum circuit according to each input.

As a result, the electronic device system of the specified specification is emulated, and a processing result (for example, an image processing result) by the input software of the specified hardware is output. This output result is processed by the input / output control means 30 and output in a state and timing that can be processed by a device connected to the extended input / output connector 60. From this result, the status of the processing result can be confirmed.

[0062] The result of this emulation, that is, how the processing of the hardware and software specified by the execution program and data is performed via the hard logic verification control device 500 or directly is performed by the host computer. Output to 300. As a result of this verification, it is possible to verify the electronic device system specified and emulated in the specification.

Therefore, according to the electronic device system verification apparatus and the verification method according to the present invention, by realizing the prototype environment of the electronic device system with hardware capable of processing in real time, it is fast, inexpensive, and easy to handle. Providing electronic device system verification equipment and verification methods.

[0064] In addition, according to the present invention, it is possible to perform a wide range of applications, such as evaluation of dynamically reconfigurable devices, early algorithm verification of development applications, principle prototyping, and incorporation into final products as solution boards. Before designing an IC for an application that requires high-speed processing such as processing, which previously required a custom IC (ASIC) Quickly and easily start development and implementation.

Industrial applicability

As described above, the data processing device, the electronic device system verification device, and the electronic device system verification method according to the present invention are applied to an electronic processing system that requires data processing, such as an image processing system, a communication system, an exchange system, and a broadcasting system. Can be applied.

Claims

The scope of the claims

[1] In a data processing device that processes input data from an external device and outputs the processed data to the external device.

A dynamic reconfigurable device and an input / output control device that controls input / output signals to / from external devices connected to the dynamically reconfigurable device. Data processing device.

[2] The dynamically reconfigurable device includes a Neumann type processor and a non-Neumann type dynamic arithmetic unit that dynamically switches a circuit configuration and performs data processing and arithmetic processing. The data processing apparatus according to 1.

[3] The processor core of the dynamically reconfigurable device includes a DAP (Digital Application Proces sor), and the dynamic operation unit includes a DNA (Distributed Network Architecture) matrix status. Item 3. The data processing device according to any one of Items 2 to 3.

[4] The input / output control means controls the signal format and timing so that the signal to be processed by the dynamically reconfigurable device and the processed signal can be input / output to / from the outside. The data processing device according to any one of claims 1 to 3.

[5] The data processing device according to any one of claims 1 to 4, wherein the input / output control means is configured by an FPGA (Field Programmable Gate Array).

[6] The data processing device according to any one of claims 1 to 5, wherein an extended input / output connector for connecting an external function device is provided.

[7] The extended input / output connector according to claim 6, wherein the extended input / output connector is provided on at least one of a front surface and a back surface of a board on which the dynamically reconfigurable device and the input / output control device are attached. Data processing device.

[8] A data processing device comprising a plurality of the data processing devices according to any one of claims 1 to 7 stacked and electrically connected.

[9] In an electronic device system verification apparatus that performs operation verification based on the design specifications of the electronic device system to be verified, A dynamic reconfigurable device that performs an operation verification operation, and an input / output control means that controls input / output signals between the dynamic reconfigurable device and an external device connected to the dynamic reconfigurable device; An electronic device system verification apparatus comprising:

[10] The dynamically reconfigurable device includes a Neumann type processor and a non-Neumann type dynamic arithmetic unit that dynamically switches a circuit configuration and performs data processing and arithmetic processing. 9. The electronic device system verification apparatus according to 9.

[11] The processor core of the dynamically reconfigurable device includes a digital application process sor (DAP), and the dynamic operation unit includes a matrix of DNA (distributed network architecture). Item 12. The electronic device system verification apparatus according to any one of Items 11.

[12] The input / output control means controls the signal format and timing so that the signal to be processed by the dynamically reconfigurable device and the processed signal can be input / output to / from an external device. 12. The electronic device system verification apparatus according to claim 9.

13. The electronic device system verification apparatus according to claim 9, wherein the input / output control means is configured by an FPGA (Field Programmable Gate Array).

14. The electronic device system verification apparatus according to claim 9, further comprising an extended input / output connector for connecting an external function device necessary for verification of the electronic device system.

15. The extended input / output connector according to claim 14, wherein the extended input / output connector is provided on at least one of a front surface and a back surface of a board on which the dynamically reconfigurable device and the input / output control device are attached. Electronic device system verification device.

[16] An electronic device system verification apparatus, wherein a plurality of electronic device system verification devices according to any one of claims 9 to 15 are stacked and electrically connected.

17. A verification control means connected to a dynamically reconfigurable device, comprising verification control means for performing operation control including data rewriting to the dynamically reconfigurable device from the outside. 17. The electronic device system verification apparatus according to any one of 16 above.

[18] A verification control unit that is connected to the input / output control unit and performs operation control including data rewriting to the dynamically reconfigurable device from the outside via the input / output control unit. The electronic device system verification apparatus according to any one of claims 9 to 17.

[19] The electronic device system verification apparatus according to any one of [9] or [18], wherein the verification control means is connected to the dynamically reconfigurable device by serial connection or parallel connection.

[20] The electronic device system verification apparatus according to any one of [9] to [19], wherein the input verification control apparatus monitors an electrical operation of the dynamically reconfigurable device. .

[21] In the electronic device system verification method that performs operation verification based on the design specifications of the electronic device system to be verified,

A dynamically reconfigurable device that performs an operation verification operation to be verified, and input / output control means that controls input / output signals between the dynamic reconfigurable device and an external device. An electronic device system verification method characterized by comprising:

[22] The electronic device according to claim 21, wherein information for verification of an electrical equipment system is input to the dynamically reconfigurable device from the verification control device according to claim 9 to 20, and a verification result is obtained. Device system verification method.

23. The electronic device system verification method according to claim 21, wherein the dynamic reconfigurable device built in the electronic device system to be verified is verified.

[24] The electronic device according to any one of claims 21 and 22, wherein the electronic device is an execution program for operating a dynamically reconfigurable device built in an electronic device system to be verified. Device system verification method.

[25] The method according to claim 21 or 22, wherein hardware and software embedded in an electronic device system to be verified are emulated by the dynamically reconfigurable device. Electronic device system verification method.