WO2006014188A2 - Fully silicided metal gates - Google Patents
Fully silicided metal gates Download PDFInfo
- Publication number
- WO2006014188A2 WO2006014188A2 PCT/US2005/008009 US2005008009W WO2006014188A2 WO 2006014188 A2 WO2006014188 A2 WO 2006014188A2 US 2005008009 W US2005008009 W US 2005008009W WO 2006014188 A2 WO2006014188 A2 WO 2006014188A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal
- suicided
- gate
- source
- suicide
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 138
- 239000002184 metal Substances 0.000 title claims abstract description 138
- 238000000034 method Methods 0.000 claims abstract description 160
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- 239000004065 semiconductor Substances 0.000 claims description 55
- 239000004020 conductor Substances 0.000 claims description 54
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 53
- 229920005591 polysilicon Polymers 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 45
- 238000000137 annealing Methods 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 39
- 125000006850 spacer group Chemical group 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 25
- 229910021332 silicide Inorganic materials 0.000 claims description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 20
- 229910005883 NiSi Inorganic materials 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 18
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- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
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- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to a semiconductor device and methods of fabricating the same, and more particularly to a metal oxide semiconductor (MOS) device that includes an advanced gate structure, e.g., fully suicided metal gate, as well as methods of fabricating the rally suicided metal gate device.
- MOS metal oxide semiconductor
- metal gate integration has proven difficult to achieve in a conventional process flow for MOS transistors.
- Most metal gate materials interact with the gate dielectric during the high temperature processing needed for source/drain (S/D) junction activation anneals.
- S/D source/drain
- the need to keep the metal gate stack from receiving high temperature anneals has lead to the development of the "gate last" or "replacement gate” process for which the gate stack is fabricated last and remains below 500°C during subsequent processing.
- replacement gate process increases the number of material choices for a metal gate, the process complexity and cost increases.
- FIG. IA which structure includes a semiconductor substrate 12, an isolation region 15, gate regions 16L and 16R, a gate dielectric 18, a polySi gate conductor 20 and a cap layer 22. Spacers 24 are located on each gate region as well.
- the source/drain implants are performed with the cap layer 22 atop the polySi conductor 20.
- the cap layer 22 is non-selectively removed, as shown in FIG.
- FIG. ID shows the structure after the salicide process in which suicided source/drain regions 100 and metal suicide gate 102 are formed. In this prior art process, gate and source/drain silicidation occurs simultaneously.
- this prior art process forms thick metal suicide gates and thick source/drain suicides, each having a thickness of approximately 100 nm. This can be problematic for a few reasons. Firstly, the suicide can extend underneath the gate and short the device. Secondly, such a thick source/drain suicide can also be problematic given the recess of the isolation regions of the device caused by the non ⁇ selective removal of the cap layer from the gate. Specifically, the suicide in this prior art process can short across devices separated by narrow isolation regions. Thirdly, the thick suicide may consume the silicon in the extension regions under the spacers leading to poor device performance. Hence, methods that produce a thick and fully suicided metal gate and a much thinner source/drain suicide are needed. In addition, the suicide in this prior art process can also contact the implanted well regions of the device thereby shorting the device.
- the present invention relates to an advanced gate structure that includes a fully suicided metal gate and suicided source and drain regions that abut the suicided metal gate.
- the present invention provides a semiconductor structure comprising a fully suicided metal gate of a first suicide metal having a first thickness and abutting suicided source and drain regions of a second metal having a second thickness, wherein said second thickness is less than the first thickness and said suicided source and drain regions are aligned to edges of a gate region including at least the fully suicided metal gate.
- the thick fully suicided metal gate and the thinner suicided source and drain regions can be composed of the same or different metal suicide such as, for example, suicides of Ti, Ta, W, Co, Ni, Pt, Pd and alloys thereof. Of the various suicides, suicides of Co, Ni or Pt, in their lowest resistivty phase, are particularly preferred.
- the source and drain regions include CoSi 2 , while the suicided metal gate includes NiSi and/or NiPtSi.
- the source and drain suicides comprise NiSi, while the suicided metal gate comprises NiSi and/or NtPtSi.
- a metal oxide semiconductor (MOS) device comprising a semiconductor substrate having suicided source and drain regions located on a surface thereof, said suicided source and drain regions having a thickness of less than 500 A and are self-aligned to an edge of a gate region that includes a fully suicided metal gate having a thickness of greater than 500 A.
- MOS metal oxide semiconductor
- the present invention also provides methods for forming the advanced gate structure having the thick and fully suicided metal gate and the thinner suicided source and drain regions abutting the suicided metal gate.
- the following processing steps are employed in fabricating the inventive structure:
- a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, a dielectric liner on at least sidewalls of said polysilicon gate conductor, and spacers on said dielectric liner and adjoining sidewalls of at least the polysilicon gate conductor;
- the suicided source/drain regions are formed prior to forming the material stack over the structure.
- the suicided source/drain regions are formed before the suicide metal gate, they are formed after forming the spacer in the structure obtained in the providing step.
- a second method of forming the inventive semiconductor structure is also provided.
- the second method employs a photoresist (negative-tone or positive-tone) and a dry etching process to selectively remove the dielectric cap.
- the second method of the present invention comprises the steps of:
- a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, and spacers on adjoining sidewalls of at least the polysilicon gate conductor;
- the suicided source/drain regions are formed prior to forming the photoresist over the structure.
- the suicided source/drain regions are formed before the suicide metal gate, they are formed after forming the spacer in the structure obtained in the providing step.
- the photoresist can be either a negative-tone photoresist or a positive-tone photoresist.
- a lift-off layer is formed surrounding the gate regions and then the patterned photoresist is formed. After removing the dielectric cap, the patterned photoresist above the lift-off layer, together with the lift-off layer, are removed from the structure.
- Another method of the present invention includes the use of a lithography level to provide precise alignment to the gate level.
- This third method of the present invention comprises:
- a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, and spacers on adjoining sidewalls of least the polysilicon gate conductor;
- the suicided source/drain regions are formed prior to forming the stack over the structure.
- the suicided source/drain regions are formed before the suicide metal gate, they are formed after forming the spacer in the structure obtained in the providing step.
- a lift-off layer can also be used in the third method of the present invention. The lift-off layer is formed on the exposed surface of the patterned gate stack prior to patterning the stack of planarizing material, masking layer and photoresist.
- FIGS. IA- ID are pictorial representations (through cross-sectional views) depicting a prior art process of fabricating self-aligned suicided metal gates from a polysilicon gate.
- FIGS. 2A-2G are pictorial representations (through cross-sectional views) illustrating the basic processing steps employed in a first method of the present invention.
- FIGS. 3A-3E are pictorial representations (through cross-sectional views) illustrating the basic processing steps employed in a second method of the present invention.
- FIGS. 4A-4D are pictorial representations (through cross-sectional views) illustrating an embodiment of the second method of the present invention in which a photoresist is used with a lift-off layer.
- FIGS. 5A-5I are pictorial representations (through cross-sectional views) illustrating a third method of the present invention in which a lithography level is used to provide precise alignment to the gate level.
- FIGS. 6A-6D are pictorial representations (through cross-sectional views) illustrating how a planarizing layer protects the underlying material and circumvents critical dimension (CD) biasing and misalignment inherent to lithography.
- CD critical dimension
- FIGS. 7A-7E are pictorial representations (through cross-sectional views) illustrating one lift-off scheme that can be used in conjugation with a planarizing layer.
- FIGS. 8A-8F are pictorial representations (through cross-sectional views) illustrating another lift-off scheme that can be used in conjugation with a planarizing layer.
- the present invention which provides a MOS device that has a fully suicided gate and thin suicided source and drain regions (relative to the gate and prior art suicided source/drain regions) as well as methods of fabricating the same, will now be described in greater detail by referring to the drawings which accompany the present application.
- FIG. 1 In the accompanying drawings, which are not drawn to scale, like and/ ⁇ r corresponding elements are referred to by like reference numerals.
- MOS device regions are shown to be formed atop a single semiconductor substrate. Although illustration is made to such an embodiment, the present invention is not limited to the formation of any specific number of MOS devices on the surface of the semiconductor structure. Instead, the method of the present invention forms at least one fully suicided MOS device on a surface of a semiconductor substrate.
- Structure 10 includes a semiconductor substrate 12 that has two gate regions 16L and 16R, which are located on a surface of the semiconductor substrate 12.
- Each gate region, i.e., 16R and 16L includes a gate dielectric 18, a polySi conductor 20, a dielectric cap 22, dielectric liner 23, spacers 24 and source/drain regions 14.
- the source/drain regions 14 are located within semiconductor substrate 12.
- the semiconductor substrate 12 of structure 10 comprises any semiconducting material including, but not limited to: Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, InAs, InP and all other III/V compound semiconductors.
- Semiconductor substrate 12 may also comprise an organic semiconductor or a layered semiconductor such as Si/SiGe, a silicon-on-insulator (SOI) or a SiGe-on-insulator (SGOI).
- SOI silicon-on-insulator
- SGOI SiGe-on-insulator
- the semiconductor substrate 12 maybe doped, undoped or contain doped and undoped regions therein.
- the semiconductor substrate 12 may also include a first doped (n- or p-) region, and a second doped (n- or p-) region.
- n- or p- doped
- second doped region doped regions are not specifically labeled in the drawings of the present application.
- the first doped region and the second doped region may be the same, or they may have different conductivities and /or doping concentrations. These doped regions are known as "wells".
- Trench isolation regions are typically already formed in the semiconductor substrate at this point of the present invention utilizing conventional processes well known to those skilled in the art.
- the trench isolation regions are located to the periphery of the region shown in the drawings of the present invention as well as between the two gate regions depicted.
- a gate dielectric 18 is formed on the entire surface of the structure 10 including the semiconductor substrate 12 and atop the isolation region, if it is present and if it is a deposited dielectric.
- the gate dielectric 18 can be formed by a thermal growing process such as, for example, oxidation, nitridation or oxynitridation.
- the gate dielectric 18 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition and other like deposition processes.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- evaporation reactive sputtering
- chemical solution deposition chemical solution deposition and other like deposition processes.
- the gate dielectric 18 may also be formed utilizing any combination of the above processes.
- the gate dielectric 18 is comprised of an insulating material including, but not limited to: an oxide, nitride, oxynitride and/or silicate including metal silicates and nitrided metal silicates, hi one embodiment, it is preferred that the gate dielectric 18 is comprised of an oxide such as, for example, SiO 2 , HfO 2> ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , and mixtures thereof.
- an oxide such as, for example, SiO 2 , HfO 2> ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , and mixtures thereof.
- the physical thickness of the gate dielectric 18 may vary, but typically, the gate dielectric 18 has a thickness from about 0.5 to about 10 nm, with a thickness from about 0.5 to about 3 nm being more typical.
- a blanket layer of polysilicon i.e., polySi
- the blanket layer of polysilicon may be doped or undoped. If doped, an in-situ doping deposition process may be employed in forming the same.
- a doped polySi layer can be formed by deposition, ion implantation and annealing. The doping of the polySi layer will shift the workfunction of the suicided metal gate formed.
- dopant ions include As, P, B, Sb, Bi, In, Al, Ga, Tl or mixtures thereof.
- the thickness, i.e., height, of the polysilicon layer deposited at this point of the present invention may vary depending on the deposition process employed. Typically, the polysilicon layer has a vertical thickness from about 20 to about 180 nm, with a thickness from about 40 to about 150 nm being more typical.
- a dielectric cap 22 is formed atop the blanket layer of polysilicon gate conductor 20 utilizing a deposition process such as, for example, physical vapor deposition or chemical vapor deposition.
- the dielectric cap 22 may be an oxide, nitride, oxynitride or any combination thereof.
- the dielectric cap 22 can be comprised of a different dielectric material than spacer 24 to be defined in detail herein below.
- a nitride such as, for example, Si 3 N 4
- the dielectric cap 22 is an oxide such as SiO 2 .
- the thickness, i.e., height, of the dielectric cap 22 is from about 20 to about 180 nm, with a thickness from about 30 to about 140 nm being more typical.
- the blanket polysilicon layer and dielectric cap layer are then patterned by lithography and etching so as to provide patterned gate stacks.
- the patterned gate stacks may have the same dimension, i.e., length, or they can have variable dimensions to improve device performance.
- Each patterned gate stack at this point of the present invention includes a polySi gate conductor 20 and dielectric cap 22.
- the lithography step includes applying a photoresist to the upper surface of the dielectric cap layer, exposing the photoresist to a desired pattern of radiation and developing the exposed photoresist utilizing a conventional resist developer.
- the pattern in the photoresist is then transferred to the dielectric cap layer and the blanket layer of polysilicon utilizing one or more dry etching steps.
- the patterned photoresist may be removed after the pattern has been transferred into the dielectric cap layer. In other embodiments, the patterned photoresist is removed after etching has been completed.
- Suitable dry etching processes that can be used in the present invention in forming the patterned gate stacks include, but are not limited to: reactive ion etching, ion beam etching, plasma etching or laser ablation.
- the dry etching process employed is typically selective to the underlying gate dielectric 18 therefore this etching step does not typically remove the gate dielectric. In some embodiments, this etching step may however be used to remove portions of the gate dielectric 18 that are not protected by the gate stacks.
- a wet etching process can also be used to remove portions of the gate dielectric 18 that are not protected by the gate stacks.
- a dielectric liner 23 is formed on all exposed surfaces containing silicon including at least the polysilicon gate conductor 20.
- the dielectric liner 23 can also extend onto a horizontal surface of the semiconductor substrate 12, as is shown in FIG. 2A.
- the dielectric liner 23 may comprise any dielectric material that contains an oxide, nitride, oxynitride or any combination thereof.
- the dielectric liner 23 is formed via a thermal growing process such as oxidation, nitridation or oxynitridation.
- the dielectric liner 23 is a thin layer whose thickness is typically from about 1 to about 10 nm.
- At least one spacer 24 is formed on exposed sidewalls of each patterned gate stack as well as atop the dielectric liner.
- the at least one spacer 24 is comprised of an insulator such as an oxide, nitride, oxynitride and/or any combination thereof and it typically is composed of a different material than the dielectric liner 23 and the dielectric cap 22.
- nitride spacers are formed.
- the at least one spacer 24 is formed by deposition and etching. Note that the etching step used in forming the spacers 24 also can remove dielectric liner 23 from atop the substrate such that a portion of the semiconductor substrate 12 is exposed.
- the exposed portion of the semiconductor substrate 12 is labeled as reference numeral 11 in FIG. 2A.
- the width of the at least one spacer 24 must be sufficiently wide enough such that the source and drain suicide contacts (to be subsequently formed) do not encroach underneath the edges of the gate stack.
- the source/drain suicide does not encroach underneath the edges of the gate stack when the at least one spacer has a width, as measured at the bottom, from about 15 to about 80 nm.
- source/drain diffusion regions 14 are formed into the substrate 12 at the exposed portion 11.
- the source/drain diffusion regions 14 are formed utilizing ion implantation and an annealing step.
- the annealing step serves to activate the dopants that were implanted by the previous implant step.
- the conditions for the ion implantation and annealing are well known to those skilled in the art.
- a material stack comprising a conformal dielectric layer 26 and a planarizing dielectric 28 is formed over the entire structure shown in FIG. 2A.
- the conformal dielectric layer 26 is formed first followed by the planarizing dielectric layer 28.
- the conformal dielectric layer 26 comprises any dielectric material including an oxide, nitride, and/or oxynitride.
- the conformal dielectric layer 26 comprises a nitride such as Si 3 N 4 .
- the conformal dielectric layer which is formed utilizing a conventional deposition process, has a thickness after deposition from about 15 to about 80 run.
- the planarizing dielectric layer 28 is formed.
- the planarizing dielectric layer 28 comprises an oxide such as a high density oxide or an oxide deposited from TEOS.
- the planarizing dielectric layer 28 may comprise a doped silicate glass, such as boron doped silicate glass (BSG) or phosphorus doped silicate glass (PSG), a spin-coatable polymeric material such as hydrogen silsesquioxane (HSQ), or a photoresist.
- BSG boron doped silicate glass
- PSG phosphorus doped silicate glass
- HSQ hydrogen silsesquioxane
- the planarizing dielectric layer 28 is formed by conventional techniques well known to those skilled in the art.
- the thickness of the planarizing dielectric layer 28 formed at this point of the present invention may vary depending on the type of material employed. Typically, the planarizing dielectric layer 28 has a thickness from about 50 to about 100 nm. hi accordance with the present invention, the planarizing layer atop the gate stacks is less than the thickness of the same over the source/drain regions and the trench isolation regions.
- FIGS. 2C and 2D represent various embodiments that can be employed in the present invention to expose dielectric cap 22.
- FIG. 2C shows an embodiment in which an etch back process is employed
- FIG. 2D shows an embodiment in which a chemical mechanical polishing (CMP) process is employed.
- the etch back process comprises at least one timed etching process that can selectively remove portions of both the planarizing dielectric layer 28 and the conformal dielectric layer 26 which extend above an upper surface of the dielectric cap 22.
- a portion of the planarizing dielectric layer 28 is first etched back and then a portion of the conformal dielectric layer 26 is etched back using different etching processes.
- 2C comprises a dry etch process that first etches oxide selective to nitride followed by a dry etch process that etches nitride selective to oxide.
- the CMP process used in forming the structure shown in FIG. 2D is conventional and well known to those skilled in the art.
- the exposed dielectric cap 22 is removed from each gate region 16L and 16R. so that the underlying polysilicon gate conductor 20 is exposed.
- the resultant structure that is formed after this step has been performed is shown, for example, in FIG. 2E.
- the dielectric cap 22 is removed in the present invention by utilizing an etching process, wet or dry, which removes the dielectric cap material from the structure.
- etching process such as reactive-ion etching (RIE), ion beam etching (IBE), and plasma etching can be employed, it is preferred that a wet etch process be employed in removing the dielectric cap 22.
- dilute hydrofluoric acid DHF
- this step also removes the remaining planarizing dielectric layer 28 between the gate regions. This is shown in FIG. 2E as well. In this instance, the remaining portion of the conformal dielectric layer 26 protects the portion of the substrate containing the source/drain regions 14.
- a first salicide process is performed to consume the polySi gate conductor 20 forming folly suicided metal gates 30.
- the first salicide process is exemplified in FIG. 2F.
- the first step of the first salicide process includes depositing a blanket suicide metal atop the structure shown in FIG. 2E.
- the suicide metal can be deposited using any conventional deposition process including, for example, sputtering, chemical vapor deposition, evaporation, chemical solution deposition, plating and the like.
- the suicide metal can be the same or different than the metal used in forming the suicided source/drain regions (to be subsequently formed and described).
- the suicide metal can be composed of at least one of Ti, Hf, Ta, W, Co, Ni, Pt, Pd or alloys thereof.
- the suicide metal is Co; CoSi 2 forms using a two step annealing process.
- the suicide metal is Ni or Pt; NiSi and PtSi form using a single annealing step.
- the suicide metal thickness is selected so as to form the suicide phase with the appropriate workfunction for the particular MOS device and to consume all of the polySi gate conductor 20.
- NiSi has a workfunction of 4.65 eV
- CoSi 2 has a workfunction of 4.45 eV
- the amount of Co needed is about 14 nm.
- the suicide metal thicknesses given are the amount necessary to just consume the polysilicon, it is preferred if the thickness were in excess by about 10% to make sure consumption is complete.
- an oxygen diffusion barrier such as TiN or W is formed atop the silicide metal prior to annealing.
- the salicide annealing includes a first anneal which is employed to form a first silicide phase in the structure; the first silicide phase may or may not represent the lowest resistivity phase of a metal silicide.
- the first anneal is typically performed at lower temperatures than the second annealing step.
- the first annealing step which may, or may not, form a high resistance silicide phase material, is performed at a temperature from about 300° to about 600 0 C using a continuous heating regime or various ramp and soak heating cycles. More preferably, the first annealing step is performed at a temperature from about 350° to about 550 0 C.
- the salicide anneals are carried out in a gas atmosphere, e.g., He, Ar, N 2 or forming gas.
- a gas atmosphere e.g., He, Ar, N 2 or forming gas.
- the gate suicide annealing steps may use different atmospheres or the annealing steps may be carried out in the same atmosphere.
- He may be used in both annealing steps, or He can be used in the first annealing step and a forming gas may be used in the second annealing step.
- a selective wet etch step is employed to remove any non-reactive suicide metal from the structure.
- the salicide process may be stopped at this point since the polysilicon is consumed and the resistivity of the first suicide phase is close to minimum values for the phase. This is in the case for Ni and Pt. hi other cases, for example when Co or Ti are used as the suicide metal, a second higher temperature anneal is needed for the consumption of the remaining polysilicon and forming a second suicide phase material.
- the first silicide phase is a high resistivity phase suicide material
- the second suicide phase material is a lower resistivity phase silicide material.
- the second annealing step is performed at a temperature from about 600 0 C to about 800 0 C using a continuous heating regime or various ramp and soak heating cycles. More preferably, the second annealing step is performed at a temperature from about 650 0 C to about 750 0 C.
- FIG. 2F shows the structure after formation of fully suicided metal gates 30.
- the fully suicided metal gates 30 are located atop the gate dielectric 18 between spacers 24 in an area previously occupied by the polySi gate conductor 20.
- the remaining portions of the planarizing dielectric layer 28 between the gate regions is removed utilizing a selective etching process.
- the remaining portions of the conformal dielectric layer 26 between each gate region is then removed utilizing an etching process that selectively etches the conformal dielectric material from the structure. This step of the present invention exposes the portion of the substrate 12 containing source/drain regions 14.
- Source and drain suicide contacts 32 are then formed using a salicide process which includes the steps of depositing a suicide metal on an exposed surface of the substrate 12 that includes the source/drain diffusion regions 11, optionally depositing an oxygen diffusion barrier material such as TiN on the suicide metal, first annealing to form a suicide, selective etching any non-reacted metal including barrier material if used and, if needed, performing a second annealing step.
- a salicide process which includes the steps of depositing a suicide metal on an exposed surface of the substrate 12 that includes the source/drain diffusion regions 11, optionally depositing an oxygen diffusion barrier material such as TiN on the suicide metal, first annealing to form a suicide, selective etching any non-reacted metal including barrier material if used and, if needed, performing a second annealing step.
- the step of the present invention is shown in FIG. 2G.
- a layer of silicon (not shown) can be grown atop the exposed surface of the semiconductor substrate 12 and can be used in forming the source/drain suicide contacts.
- the suicide metal used in forming the source/drain suicides 32 comprises any metal that is capable of reacting with silicon to form a metal suicide. If the substrate does not include silicon, then the metal suicide needs to comprise a metal that will form a suicide with other substrate materials, e.g., Ni for a SiGe surface. Examples of such metals include, but are not limited to: Ti, Ta, W, Co, Ni, Pt, Pd and alloys thereof. In one embodiment, Co is a preferred metal. In such an embodiment, the second annealing step is required. In another embodiment, Ni or Pt is preferred. In this embodiment, the second annealing step is typically not performed.
- the suicided source/drain regions 32 can be formed utilizing the conditions described above in forming the suicided gate.
- the source/drain suicides, i.e., suicided source/drain regions, 32, which are formed utilizing the above-mentioned process, are self-aligned to edges of the gate region 16R or 16L.
- the outer edges of the suicided source/drain regions 32 are aligned with edges of the dielectric liner 23 and spacer 24.
- the suicided source/drain regions 32 have a thickness (measured vertically) of less than 50 nm, with a thickness from about 15 to about 30 nm being more typical.
- the suicided metal used in forming the suicided source/drain regions and the suicided metal gate may include an alloying additive that can enhance the formation of the metal suicide.
- alloying additives that can be employed in the present invention include, but are not limited to: C, Al, Ti, V, Cr, Mn 5 Fe, Co, Ni, Cu, Ge, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Hf, Ta, W, Re, Ir, Pt or mixtures thereof, with the proviso that the alloying additive is not the same as the material used in forming the suicide.
- the alloying additive is present in an amount from about 0.1 to about 50 atomic percent.
- the alloying additive may be introduced as a dopant material to the suicide metal layer or it can be a layer that is formed atop the suicide metal layer prior to annealing.
- the present invention also contemplates the presence of raised source/drain regions in the initial structure.
- the raised source/drain regions are formed utilizing conventional techniques well known to those skilled in the art. Specifically, the raised source/drain regions are formed by depositing any Si-containing layer, such as epi Si, amorphous Si, SiGe, and the like, atop the substrate prior to implanting the source/drain regions.
- the present invention also contemplates an embodiment in which the suicided source/drain regions are formed prior to the suicided metal gate.
- the suicided source/drain regions can be formed after spacer 24 formation, prior to forming conformal dielectric layer 26 over the structure.
- FIGS. 3A-3E show a second method of the present invention.
- a photoresist negative-tone or positive- tone
- dry etching are employed to remove the dielectric cap 22 that lies atop the polysilicon gate conductor 20.
- the second method begins with first providing the structure 50 shown in FIG. 3A.
- the structure 50 is similar to the structure 10 shown in FIG. 2A except that no dielectric liner 23 is present. Although, no dielectric liner 23 is shown, the present invention contemplates an embodiment in which the same is present.
- the structure 50 shown in FIG. 3A comprises substrate 12 that has two gate regions 16L and 16R, which are located on a surface of the semiconductor substrate 12.
- Each gate region, i.e., 16R and 16L includes a gate dielectric 18, a polySi gate conductor 20, a dielectric cap 22, spacers 24 and source/drain regions 14.
- the source/drain regions 14 are located within semiconductor substrate 12.
- the initial structure shown in FIG. 3 A is fabricated using the techniques described above in the first embodiment for fabricating structure 10 shown in FIG.
- a negative-tone photoresist (or alternatively a positive-tone photoresist) 52 is then formed over the entire structure providing the structure shown in FIG. 3B.
- the term "negative-tone photoresist” denotes a photoresist that remains in areas that were not protected from exposure by opaque regions of a mask, while being removed by the developer in regions that were protected. Hence, the unexposed regions of the photoresist remain after development and thus the negative image of a mask remains.
- the negative-tone photoresist 52 employed in the present invention thus includes any photoresist material which when exposed to light changes from a soluble condition to an insoluble condition. Such negative-tone resists are conventional and well known to those skilled in the art.
- the present invention also contemplates using positive-tone photoresists.
- Such positive-tone photoresists are also well known to those skilled in the art.
- the use of the positive-tone photoresist does not alter the processing steps described below.
- the specific type of photoresist employed is dependent upon the polarity of the mask used, as is well known to those skilled in the art.
- the photoresist 52 is applied to the structure shown in FIG. 3 A using a conventional deposition process such as spin-on coating that is well known to those skilled in the art.
- the thickness of the applied photoresist 52 may vary so long as the upper surface thereof is above the upper surface of the dielectric cap 22.
- FIG. 3 C shows the structure after exposing the photoresist to radiation and developing the areas of the photoresist 52 that are above each gate region 16L and 16R.
- the exposure and developing process include conventional lithography techniques that are well known to those skilled in the art. Note that in this structure the upper surface of each dielectric cap 22 atop the polySi gate conductor 20 is exposed.
- the dielectric cap 22 is removed from the structure so that the underlying polySi gate conductor 20 is exposed, hi accordance with this embodiment of the present invention, the dielectric cap 22 is removed utilizing a dry etching process that selectively removes the dielectric cap as compared to the photoresist.
- a dry etching process that selectively removes the dielectric cap as compared to the photoresist.
- reactive ion etching, or laser beam etching ion beam etching can be used to selectively remove the dielectric cap 22.
- the remaining photoresist 52 is removed from the structure providing the structure illustrated in FIG. 3E.
- the processing described above in forming the suicided metal gates and suicided source/drain regions is then performed.
- the resultant structure is similar to the one depicted in FIG. 2G except that the dielectric liner 23 is not necessarily present.
- the second embodiment also contemplates the case when the suicided source/drain regions are formed prior to formation of the photoresist (negative-tone or positive-tone).
- FIGS. 4A-4D are pictorial representations illustrating a embodiment of the second method of the present invention in which a photoresist is used with a lift-off layer.
- This method of the present invention begins by providing the structure 60 shown in FIG. 4A.
- This structure includes substrate 12 that has two gate regions 16L and 16R, which are located on a surface of the semiconductor substrate 12.
- Each gate region, i.e., 16R and 16L includes a gate dielectric 18, a polySi gate conductor 20, a dielectric cap 22, spacers 24 and source/drain regions 14.
- the source/drain regions 14 are located within semiconductor substrate 12.
- a photoresist (either negative-tone or positive-tone) 52 is located atop the substrate 12 and the gate regions 16L and 16R.
- a lift-off layer 62 surrounds the gate regions 16L and 16R.
- the lift-off layer 62 is located around the gate stacks and beneath the photoresist.
- the lift-off layer 62 is a weakly adhering layer that is capable of detaching from the substrate in a chemical solvent.
- the materials above the lift-off layer are removed.
- the suicide metal is deposited on the exposed polySi gate conductor and thereafter the remaining lift-off layer and photoresist are removed.
- the initial structure shown in FIG. 4A is fabricated using the techniques described above in the first embodiment for fabricating structure 10 shown in FIG. 2A as well as the processing techniques described in connection with fabricating the structure shown in FIG. 3 B.
- a difference in the structure shown in FIG. 4 A is that a lift-off layer 62 is formed surrounding each gate stack prior to applying the photoresist.
- the lift-off layer 62 is formed utilizing known deposition processes such as a spin-on process.
- the thickness of the lift-off layer 62 may vary depending on the material employed as well as the thickness of photoresist 52.
- the lift ⁇ off layer 62 has a thickness from about 50 to about 200 nm, with a thickness from about 100 to about 150 nm being more typical. Common lift-off materials are known to those skilled in the art.
- Photoresist 52 is then applied and the photoresist 52 is thereafter exposed and developed as described above in the second method providing openings that expose the lift-off layer 62 that is located on the upper surface layer of each dielectric cap 22. After exposing the lift-off layer 62 on each gate region, the exposed lift-off layer 62 is removed exposing an underlying surface of the dielectric cap 22. See FIG. 4B. The exposed dielectric cap 22 is then removed from the structure utilizing the dry etching process described in the second method of the present invention that selectively removes the dielectric cap 22 as compared to the photoresist 52. The structure is shown, for example, in FIG. 4C.
- the photoresist 52 is removed from the structure utilizing a conventional lift-off process that is well known in the art.
- the lift-off process may include a wet etch process that detaches the remaining lift-off layer 62 not previously removed. Processing as described above, i.e., silicidation of the gate, now takes place.
- the metal suicide can be formed on the exposed polySi gate conductor prior to the lift-off procedure. This avoids the need of utilizing a selective wet etch process during the silicidation step since no metal suicide is present on other areas of the structure besides the polySi gate conductor. There is no need to suicide prior to lift-off because after the lift-off process the suicide metal is only present on top of the polySi gate.
- the suicided source and drain regions can be formed prior to forming the lift ⁇ off layer 62 and the photoresist 52 on the structure or after suicide metal gate formation.
- FIGS. 5A-5I A third method of the present invention is shown in FIGS. 5A-5I.
- a lithography level is used to provide precise alignment to the gate level.
- FIG. 5A shows an initial structure 70 that is employed in this embodiment of the present invention.
- Initial structure 70 includes substrate 12 that has two gate regions 16L and 16R, which are located on a surface of the semiconductor substrate 12.
- Each gate region, i.e., 16R and 16L includes a gate dielectric 18, a polySi gate conductor 20, a dielectric cap 22, spacers 24 and source/drain regions 14.
- the source/drain regions 14 are located within semiconductor substrate 12.
- the initial structure shown in FIG. 5A is fabricated using the techniques described above in the first method for fabricating structure 10 shown in FIG. 2A except that the dielectric liner 23 is not present.
- a planarizing material 72 such as BSG, PSG or an oxide is applied to the initial structure 70.
- the planarizing material 70 in this embodiment of the present invention is an organic material.
- the planaiizing material 72 is formed as described in the first method of the present invention.
- a masking layer 74 such as an oxide is then formed atop the planarizing material 72 utilizing a conventional deposition process.
- Masking layer 74 typically has a thickness after deposition from about 25 to about 75 nm.
- the masking layer 74 is then patterned by lithography and etching. These steps are shown in FIGS. 5D-5F.
- FIG. 5D shows the structure after a photoresist 76 is formed atop the masking layer.
- FIG. 5E shows the structure after photoresist 76 has been patterned via exposure and development
- FIG. 5F shows the structure after the pattern is transferred from the photoresist 76 into the masking layer 74.
- the transfer of the pattern occurs by an etching process such as reactive-ion etching or another like dry etching process.
- the pattern is transferred into the planarizing material 72 by a dry etching process that also consumes the photoresist 76.
- a dry etching process that also consumes the photoresist 76.
- RIE reactive ion etching
- this step exposes the top surface of the dielectric cap 22.
- the dielectric cap 22 and the remaining masking layer 74 is then removed utilizing a dry etching process as described above in the second method of the present invention providing the structure shown in FIG. 5H.
- the underlying polySi gate conductor 20 is exposed.
- the remaining planarizing material 72 is then stripped and processing of the fully suicided metal gate and suicided source/drain regions can be performed as described above. Alternatively, the suicided source/drain regions can be formed prior to forming the planarizing material 72 on the structure.
- a lift-off layer as described above can also be employed in this method as well.
- FIG. 51 shows the structure after planarizing material 72 has been removed.
- FIGS 6A-6D show how the planarizing material 72 protects the underlying material and circumvents the CD bias and misalignment inherent to lithography and dry etching methods as is known to those skilled in the art. Note that the elements in these drawings are the same as that shown in FIGS. 5A-5I. The significance of the process shown in FIGS. 6A-6D is that even in the event of increased CD or overlay mismatch the source and drain regions and the trench isolation regions are still protected. Note that the structure shown in FIG. 6D can be processed as described above such that a fully suicided metal gate and suicided source/drain regions are formed therein.
- FIGS. 7A-7E and FIGS. 8A-8F show embodiments in which a lift-off layer 78 is used in conjunction with planarizing material 72.
- Layer 78 is a lift-off layer. Note that lift-off layer 78 is the same material as lift-off layer 62 depicted in the previous drawings.
- FIGS. 7A-7E illustrate how a planarizing organic scheme such as shown in FIGS. 5A-5I can be used in conjunction with a lift-off layer, hi these drawings, the lift-off layer 78, the planarizing organic layer 72, a stack comprising a first hard mask 73 and a second hard mask 74 are employed and are deposited in the order indicated. Resist 76 is then applied and patterned. The resist pattern is first transferred into the hard mask stack and thereafter into the planarizing organic layer 72 while at the same time consuming photoresist 76. The lift-off layer 78 above the dielectric cap and the underlying dielectric cap 22 are then removed as described above. A metal suicide, labeled as 90 in the drawings, is then applied atop the exposed surface of the dielectric cap and then the remaining lift-off layer and material layers above the lift-off layer are removed. At least one suicide anneal is then performed.
- a metal suicide labeled as 90 in the drawings
- FIGS. 8A-8F describe a different embodiment where the planarizing organic layer 72 can be slightly undercut through an isotropic etch after the dielectric cap 22 has been removed. This embodiment would make the lift-off process more robust.
- liner 23 can be employed. Also, in embodiments in which a photoresist is employed, lift ⁇ off technology can be used.
- the various methods of the present invention provide a MOS structure having folly suicided metal gates and abutting suicided source/drain regions in which the suicided source drains regions have a thickness that is thinner than the fully suicided metal gates.
- the thickness of the suicided metal gates is greater than 500 A and the thickness of the suicided source/drain regions is less than 500 A, preferably less than 300 A, and even more preferably less than 200 A.
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Abstract
An advanced gate structure that includes a fully silicided metal gate (30) and silicided source and drain regions (32) in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.
Description
METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES
[0001] The present invention relates to a semiconductor device and methods of fabricating the same, and more particularly to a metal oxide semiconductor (MOS) device that includes an advanced gate structure, e.g., fully suicided metal gate, as well as methods of fabricating the rally suicided metal gate device.
Background of the Invention
[0002] Throughout the prior art, metal gate integration has proven difficult to achieve in a conventional process flow for MOS transistors. Most metal gate materials interact with the gate dielectric during the high temperature processing needed for source/drain (S/D) junction activation anneals. The need to keep the metal gate stack from receiving high temperature anneals has lead to the development of the "gate last" or "replacement gate" process for which the gate stack is fabricated last and remains below 500°C during subsequent processing. Although the prior art replacement gate process increases the number of material choices for a metal gate, the process complexity and cost increases.
[0003] It is known in the prior art to form self-aligned suicided metal gates from a polysilicon gate using the processing steps shown, for example, in FIGS. 1 A-ID. Specifically, the prior art process begins with providing the structure shown in FIG. IA, which structure includes a semiconductor substrate 12, an isolation region 15, gate regions 16L and 16R, a gate dielectric 18, a polySi gate conductor 20 and a cap layer 22. Spacers 24 are located on each gate region as well. As shown, the source/drain implants are performed with the cap layer 22 atop the polySi conductor 20. Next, the cap layer 22 is non-selectively removed, as shown in FIG. IB, and then a suicide metal 105 such as Ni is deposited on the entire structure providing the structure shown in FIG. 1C. An optional oxygen diffusion barrier layer can be formed atop the suicide metal and then annealing is performed to cause reaction between the polySi and suicide metal. Depending on the metal, a low resistivity suicide can be formed utilizing a single anneal. After the single anneal, any
unreacted metal and the optional oxygen diffusion barrier is removed, and if needed, a second anneal may be performed. FIG. ID shows the structure after the salicide process in which suicided source/drain regions 100 and metal suicide gate 102 are formed. In this prior art process, gate and source/drain silicidation occurs simultaneously.
[0004] As shown, this prior art process forms thick metal suicide gates and thick source/drain suicides, each having a thickness of approximately 100 nm. This can be problematic for a few reasons. Firstly, the suicide can extend underneath the gate and short the device. Secondly, such a thick source/drain suicide can also be problematic given the recess of the isolation regions of the device caused by the non¬ selective removal of the cap layer from the gate. Specifically, the suicide in this prior art process can short across devices separated by narrow isolation regions. Thirdly, the thick suicide may consume the silicon in the extension regions under the spacers leading to poor device performance. Hence, methods that produce a thick and fully suicided metal gate and a much thinner source/drain suicide are needed. In addition, the suicide in this prior art process can also contact the implanted well regions of the device thereby shorting the device.
Summary of the Invention
[0005] The present invention relates to an advanced gate structure that includes a fully suicided metal gate and suicided source and drain regions that abut the suicided metal gate. Specifically, and in broad terms, the present invention provides a semiconductor structure comprising a fully suicided metal gate of a first suicide metal having a first thickness and abutting suicided source and drain regions of a second metal having a second thickness, wherein said second thickness is less than the first thickness and said suicided source and drain regions are aligned to edges of a gate region including at least the fully suicided metal gate.
[0006] In accordance with the present invention, the thick fully suicided metal gate and the thinner suicided source and drain regions can be composed of the same or different metal suicide such as, for example, suicides of Ti, Ta, W, Co, Ni, Pt, Pd and
alloys thereof. Of the various suicides, suicides of Co, Ni or Pt, in their lowest resistivty phase, are particularly preferred. In a highly preferred embodiment of the present invention, the source and drain regions include CoSi2, while the suicided metal gate includes NiSi and/or NiPtSi. In another preferred embodiment of the present invention, the source and drain suicides comprise NiSi, while the suicided metal gate comprises NiSi and/or NtPtSi.
[0007] A metal oxide semiconductor (MOS) device is provided that comprises a semiconductor substrate having suicided source and drain regions located on a surface thereof, said suicided source and drain regions having a thickness of less than 500 A and are self-aligned to an edge of a gate region that includes a fully suicided metal gate having a thickness of greater than 500 A.
[0008] In addition to the structure described above, the present invention also provides methods for forming the advanced gate structure having the thick and fully suicided metal gate and the thinner suicided source and drain regions abutting the suicided metal gate. In one method of the present invention, the following processing steps are employed in fabricating the inventive structure:
[0009] providing a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, a dielectric liner on at least sidewalls of said polysilicon gate conductor, and spacers on said dielectric liner and adjoining sidewalls of at least the polysilicon gate conductor;
[0010] depositing a material stack comprising a conformal dielectric layer and a planarizing dielectric layer on the structure including atop the at least one patterned gate stack;
[0011] removing portions of the conformal dielectric layer and planarizing dielectric layer to expose said dielectric cap;
[0012] removing the dielectric cap to expose the polysilicon gate conductor;
[0013] converting the polysilicon gate conductor into a fully suicided metal gate;
[0014] exposing said source and drain regions; and
[0015] saliciding said source and drain regions to form suicided source and drain regions that have a thickness that is less than the fully suicided metal gate.
[0016] In some embodiments of the method described above, the suicided source/drain regions are formed prior to forming the material stack over the structure. In particular, when the suicided source/drain regions are formed before the suicide metal gate, they are formed after forming the spacer in the structure obtained in the providing step.
[0017] A second method of forming the inventive semiconductor structure is also provided. The second method employs a photoresist (negative-tone or positive-tone) and a dry etching process to selectively remove the dielectric cap. Specifically, and in broad terms, the second method of the present invention comprises the steps of:
[0018] providing a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, and spacers on adjoining sidewalls of at least the polysilicon gate conductor;
[0019] forming a patterned photoresist atop the structure including said at least one patterned gate stack, said patterned photoresist containing an opening that exposes said dielectric cap;
[0020] selectively removing the dielectric cap utilizing a dry etching process to expose the polysilicon gate conductor;
[0021] removing the patterned photoresist;
[0022] converting the polysilicon gate conductor into a fully suicided metal gate; and
[0023] saliciding said source and drain regions to form suicided source and drain regions that have a thickness that is less than the fully suicided metal gate.
[0024] In some embodiments of the second method described above, the suicided source/drain regions are formed prior to forming the photoresist over the structure. In particular, when the suicided source/drain regions are formed before the suicide metal gate, they are formed after forming the spacer in the structure obtained in the providing step. In the second embodiment of the present invention, the photoresist can be either a negative-tone photoresist or a positive-tone photoresist.
[0025] In some embodiments of the second method of the present invention, a lift-off layer is formed surrounding the gate regions and then the patterned photoresist is formed. After removing the dielectric cap, the patterned photoresist above the lift-off layer, together with the lift-off layer, are removed from the structure.
[0026] Another method of the present invention includes the use of a lithography level to provide precise alignment to the gate level. This third method of the present invention comprises:
[0027] providing a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, and spacers on adjoining sidewalls of least the polysilicon gate conductor;
[0028] depositing a stack comprising a planarizing material, a masking layer and a photoresist on the structure including atop the at least one patterned gate stack;
[0029] patterning the stack to expose the dielectric cap;
[0030] selectively removing the dielectric cap utilizing a dry etching process to expose the polysilicon gate conductor;
[0031] removing the stack;
[0032] converting the polysilicon gate conductor into a fully suicided metal gate; and
[0033] saliciding said source and drain regions to form suicided source and drain regions that have a thickness that is less than the fully suicided metal gate.
[0034] In some embodiments of the third method described above, the suicided source/drain regions are formed prior to forming the stack over the structure. In particular, when the suicided source/drain regions are formed before the suicide metal gate, they are formed after forming the spacer in the structure obtained in the providing step. A lift-off layer can also be used in the third method of the present invention. The lift-off layer is formed on the exposed surface of the patterned gate stack prior to patterning the stack of planarizing material, masking layer and photoresist.
Brief Description of the Drawings
[0035] FIGS. IA- ID are pictorial representations (through cross-sectional views) depicting a prior art process of fabricating self-aligned suicided metal gates from a polysilicon gate.
[0036] FIGS. 2A-2G are pictorial representations (through cross-sectional views) illustrating the basic processing steps employed in a first method of the present invention.
[0037] FIGS. 3A-3E are pictorial representations (through cross-sectional views) illustrating the basic processing steps employed in a second method of the present invention.
[0038] FIGS. 4A-4D are pictorial representations (through cross-sectional views) illustrating an embodiment of the second method of the present invention in which a photoresist is used with a lift-off layer.
[0039] FIGS. 5A-5I are pictorial representations (through cross-sectional views) illustrating a third method of the present invention in which a lithography level is used to provide precise alignment to the gate level.
[0040] FIGS. 6A-6D are pictorial representations (through cross-sectional views) illustrating how a planarizing layer protects the underlying material and circumvents critical dimension (CD) biasing and misalignment inherent to lithography.
[0041] FIGS. 7A-7E are pictorial representations (through cross-sectional views) illustrating one lift-off scheme that can be used in conjugation with a planarizing layer.
[0042] FIGS. 8A-8F are pictorial representations (through cross-sectional views) illustrating another lift-off scheme that can be used in conjugation with a planarizing layer.
Detailed Description of the Invention
[0043] The present invention, which provides a MOS device that has a fully suicided gate and thin suicided source and drain regions (relative to the gate and prior art suicided source/drain regions) as well as methods of fabricating the same, will now be described in greater detail by referring to the drawings which accompany the present application. In the accompanying drawings, which are not drawn to scale, like and/όr corresponding elements are referred to by like reference numerals.
[0044] It is noted that in the drawings two MOS device regions are shown to be formed atop a single semiconductor substrate. Although illustration is made to such an embodiment, the present invention is not limited to the formation of any specific number of MOS devices on the surface of the semiconductor structure. Instead, the
method of the present invention forms at least one fully suicided MOS device on a surface of a semiconductor substrate.
[0045] Reference is first made to structure 10 that is illustrated in FIG. 2A. Structure 10 includes a semiconductor substrate 12 that has two gate regions 16L and 16R, which are located on a surface of the semiconductor substrate 12. Each gate region, i.e., 16R and 16L, includes a gate dielectric 18, a polySi conductor 20, a dielectric cap 22, dielectric liner 23, spacers 24 and source/drain regions 14. The source/drain regions 14 are located within semiconductor substrate 12.
[0046] The semiconductor substrate 12 of structure 10 comprises any semiconducting material including, but not limited to: Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, InAs, InP and all other III/V compound semiconductors. Semiconductor substrate 12 may also comprise an organic semiconductor or a layered semiconductor such as Si/SiGe, a silicon-on-insulator (SOI) or a SiGe-on-insulator (SGOI). In some embodiments of the present invention, it is preferred that the semiconductor substrate 12 be composed of a Si-containing semiconductor material, i.e., a semiconductor material that includes silicon. The semiconductor substrate 12 maybe doped, undoped or contain doped and undoped regions therein.
[0047] The semiconductor substrate 12 may also include a first doped (n- or p-) region, and a second doped (n- or p-) region. For clarity, the doped regions are not specifically labeled in the drawings of the present application. The first doped region and the second doped region may be the same, or they may have different conductivities and /or doping concentrations. These doped regions are known as "wells".
[0048] Trench isolation regions (not specifically shown) are typically already formed in the semiconductor substrate at this point of the present invention utilizing conventional processes well known to those skilled in the art. The trench isolation regions are located to the periphery of the region shown in the drawings of the present invention as well as between the two gate regions depicted.
[0049] A gate dielectric 18 is formed on the entire surface of the structure 10 including the semiconductor substrate 12 and atop the isolation region, if it is present and if it is a deposited dielectric. The gate dielectric 18 can be formed by a thermal growing process such as, for example, oxidation, nitridation or oxynitridation. Alternatively, the gate dielectric 18 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition and other like deposition processes. The gate dielectric 18 may also be formed utilizing any combination of the above processes.
[0050] The gate dielectric 18 is comprised of an insulating material including, but not limited to: an oxide, nitride, oxynitride and/or silicate including metal silicates and nitrided metal silicates, hi one embodiment, it is preferred that the gate dielectric 18 is comprised of an oxide such as, for example, SiO2, HfO2>ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, and mixtures thereof.
[0051] The physical thickness of the gate dielectric 18 may vary, but typically, the gate dielectric 18 has a thickness from about 0.5 to about 10 nm, with a thickness from about 0.5 to about 3 nm being more typical.
[0052] After forming the gate dielectric 18, a blanket layer of polysilicon (i.e., polySi) which becomes the polySi gate conductor 20 shown in FIG. 2A is formed on the gate dielectric 18 utilizing a known deposition process such as, for example, physical vapor deposition, CVD or evaporation. The blanket layer of polysilicon may be doped or undoped. If doped, an in-situ doping deposition process may be employed in forming the same. Alternatively, a doped polySi layer can be formed by deposition, ion implantation and annealing. The doping of the polySi layer will shift the workfunction of the suicided metal gate formed. Illustrative examples of dopant ions include As, P, B, Sb, Bi, In, Al, Ga, Tl or mixtures thereof. Typical doses for the ion implants are 1E14 (=lxlθ14) to 1E16 (=lxlθ16) atoms/cm2 or more typically 1E15 to 5E15 atoms/cm2. The thickness, i.e., height, of the polysilicon layer deposited at this point of the present invention may vary depending on the deposition process employed. Typically, the polysilicon layer has a vertical thickness from
about 20 to about 180 nm, with a thickness from about 40 to about 150 nm being more typical.
[0053] After deposition of the blanket layer of polysilicon, a dielectric cap 22 is formed atop the blanket layer of polysilicon gate conductor 20 utilizing a deposition process such as, for example, physical vapor deposition or chemical vapor deposition. The dielectric cap 22 may be an oxide, nitride, oxynitride or any combination thereof. The dielectric cap 22 can be comprised of a different dielectric material than spacer 24 to be defined in detail herein below. In one embodiment, a nitride such as, for example, Si3N4, is employed as the dielectric cap 22. In yet another embodiment, which is preferred, the dielectric cap 22 is an oxide such as SiO2. The thickness, i.e., height, of the dielectric cap 22 is from about 20 to about 180 nm, with a thickness from about 30 to about 140 nm being more typical.
[0054] The blanket polysilicon layer and dielectric cap layer are then patterned by lithography and etching so as to provide patterned gate stacks. The patterned gate stacks may have the same dimension, i.e., length, or they can have variable dimensions to improve device performance. Each patterned gate stack at this point of the present invention includes a polySi gate conductor 20 and dielectric cap 22. The lithography step includes applying a photoresist to the upper surface of the dielectric cap layer, exposing the photoresist to a desired pattern of radiation and developing the exposed photoresist utilizing a conventional resist developer. The pattern in the photoresist is then transferred to the dielectric cap layer and the blanket layer of polysilicon utilizing one or more dry etching steps. In some embodiments, the patterned photoresist may be removed after the pattern has been transferred into the dielectric cap layer. In other embodiments, the patterned photoresist is removed after etching has been completed.
[0055] Suitable dry etching processes that can be used in the present invention in forming the patterned gate stacks include, but are not limited to: reactive ion etching, ion beam etching, plasma etching or laser ablation. The dry etching process employed is typically selective to the underlying gate dielectric 18 therefore this etching step does not typically remove the gate dielectric. In some embodiments, this
etching step may however be used to remove portions of the gate dielectric 18 that are not protected by the gate stacks. A wet etching process can also be used to remove portions of the gate dielectric 18 that are not protected by the gate stacks.
[0056] Next, a dielectric liner 23 is formed on all exposed surfaces containing silicon including at least the polysilicon gate conductor 20. The dielectric liner 23 can also extend onto a horizontal surface of the semiconductor substrate 12, as is shown in FIG. 2A. The dielectric liner 23 may comprise any dielectric material that contains an oxide, nitride, oxynitride or any combination thereof. The dielectric liner 23 is formed via a thermal growing process such as oxidation, nitridation or oxynitridation. In accordance with the present invention, the dielectric liner 23 is a thin layer whose thickness is typically from about 1 to about 10 nm.
[0057] At least one spacer 24 is formed on exposed sidewalls of each patterned gate stack as well as atop the dielectric liner. The at least one spacer 24 is comprised of an insulator such as an oxide, nitride, oxynitride and/or any combination thereof and it typically is composed of a different material than the dielectric liner 23 and the dielectric cap 22. Preferably, nitride spacers are formed. The at least one spacer 24 is formed by deposition and etching. Note that the etching step used in forming the spacers 24 also can remove dielectric liner 23 from atop the substrate such that a portion of the semiconductor substrate 12 is exposed. The exposed portion of the semiconductor substrate 12 is labeled as reference numeral 11 in FIG. 2A.
[0058] The width of the at least one spacer 24 must be sufficiently wide enough such that the source and drain suicide contacts (to be subsequently formed) do not encroach underneath the edges of the gate stack. Typically, the source/drain suicide does not encroach underneath the edges of the gate stack when the at least one spacer has a width, as measured at the bottom, from about 15 to about 80 nm.
[0059] After spacer formation, source/drain diffusion regions 14 are formed into the substrate 12 at the exposed portion 11. The source/drain diffusion regions 14 are formed utilizing ion implantation and an annealing step. The annealing step serves to activate the dopants that were implanted by the previous implant step. The
conditions for the ion implantation and annealing are well known to those skilled in the art.
[0060] Next, and as shown in FIG. 2B, a material stack comprising a conformal dielectric layer 26 and a planarizing dielectric 28 is formed over the entire structure shown in FIG. 2A. In accordance with the present invention, the conformal dielectric layer 26 is formed first followed by the planarizing dielectric layer 28. The conformal dielectric layer 26 comprises any dielectric material including an oxide, nitride, and/or oxynitride. Specifically, the conformal dielectric layer 26 comprises a nitride such as Si3N4. The conformal dielectric layer, which is formed utilizing a conventional deposition process, has a thickness after deposition from about 15 to about 80 run.
[0061] After forming the conformal dielectric layer 26 over the structure shown in FIG. 2A, the planarizing dielectric layer 28 is formed. The planarizing dielectric layer 28 comprises an oxide such as a high density oxide or an oxide deposited from TEOS. Alternatively, the planarizing dielectric layer 28 may comprise a doped silicate glass, such as boron doped silicate glass (BSG) or phosphorus doped silicate glass (PSG), a spin-coatable polymeric material such as hydrogen silsesquioxane (HSQ), or a photoresist. The planarizing dielectric layer 28 is formed by conventional techniques well known to those skilled in the art. The thickness of the planarizing dielectric layer 28 formed at this point of the present invention may vary depending on the type of material employed. Typically, the planarizing dielectric layer 28 has a thickness from about 50 to about 100 nm. hi accordance with the present invention, the planarizing layer atop the gate stacks is less than the thickness of the same over the source/drain regions and the trench isolation regions.
[0062] FIGS. 2C and 2D represent various embodiments that can be employed in the present invention to expose dielectric cap 22. FIG. 2C shows an embodiment in which an etch back process is employed, while FIG. 2D shows an embodiment in which a chemical mechanical polishing (CMP) process is employed. The etch back process comprises at least one timed etching process that can selectively remove portions of both the planarizing dielectric layer 28 and the conformal dielectric layer
26 which extend above an upper surface of the dielectric cap 22. In some embodiments, a portion of the planarizing dielectric layer 28 is first etched back and then a portion of the conformal dielectric layer 26 is etched back using different etching processes. An example of an etching process that can be used in forming the structure shown in FIG. 2C comprises a dry etch process that first etches oxide selective to nitride followed by a dry etch process that etches nitride selective to oxide. The CMP process used in forming the structure shown in FIG. 2D is conventional and well known to those skilled in the art.
[0063] Notwithstanding which technique (e.g., etch back or CMP) is employed, the resultant structure after etching back or CMP has the dielectric cap 22 exposed. Although both embodiments can be used in the present invention, the following drawings illustrate the structure which has been subjected to the etch back process. It is noted that the structure that has been planarized by CMP can also undergo the following processes.
[0064] The exposed dielectric cap 22 is removed from each gate region 16L and 16R. so that the underlying polysilicon gate conductor 20 is exposed. The resultant structure that is formed after this step has been performed is shown, for example, in FIG. 2E. The dielectric cap 22 is removed in the present invention by utilizing an etching process, wet or dry, which removes the dielectric cap material from the structure. Although a dry etching process such as reactive-ion etching (RIE), ion beam etching (IBE), and plasma etching can be employed, it is preferred that a wet etch process be employed in removing the dielectric cap 22. An example of a wet etch process that can be used to remove the dielectric cap 22 includes dilute hydrofluoric acid (DHF). In embodiments in which the dielectric cap 22 and the planarizing dielectric layer 28 are composed of oxides, this step also removes the remaining planarizing dielectric layer 28 between the gate regions. This is shown in FIG. 2E as well. In this instance, the remaining portion of the conformal dielectric layer 26 protects the portion of the substrate containing the source/drain regions 14.
[0065] After etching the cap dielectric 22 from atop the polySi gate conductor 20, a first salicide process is performed to consume the polySi gate conductor 20 forming
folly suicided metal gates 30. The first salicide process is exemplified in FIG. 2F. The first step of the first salicide process includes depositing a blanket suicide metal atop the structure shown in FIG. 2E. The suicide metal can be deposited using any conventional deposition process including, for example, sputtering, chemical vapor deposition, evaporation, chemical solution deposition, plating and the like. The suicide metal can be the same or different than the metal used in forming the suicided source/drain regions (to be subsequently formed and described).
[0066] The suicide metal can be composed of at least one of Ti, Hf, Ta, W, Co, Ni, Pt, Pd or alloys thereof. In one embodiment, the suicide metal is Co; CoSi2 forms using a two step annealing process. In another embodiment of the present invention, the suicide metal is Ni or Pt; NiSi and PtSi form using a single annealing step.
[0067] The suicide metal thickness is selected so as to form the suicide phase with the appropriate workfunction for the particular MOS device and to consume all of the polySi gate conductor 20. For example, NiSi has a workfunction of 4.65 eV, and if the initial polysilicon height is 50 nm, the amount of Ni needed is about 27 nm. CoSi2 has a workfunction of 4.45 eV, and if the initial polysilicon height is 50 nm, the amount of Co needed is about 14 nm. Although the suicide metal thicknesses given are the amount necessary to just consume the polysilicon, it is preferred if the thickness were in excess by about 10% to make sure consumption is complete.
[0068] In some embodiments (not shown), an oxygen diffusion barrier such as TiN or W is formed atop the silicide metal prior to annealing.
[0069] Specifically, the salicide annealing includes a first anneal which is employed to form a first silicide phase in the structure; the first silicide phase may or may not represent the lowest resistivity phase of a metal silicide. The first anneal is typically performed at lower temperatures than the second annealing step. Typically, the first annealing step, which may, or may not, form a high resistance silicide phase material, is performed at a temperature from about 300° to about 6000C using a continuous heating regime or various ramp and soak heating cycles. More preferably, the first annealing step is performed at a temperature from about 350° to about 5500C.
[0070] The salicide anneals (first and second) are carried out in a gas atmosphere, e.g., He, Ar, N2 or forming gas. The gate suicide annealing steps may use different atmospheres or the annealing steps may be carried out in the same atmosphere. For example, He may be used in both annealing steps, or He can be used in the first annealing step and a forming gas may be used in the second annealing step.
[0071] Next, a selective wet etch step is employed to remove any non-reactive suicide metal from the structure. For some metal suicides, the salicide process may be stopped at this point since the polysilicon is consumed and the resistivity of the first suicide phase is close to minimum values for the phase. This is in the case for Ni and Pt. hi other cases, for example when Co or Ti are used as the suicide metal, a second higher temperature anneal is needed for the consumption of the remaining polysilicon and forming a second suicide phase material. In this embodiment, the first silicide phase is a high resistivity phase suicide material, while the second suicide phase material is a lower resistivity phase silicide material.
[0072] The second annealing step is performed at a temperature from about 6000C to about 8000C using a continuous heating regime or various ramp and soak heating cycles. More preferably, the second annealing step is performed at a temperature from about 6500C to about 750 0C.
[0073] FIG. 2F shows the structure after formation of fully suicided metal gates 30. The fully suicided metal gates 30 are located atop the gate dielectric 18 between spacers 24 in an area previously occupied by the polySi gate conductor 20.
[0074] In some embodiments of the present invention and if not previously done, the remaining portions of the planarizing dielectric layer 28 between the gate regions is removed utilizing a selective etching process. The remaining portions of the conformal dielectric layer 26 between each gate region is then removed utilizing an etching process that selectively etches the conformal dielectric material from the structure. This step of the present invention exposes the portion of the substrate 12 containing source/drain regions 14.
[0075] Source and drain suicide contacts 32 (hereinafter source/drain suicides) are then formed using a salicide process which includes the steps of depositing a suicide metal on an exposed surface of the substrate 12 that includes the source/drain diffusion regions 11, optionally depositing an oxygen diffusion barrier material such as TiN on the suicide metal, first annealing to form a suicide, selective etching any non-reacted metal including barrier material if used and, if needed, performing a second annealing step. The step of the present invention is shown in FIG. 2G.
[0076] When the semiconductor substrate does not comprise silicon, a layer of silicon (not shown) can be grown atop the exposed surface of the semiconductor substrate 12 and can be used in forming the source/drain suicide contacts.
[0077] The suicide metal used in forming the source/drain suicides 32 comprises any metal that is capable of reacting with silicon to form a metal suicide. If the substrate does not include silicon, then the metal suicide needs to comprise a metal that will form a suicide with other substrate materials, e.g., Ni for a SiGe surface. Examples of such metals include, but are not limited to: Ti, Ta, W, Co, Ni, Pt, Pd and alloys thereof. In one embodiment, Co is a preferred metal. In such an embodiment, the second annealing step is required. In another embodiment, Ni or Pt is preferred. In this embodiment, the second annealing step is typically not performed.
[0078] The suicided source/drain regions 32 can be formed utilizing the conditions described above in forming the suicided gate. The source/drain suicides, i.e., suicided source/drain regions, 32, which are formed utilizing the above-mentioned process, are self-aligned to edges of the gate region 16R or 16L. In particular, the outer edges of the suicided source/drain regions 32 are aligned with edges of the dielectric liner 23 and spacer 24. The suicided source/drain regions 32 have a thickness (measured vertically) of less than 50 nm, with a thickness from about 15 to about 30 nm being more typical.
[0079] hi the process of the present invention, the suicided metal used in forming the suicided source/drain regions and the suicided metal gate may include an alloying
additive that can enhance the formation of the metal suicide. Examples of alloying additives that can be employed in the present invention include, but are not limited to: C, Al, Ti, V, Cr, Mn5 Fe, Co, Ni, Cu, Ge, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Hf, Ta, W, Re, Ir, Pt or mixtures thereof, with the proviso that the alloying additive is not the same as the material used in forming the suicide. When present, the alloying additive is present in an amount from about 0.1 to about 50 atomic percent. The alloying additive may be introduced as a dopant material to the suicide metal layer or it can be a layer that is formed atop the suicide metal layer prior to annealing.
[0080] It should be noted that although the above describes an initial structure that does not include raised source/drain regions, the present invention also contemplates the presence of raised source/drain regions in the initial structure. The raised source/drain regions are formed utilizing conventional techniques well known to those skilled in the art. Specifically, the raised source/drain regions are formed by depositing any Si-containing layer, such as epi Si, amorphous Si, SiGe, and the like, atop the substrate prior to implanting the source/drain regions.
[0081] In addition to the embodiment described above in which the suicided source/drain regions are formed after the suicided metal gate, the present invention also contemplates an embodiment in which the suicided source/drain regions are formed prior to the suicided metal gate. In such an embodiment, the suicided source/drain regions can be formed after spacer 24 formation, prior to forming conformal dielectric layer 26 over the structure.
[0082] Reference is now made to FIGS. 3A-3E which show a second method of the present invention. In this second method a photoresist (negative-tone or positive- tone) and dry etching are employed to remove the dielectric cap 22 that lies atop the polysilicon gate conductor 20. Specifically, the second method begins with first providing the structure 50 shown in FIG. 3A. The structure 50 is similar to the structure 10 shown in FIG. 2A except that no dielectric liner 23 is present. Although, no dielectric liner 23 is shown, the present invention contemplates an embodiment in which the same is present. The structure 50 shown in FIG. 3A comprises substrate 12 that has two gate regions 16L and 16R, which are located on a surface of the
semiconductor substrate 12. Each gate region, i.e., 16R and 16L, includes a gate dielectric 18, a polySi gate conductor 20, a dielectric cap 22, spacers 24 and source/drain regions 14. The source/drain regions 14 are located within semiconductor substrate 12.
[0083] The initial structure shown in FIG. 3 A is fabricated using the techniques described above in the first embodiment for fabricating structure 10 shown in FIG.
2A.
[0084] In accordance with the second embodiment of the present invention, a negative-tone photoresist (or alternatively a positive-tone photoresist) 52 is then formed over the entire structure providing the structure shown in FIG. 3B. The term "negative-tone photoresist" denotes a photoresist that remains in areas that were not protected from exposure by opaque regions of a mask, while being removed by the developer in regions that were protected. Hence, the unexposed regions of the photoresist remain after development and thus the negative image of a mask remains. The negative-tone photoresist 52 employed in the present invention thus includes any photoresist material which when exposed to light changes from a soluble condition to an insoluble condition. Such negative-tone resists are conventional and well known to those skilled in the art.
[0085] In addition to negative-tone photoresists, the present invention also contemplates using positive-tone photoresists. The difference in using a positive- tone photoresist, as compared to a negative-tone photoresist, is that the exposed positive-tone photoresist becomes soluble when exposed to radiation. Hence, the exposed areas are developed and are removed. Such positive-tone photoresists are also well known to those skilled in the art. The use of the positive-tone photoresist does not alter the processing steps described below. The specific type of photoresist employed is dependent upon the polarity of the mask used, as is well known to those skilled in the art.
[0086] The photoresist 52 is applied to the structure shown in FIG. 3 A using a conventional deposition process such as spin-on coating that is well known to those
skilled in the art. The thickness of the applied photoresist 52 may vary so long as the upper surface thereof is above the upper surface of the dielectric cap 22.
[0087] FIG. 3 C shows the structure after exposing the photoresist to radiation and developing the areas of the photoresist 52 that are above each gate region 16L and 16R. The exposure and developing process include conventional lithography techniques that are well known to those skilled in the art. Note that in this structure the upper surface of each dielectric cap 22 atop the polySi gate conductor 20 is exposed.
[0088] Next, and as shown in FIG. 3D, the dielectric cap 22 is removed from the structure so that the underlying polySi gate conductor 20 is exposed, hi accordance with this embodiment of the present invention, the dielectric cap 22 is removed utilizing a dry etching process that selectively removes the dielectric cap as compared to the photoresist. For example, reactive ion etching, or laser beam etching ion beam etching can be used to selectively remove the dielectric cap 22.
[0089] Following the removal of the dielectric cap 22, the remaining photoresist 52 is removed from the structure providing the structure illustrated in FIG. 3E. The processing described above in forming the suicided metal gates and suicided source/drain regions is then performed. The resultant structure is similar to the one depicted in FIG. 2G except that the dielectric liner 23 is not necessarily present.
[0090] hi addition, the second embodiment also contemplates the case when the suicided source/drain regions are formed prior to formation of the photoresist (negative-tone or positive-tone).
[0091] Reference is now made to FIGS. 4A-4D, which are pictorial representations illustrating a embodiment of the second method of the present invention in which a photoresist is used with a lift-off layer. This method of the present invention begins by providing the structure 60 shown in FIG. 4A. This structure includes substrate 12 that has two gate regions 16L and 16R, which are located on a surface of the semiconductor substrate 12. Each gate region, i.e., 16R and 16L, includes a gate
dielectric 18, a polySi gate conductor 20, a dielectric cap 22, spacers 24 and source/drain regions 14. The source/drain regions 14 are located within semiconductor substrate 12. A photoresist (either negative-tone or positive-tone) 52 is located atop the substrate 12 and the gate regions 16L and 16R. A lift-off layer 62 surrounds the gate regions 16L and 16R.
[0092] Specifically, the lift-off layer 62 is located around the gate stacks and beneath the photoresist. The lift-off layer 62 is a weakly adhering layer that is capable of detaching from the substrate in a chemical solvent. As known to those skilled in the art, the materials above the lift-off layer are removed. Specifically, in the present invention, once the dielectric gap is removed, the suicide metal is deposited on the exposed polySi gate conductor and thereafter the remaining lift-off layer and photoresist are removed.
[0093] The initial structure shown in FIG. 4A is fabricated using the techniques described above in the first embodiment for fabricating structure 10 shown in FIG. 2A as well as the processing techniques described in connection with fabricating the structure shown in FIG. 3 B. A difference in the structure shown in FIG. 4 A is that a lift-off layer 62 is formed surrounding each gate stack prior to applying the photoresist. The lift-off layer 62 is formed utilizing known deposition processes such as a spin-on process. The thickness of the lift-off layer 62 may vary depending on the material employed as well as the thickness of photoresist 52. Typically, the lift¬ off layer 62 has a thickness from about 50 to about 200 nm, with a thickness from about 100 to about 150 nm being more typical. Common lift-off materials are known to those skilled in the art.
[0094] Photoresist 52 is then applied and the photoresist 52 is thereafter exposed and developed as described above in the second method providing openings that expose the lift-off layer 62 that is located on the upper surface layer of each dielectric cap 22. After exposing the lift-off layer 62 on each gate region, the exposed lift-off layer 62 is removed exposing an underlying surface of the dielectric cap 22. See FIG. 4B. The exposed dielectric cap 22 is then removed from the structure utilizing the dry etching process described in the second method of the present invention that
selectively removes the dielectric cap 22 as compared to the photoresist 52. The structure is shown, for example, in FIG. 4C.
[0095] Next, and as shown in FIG. 4D, the photoresist 52 is removed from the structure utilizing a conventional lift-off process that is well known in the art. For example, the lift-off process may include a wet etch process that detaches the remaining lift-off layer 62 not previously removed. Processing as described above, i.e., silicidation of the gate, now takes place. Alternatively, the metal suicide can be formed on the exposed polySi gate conductor prior to the lift-off procedure. This avoids the need of utilizing a selective wet etch process during the silicidation step since no metal suicide is present on other areas of the structure besides the polySi gate conductor. There is no need to suicide prior to lift-off because after the lift-off process the suicide metal is only present on top of the polySi gate.
[0096] The suicided source and drain regions can be formed prior to forming the lift¬ off layer 62 and the photoresist 52 on the structure or after suicide metal gate formation.
[0097] A third method of the present invention is shown in FIGS. 5A-5I. In this preferred method of the present invention, a lithography level is used to provide precise alignment to the gate level. FIG. 5A shows an initial structure 70 that is employed in this embodiment of the present invention. Initial structure 70 includes substrate 12 that has two gate regions 16L and 16R, which are located on a surface of the semiconductor substrate 12. Each gate region, i.e., 16R and 16L, includes a gate dielectric 18, a polySi gate conductor 20, a dielectric cap 22, spacers 24 and source/drain regions 14. The source/drain regions 14 are located within semiconductor substrate 12. The initial structure shown in FIG. 5A is fabricated using the techniques described above in the first method for fabricating structure 10 shown in FIG. 2A except that the dielectric liner 23 is not present.
[0098] Next, and as shown in FIG. 5B, a planarizing material 72 such as BSG, PSG or an oxide is applied to the initial structure 70. Preferably, the planarizing material 70 in this embodiment of the present invention is an organic material. The
planaiizing material 72 is formed as described in the first method of the present invention.
[0099] A masking layer 74 such as an oxide is then formed atop the planarizing material 72 utilizing a conventional deposition process. Masking layer 74 typically has a thickness after deposition from about 25 to about 75 nm. The masking layer 74 is then patterned by lithography and etching. These steps are shown in FIGS. 5D-5F. In particular, FIG. 5D shows the structure after a photoresist 76 is formed atop the masking layer. FIG. 5E shows the structure after photoresist 76 has been patterned via exposure and development, and FIG. 5F shows the structure after the pattern is transferred from the photoresist 76 into the masking layer 74. The transfer of the pattern occurs by an etching process such as reactive-ion etching or another like dry etching process.
[00100] Next, and as shown in FIG. 5G, the pattern is transferred into the planarizing material 72 by a dry etching process that also consumes the photoresist 76. For example, reactive ion etching (RIE) can be used to transfer the pattern into the planarizing material and consume the photoresist. Note that this step exposes the top surface of the dielectric cap 22.
[00101] The dielectric cap 22 and the remaining masking layer 74 is then removed utilizing a dry etching process as described above in the second method of the present invention providing the structure shown in FIG. 5H. During the removal of the dielectric cap 22, the underlying polySi gate conductor 20 is exposed. The remaining planarizing material 72 is then stripped and processing of the fully suicided metal gate and suicided source/drain regions can be performed as described above. Alternatively, the suicided source/drain regions can be formed prior to forming the planarizing material 72 on the structure. A lift-off layer as described above can also be employed in this method as well.
[00102] FIG. 51 shows the structure after planarizing material 72 has been removed.
[00103] FIGS 6A-6D show how the planarizing material 72 protects the underlying material and circumvents the CD bias and misalignment inherent to lithography and dry etching methods as is known to those skilled in the art. Note that the elements in these drawings are the same as that shown in FIGS. 5A-5I. The significance of the process shown in FIGS. 6A-6D is that even in the event of increased CD or overlay mismatch the source and drain regions and the trench isolation regions are still protected. Note that the structure shown in FIG. 6D can be processed as described above such that a fully suicided metal gate and suicided source/drain regions are formed therein.
[00104] FIGS. 7A-7E and FIGS. 8A-8F show embodiments in which a lift-off layer 78 is used in conjunction with planarizing material 72. The basic processing steps and materials used in these embodiments have been described in greater detail above. Therefore, there is no need to repeat the processing steps here. Layer 78 is a lift-off layer. Note that lift-off layer 78 is the same material as lift-off layer 62 depicted in the previous drawings.
[00105] FIGS. 7A-7E illustrate how a planarizing organic scheme such as shown in FIGS. 5A-5I can be used in conjunction with a lift-off layer, hi these drawings, the lift-off layer 78, the planarizing organic layer 72, a stack comprising a first hard mask 73 and a second hard mask 74 are employed and are deposited in the order indicated. Resist 76 is then applied and patterned. The resist pattern is first transferred into the hard mask stack and thereafter into the planarizing organic layer 72 while at the same time consuming photoresist 76. The lift-off layer 78 above the dielectric cap and the underlying dielectric cap 22 are then removed as described above. A metal suicide, labeled as 90 in the drawings, is then applied atop the exposed surface of the dielectric cap and then the remaining lift-off layer and material layers above the lift-off layer are removed. At least one suicide anneal is then performed.
[00106] FIGS. 8A-8F describe a different embodiment where the planarizing organic layer 72 can be slightly undercut through an isotropic etch after the dielectric
cap 22 has been removed. This embodiment would make the lift-off process more robust.
[00107] It should be noted that in the various embodiments described above, liner 23 can be employed. Also, in embodiments in which a photoresist is employed, lift¬ off technology can be used.
[00108] As indicated above, the various methods of the present invention provide a MOS structure having folly suicided metal gates and abutting suicided source/drain regions in which the suicided source drains regions have a thickness that is thinner than the fully suicided metal gates. Specifically, the thickness of the suicided metal gates is greater than 500 A and the thickness of the suicided source/drain regions is less than 500 A, preferably less than 300 A, and even more preferably less than 200 A.
[00109] While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims
1. A semiconductor structure comprising a folly suicided metal gate of a first suicide metal having a first thickness and abutting suicided source and drain regions of a second metal having a second thickness, wherein said second thickness is less than the first thickness and said suicided source and drain regions are aligned to edges of a gate region including at least the folly suicided metal gate.
2. The semiconductor structure of Claim 1 wherein said first thickness is greater than 500 A and the second thickness is less than 500 A.
3. The semiconductor structure of Claim 2 wherein said second thickness is less than 300 A.
4. The semiconductor structure of Claim 2 wherein said second thickness is less than 200 A.
5. The semiconductor structure of Claim 1 wherein the first and second suicide metals are comprised of the same silicide metal.
6. The semiconductor structure of Claim 1 wherein the first and second silicide metals are comprised of the different silicide metal.
7. The semiconductor structure of Claim 5 wherein the same silicide metal comprises a silicide of at least one of Ti, Ta, W, Co, Ni, Pt, Pd or alloys thereof.
8. The semiconductor structure of Claim 7 wherein the same metal silicide comprises a silicide of at least one of Co, Ni or Pt.
9. The semiconductor structure of Claim 6 wherein the different silicide metals comprise a silicide of at least two of Ti, Ta, W, Co, Ni, Pt, Pd or alloys thereof
10. The semiconductor structure of Claim 9 wherein the different suicide metals comprise a suicide of at least two of Co, Ni or Pt.
11. The semiconductor structure of Claim 1 wherein said first suicide metal comprises NiSi, NiPtSi or a combination thereof, and said second suicide metal comprises NiSi.
12. The semiconductor structure of Claim 1 wherein said first silicide metal comprises NiSi, NiPtSi or a combination thereof, and said second silicide metal comprises CoSi2.
13. A metal oxide semiconductor (MOS) device comprising a semiconductor substrate having suicided source and drain regions located on a surface thereof, said suicided source and drain regions having a thickness of less than 500 A and are self- aligned to edges of a gate region that includes a fully suicided metal gate having a thickness of greater than 500 A.
14. The MOS device of Claim 13 wherein said thickness of said suicided source/and drain regions is less than 300 A.
15. The MOS device semiconductor structure of Claim 13 wherein said thickness of said suicided source and drain regions is less than 200 A.
16. The MOS device of Claim 13 wherein the suicided source and drain regions and the suicided metal gate are comprised of the same silicide metal.
17. The MOS device of Claim 13 wherein the suicided source and drain regions and the suicided metal gate are comprised of the different silicide metal.
18. The MOS device of Claim 16 wherein the same silicide metal comprises a silicide of at least one of Ti, Ta, W, Co, Ni, Pt, Pd or alloys thereof.
19. The MOS device of Claim 18 wherein the same metal suicide comprises a suicide of at least one of Co, Ni or Pt.
20. The MOS device of Claim 17 wherein the different suicide metals comprise a suicide of at least two of Ti, Ta, W, Co, Ni, Pt, Pd or alloys thereof
21. The MOS device of Claim 20 wherein the different suicide metals comprise a suicide of at least two of Co, Ni or Pt.
22. The MOS device of Claim 13 wherein said suicided metal gate comprises NiSi, NiPtSi or a combination thereof, and said suicided source and drain regions comprise NiSi.
23. The MOS device of Claim 13 wherein said suicided metal gate comprises NiSi, NiPtSi or a combination thereof, and said suicided source and drain regions comprise CoSi2.
24. A method of forming an advanced metal oxide semiconductor structure comprising the steps of:
providing a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, a dielectric liner on at least sidewalls of said polysilicon gate conductor, and spacers on said dielectric liner and adjoining sidewalls of at least the polysilicon gate conductor;
depositing a material stack comprising a conformal dielectric layer and a planarizing dielectric layer on the structure including atop the at least one patterned gate stack; removing portions of the conformal dielectric layer and planarizing dielectric layer to expose said dielectric cap;
removing the exposed dielectric cap to expose the polysilicon gate conductor; converting the polysilicon gate conductor into a fully suicided metal gate;
exposing said source and drain regions; and
saliciding said source and drain regions to form suicided source and drain regions that have a thickness that is less than the fully suicided metal gate.
25. The method of Claim 24 wherein the steps are modified such that suicided source and drain regions are formed in the providing step.
26. The method of Claim 24 wherein said removing said portions of the conformal dielectric layer and the planarizing dielectric layer comprises an etch back process.
27. The method of Claim 24 wherein said removing said portions of the conformal dielectric layer and the planarizing dielectric layer comprises chemical mechanical polishing.
28. The method of Claim 24 wherein said removing the exposed dielectric cap comprises an etching process.
29. The method of Claim 28 wherein said etching process comprises a wet etch in which dilute hydrofluoric acid is employed.
30. The method of Claim 24 wherein said converting the polysilicon gate conductor comprises a salicidation process.
31. The method of Claim 30 wherein said salicidation process comprises forming at least one metal that can react with polysilicon to form a metal suicide cm the exposed polysilicon gate conductor, first annealing to form a first suicide phase, removing any unreacted metal and optional second annealing to covert the first suicide phase into a second suicide phase.
32. The method of Claim 31 wherein said first annealing is performed at a temperature from about 300° to about 600°C.
33. The method of Claim 31 wherein said optional second annealing is performed at a temperature from about 600° to about 800°C.
34. The method of Claim 31 wherein said first annealing and said optional second anneal are conducted in an atmosphere comprising He, Ar, N2 or a forming gas.
35. The method of Claim 24 wherein said fully suicided metal gate comprises NiSi or NiSiPt and said suicided source drain comprise CoSi2.
36. The method of Claim 24 wherein said fully suicided metal gate comprises NiSi or NiSiPt and said suicided source drain comprise NiSi.
37. A method of forming an advanced metal oxide semiconductor structure comprising the steps of:
providing a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor, an overlying dielectric cap, and spacers on adjoining sidewalls of at least the polysilicon gate conductor;
forming a patterned photoresist atop the structure including said at least one patterned gate stack, said patterned photoresist containing an opening that exposes said dielectric cap;
selectively removing the exposed dielectric cap utilizing a dry etching process to expose the polysilicon gate conductor;
removing the patterned photoresist;
converting the polysilicon gate conductor into a fully suicided metal gate; and saliciding said source and drain regions to form suicided source and drain regions that have a thickness that is less than the fully suicided metal gate.
38. The method of Claim 37 wherein the steps are modified such that suicided source and drain regions are formed in the providing step.
39. The method of Claim 37 wherein said patterned photoresist comprises a negative-tone resist.
40. The method of Claim 37 wherein said patterned photoresist comprises a positive- tone resist.
41. The method of Claim 37 further comprising applying a lift-off layer so as to surround said at least one patterned gate stack.
42. The method of Claim 41 wherein a portion of the lift-off layer atop the patterned gate stack is removed prior to removing said dielectric cap.
43. The method of Claim 41 wherein the patterned photoresist above said lift-off layer is removed after selectively removing the dielectric cap but prior to converting the polysilicon gate conductor into a fully suicided metal gate using a lift-off process.
44. The method of Claim 43 wherein said converting comprising a first anneal and optionally a second anneal with no selective etching employed therebetween.
45. The method of Claim 37 wherein said selectively removing said exposed dielectric cap comprises a dry etching process.
46. The method of Claim 37 wherein said converting step comprises forming at least one metal that can react with polysilicon to form a metal suicide on said exposed polysilicon gate conductor, first annealing to form a first suicide phase, removing any unreacted metal and optional second annealing to covert the first suicide phase into a second suicide phase.
47. The method of Claim 46 wherein said first annealing is performed at a temperature from about 300° to about 600°C.
48. The method of Claim 46 wherein said optional second annealing is performed at a temperature from about 600° to about 800°C.
49. The method of Claim 46 wherein said first annealing and said optional second anneal are conducted in an atmosphere comprising He, Ar, N2 or a forming gas.
50. The method of Claim 37 wherein said fully suicided metal gate comprises NiSi or NiSiPt and said suicided source drain comprise CoSi2.
51. The method of Claim 37 wherein said fully suicided metal gate comprises NiSi or NiSiPt and said suicided source drain comprise NiSi.
52. A method of forming an advanced metal oxide semiconductor structure comprising the steps of:
providing a structure comprising at least one patterned gate stack and abutting source and drain regions, said at least one patterned gate stack including a polysilicon gate conductor an overlying dielectric cap, and spacers on adjoining sidewalls of least the polysilicon gate conductor;
depositing a stack comprising a planarizing material, a masking layer and a photoresist on the structure including atop the at least one patterned gate stack;
patterning the stack to expose the dielectric cap;
selectively removing the exposed dielectric cap utilizing a dry etching process to expose the polysilicon gate conductor; removing the patterned stack;
converting the polysilicon gate conductor into a folly suicided metal gate; and
saliciding said source and drain regions to form suicided source and drain regions that have a thickness that is less than the folly suicided metal gate.
53. The method of Claim 52 wherein the steps are modified such that silicided source and drain regions are formed in the providing step.
54. The method of Claim 52 wherein said photoresist comprises a negative-tone resist.
55. The method of Claim 52 wherein said photoresist comprises a positive-tone resist.
56. The method of Claim 52 further comprising applying a lift-off layer so as to surround said at least one patterned gate stack.
57. The method of Claim 56 wherein a portion of the lift-off layer atop the patterned gate stack is removed prior to removing said dielectric cap..
58. The method of Claim 56 wherein the patterned photoresist above the lift-off layer is removed after selectively removing the dielectric cap but prior to converting the polysilicon gate conductor into a folly silicided metal gate using a lift-off process.
59. The method of Claim 58 wherein said converting comprising a first anneal and optionally a second anneal with no selective etching employed therebetween.
60. The method of Claim 52 wherein said selectively removing said exposed dielectric cap comprises a dry etching process.
61. The method of Claim 52 wherein said converting step comprises forming at least one metal that can react with polysilicon to form a metal suicide on the exposed polysilicon gate conductor, first annealing to form a first suicide phase, removing any unreacted metal and optional second annealing to covert the first suicide phase into a second suicide phase.
62. The method of Claim 61 wherein said first annealing is performed at a temperature from about 300° to about 600°C.
63. The method of Claim 61 wherein said optional second annealing is performed at a temperature from about 600° to about 800°C.
64. The method of Claim 61 wherein said first annealing and said optional second anneal are conducted in an atmosphere comprising He, Ar, N2 or a forming gas.
65. The method of Claim 52 wherein said fully suicided metal gate comprises NiSi or NiSiPt and said suicided source drain comprise CoSi2.
66. The method of Claim 52 wherein said fully suicided metal gate comprises NiSi or NiSiPt and said suicided source drain comprise NiSi.
Priority Applications (2)
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| JP2007520293A JP2008506253A (en) | 2004-07-06 | 2005-03-10 | Method for the formation of silicided metal gates |
| EP05725271A EP1807875A4 (en) | 2004-07-06 | 2005-03-10 | Methods for the formation of fully silicided metal gates |
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| US10/885,462 | 2004-07-06 | ||
| US10/885,462 US7705405B2 (en) | 2004-07-06 | 2004-07-06 | Methods for the formation of fully silicided metal gates |
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| WO2006014188A2 true WO2006014188A2 (en) | 2006-02-09 |
| WO2006014188A3 WO2006014188A3 (en) | 2006-11-23 |
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| EP (1) | EP1807875A4 (en) |
| JP (2) | JP2008506253A (en) |
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| CN (1) | CN100461463C (en) |
| TW (1) | TWI364796B (en) |
| WO (1) | WO2006014188A2 (en) |
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Also Published As
| Publication number | Publication date |
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| TW200618119A (en) | 2006-06-01 |
| KR20070029799A (en) | 2007-03-14 |
| CN100461463C (en) | 2009-02-11 |
| CN1981386A (en) | 2007-06-13 |
| KR100945785B1 (en) | 2010-03-08 |
| TWI364796B (en) | 2012-05-21 |
| JP2012124519A (en) | 2012-06-28 |
| EP1807875A4 (en) | 2008-11-19 |
| US7705405B2 (en) | 2010-04-27 |
| JP2008506253A (en) | 2008-02-28 |
| JP5400913B2 (en) | 2014-01-29 |
| US20090029515A1 (en) | 2009-01-29 |
| US8178433B2 (en) | 2012-05-15 |
| US20060006476A1 (en) | 2006-01-12 |
| EP1807875A2 (en) | 2007-07-18 |
| WO2006014188A3 (en) | 2006-11-23 |
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