WO2006013279A3 - Procede de partage de temps d'un processeur - Google Patents
Procede de partage de temps d'un processeur Download PDFInfo
- Publication number
- WO2006013279A3 WO2006013279A3 PCT/FR2005/001712 FR2005001712W WO2006013279A3 WO 2006013279 A3 WO2006013279 A3 WO 2006013279A3 FR 2005001712 W FR2005001712 W FR 2005001712W WO 2006013279 A3 WO2006013279 A3 WO 2006013279A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- software
- secure
- execution mode
- processor
- called
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
- Hardware Redundancy (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/631,511 US20070283361A1 (en) | 2004-07-06 | 2005-07-04 | Processor Time-Sharing Method |
EP05786106A EP1766519A2 (fr) | 2004-07-06 | 2005-07-04 | Procede de partage de temps d'un processeur |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0407496 | 2004-07-06 | ||
FR0407496A FR2872933B1 (fr) | 2004-07-06 | 2004-07-06 | Procede de partage de temps d'un processeur |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006013279A2 WO2006013279A2 (fr) | 2006-02-09 |
WO2006013279A3 true WO2006013279A3 (fr) | 2006-05-04 |
Family
ID=34949106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2005/001712 WO2006013279A2 (fr) | 2004-07-06 | 2005-07-04 | Procede de partage de temps d'un processeur |
Country Status (4)
Country | Link |
---|---|
US (1) | US20070283361A1 (fr) |
EP (1) | EP1766519A2 (fr) |
FR (1) | FR2872933B1 (fr) |
WO (1) | WO2006013279A2 (fr) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20080014786A (ko) * | 2005-06-01 | 2008-02-14 | 마츠시타 덴끼 산교 가부시키가이샤 | 컴퓨터시스템 및 프로그램 생성장치 |
US8214296B2 (en) * | 2006-02-14 | 2012-07-03 | Microsoft Corporation | Disaggregated secure execution environment |
US8261345B2 (en) * | 2006-10-23 | 2012-09-04 | Endeavors Technologies, Inc. | Rule-based application access management |
US8892738B2 (en) | 2007-11-07 | 2014-11-18 | Numecent Holdings, Inc. | Deriving component statistics for a stream enabled application |
US8819839B2 (en) | 2008-05-24 | 2014-08-26 | Via Technologies, Inc. | Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levels |
US8607034B2 (en) | 2008-05-24 | 2013-12-10 | Via Technologies, Inc. | Apparatus and method for disabling a microprocessor that provides for a secure execution mode |
US20120102242A1 (en) * | 2010-10-26 | 2012-04-26 | Kaminario Technologies Ltd. | Controlling data destaging within a multi-tiered storage system |
CN105068861A (zh) * | 2015-07-09 | 2015-11-18 | 合肥君正科技有限公司 | 一种事务执行方法及装置 |
FR3086772B1 (fr) * | 2018-10-01 | 2021-11-12 | Stmicroelectronics Grand Ouest Sas | Procede de gestion d'une alimentation dvfs et systeme correspondant |
FR3100901B1 (fr) * | 2019-09-12 | 2021-08-27 | Stmicroelectronics Grand Ouest Sas | Système de protection de la mémoire |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001046800A2 (fr) * | 1999-12-23 | 2001-06-28 | General Instrument Corporation | Processeur bimodal |
US20040105298A1 (en) * | 2002-11-18 | 2004-06-03 | Arm Limited | Apparatus and method for managing processor configuration data |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55112651A (en) * | 1979-02-21 | 1980-08-30 | Fujitsu Ltd | Virtual computer system |
JP2900767B2 (ja) * | 1993-09-20 | 1999-06-02 | 株式会社日立製作所 | 仮想計算機システムの仮想計算機走行時間間隔制御方式 |
US6078747A (en) * | 1998-01-05 | 2000-06-20 | Jewitt; James W. | Application program interface to physical devices |
US7191440B2 (en) * | 2001-08-15 | 2007-03-13 | Intel Corporation | Tracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor |
US7370324B2 (en) * | 2003-09-30 | 2008-05-06 | Intel Corporation | Switching between a service virtual machine and a guest virtual machine in a virtual machine monitor environment |
US7475002B1 (en) * | 2004-02-18 | 2009-01-06 | Vmware, Inc. | Method and apparatus for emulating multiple virtual timers in a virtual computer system when the virtual timers fall behind the real time of a physical computer system |
-
2004
- 2004-07-06 FR FR0407496A patent/FR2872933B1/fr not_active Expired - Fee Related
-
2005
- 2005-07-04 US US11/631,511 patent/US20070283361A1/en not_active Abandoned
- 2005-07-04 EP EP05786106A patent/EP1766519A2/fr not_active Withdrawn
- 2005-07-04 WO PCT/FR2005/001712 patent/WO2006013279A2/fr active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001046800A2 (fr) * | 1999-12-23 | 2001-06-28 | General Instrument Corporation | Processeur bimodal |
US20040105298A1 (en) * | 2002-11-18 | 2004-06-03 | Arm Limited | Apparatus and method for managing processor configuration data |
Non-Patent Citations (2)
Title |
---|
RAVI S ET AL: "Tamper resistance mechanisms for secure, embedded systems", VLSI DESIGN, 2004. PROCEEDINGS. 17TH INTERNATIONAL CONFERENCE ON MUMBAI, INDIA 5-9 JAN. 2004, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 5 January 2004 (2004-01-05), pages 605 - 610, XP010679056, ISBN: 0-7695-2072-3 * |
YORK ET AL: "A New Foundation for CPU Systems Security : Security Extensions to the ARM Architecture", WHITE PAPER ARM, XX, XX, May 2003 (2003-05-01), pages 1 - 8, XP002278307 * |
Also Published As
Publication number | Publication date |
---|---|
US20070283361A1 (en) | 2007-12-06 |
FR2872933A1 (fr) | 2006-01-13 |
WO2006013279A2 (fr) | 2006-02-09 |
EP1766519A2 (fr) | 2007-03-28 |
FR2872933B1 (fr) | 2008-01-25 |
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