WO2006012875A3 - Method for evaluating a test program quality - Google Patents

Method for evaluating a test program quality Download PDF

Info

Publication number
WO2006012875A3
WO2006012875A3 PCT/DE2005/001349 DE2005001349W WO2006012875A3 WO 2006012875 A3 WO2006012875 A3 WO 2006012875A3 DE 2005001349 W DE2005001349 W DE 2005001349W WO 2006012875 A3 WO2006012875 A3 WO 2006012875A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
test program
evaluating
mutant
program quality
Prior art date
Application number
PCT/DE2005/001349
Other languages
German (de)
French (fr)
Other versions
WO2006012875A2 (en
Inventor
Joerg Grosse
Mark Hampton
Original Assignee
Certess S A
Joerg Grosse
Mark Hampton
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Certess S A, Joerg Grosse, Mark Hampton filed Critical Certess S A
Priority to DE502005006290T priority Critical patent/DE502005006290D1/en
Priority to US11/658,930 priority patent/US8311793B2/en
Priority to EP05771429A priority patent/EP1771799B1/en
Publication of WO2006012875A2 publication Critical patent/WO2006012875A2/en
Publication of WO2006012875A3 publication Critical patent/WO2006012875A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The invention relates to a method for evaluating an integrated circuit test program simulated with the aid of a computer and consisting (a) in providing a first file describing an integrated circuit, (b) in simulating a mutant integrated circuit obtainable by introducing mutations into the integrated circuit described at the first stage, (c) in supplying input values to the mutant integrated circuit and detecting output values produced by the mutant integrated circuit for said input values, (d) in comparing the output values produced by the mutant integrated circuit with expected values produced by the test program, wherein said expected values are generated in a reference system and (e) in evaluating the test program quality by means of comparison results.
PCT/DE2005/001349 2004-07-30 2005-07-28 Method for evaluating a test program quality WO2006012875A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE502005006290T DE502005006290D1 (en) 2004-07-30 2005-07-28 METHOD FOR EVALUATING THE GOODS OF A TEST PROGRAM
US11/658,930 US8311793B2 (en) 2004-07-30 2005-07-28 Method for evaluating a test program quality
EP05771429A EP1771799B1 (en) 2004-07-30 2005-07-28 Method for evaluating the quality of a test program

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004037402A DE102004037402B4 (en) 2004-07-30 2004-07-30 Method for evaluating the quality of a test program
DE102004037402.3 2004-07-30

Publications (2)

Publication Number Publication Date
WO2006012875A2 WO2006012875A2 (en) 2006-02-09
WO2006012875A3 true WO2006012875A3 (en) 2006-05-26

Family

ID=35345117

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2005/001349 WO2006012875A2 (en) 2004-07-30 2005-07-28 Method for evaluating a test program quality

Country Status (5)

Country Link
US (1) US8311793B2 (en)
EP (1) EP1771799B1 (en)
AT (1) ATE418108T1 (en)
DE (2) DE102004037402B4 (en)
WO (1) WO2006012875A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8997034B2 (en) * 2012-07-30 2015-03-31 Synopsys, Inc. Emulation-based functional qualification
US10394533B2 (en) * 2013-09-30 2019-08-27 The Mathworks, Inc. Reusable component in a modeling environment
GB2519545A (en) * 2013-10-24 2015-04-29 Ibm Determining a quality parameter for a verification environment
CN105335379B (en) 2014-06-26 2018-11-02 国际商业机器公司 The method and apparatus to sort to the combination of mutation, test case, random seed in mutation test
US9952837B1 (en) 2015-04-01 2018-04-24 The Mathworks, Inc. Reusable component in a modeling environment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19959157A1 (en) * 1999-01-25 2000-08-03 Hewlett Packard Co Improved function testing for computer software by first stage filtering out of large bugs or defects in source code by insertion of large syntax errors into source code modules to be detected by the testing system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2147036A1 (en) * 1994-05-16 1995-11-17 Yih-Farn Robin Chen System and method for selective regression testing
US5724504A (en) * 1995-06-01 1998-03-03 International Business Machines Corporation Method for measuring architectural test coverage for design verification and building conformal test
US5754760A (en) * 1996-05-30 1998-05-19 Integrity Qa Software, Inc. Automatic software testing tool
US6931629B1 (en) * 1999-12-30 2005-08-16 Intel Corporation Method and apparatus for generation of validation tests
EP1382976B1 (en) * 2002-07-19 2007-02-28 Infineon Technologies AG Method of processing test patterns for an integrated circuit
FR2843214B1 (en) * 2002-07-30 2008-07-04 Bull Sa METHOD FOR FUNCTIONALLY CHECKING AN INTEGRATED CIRCUIT MODEL TO CONSTITUTE A VERIFICATION PLATFORM, EMULATOR EQUIPMENT AND VERIFICATION PLATFORM.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19959157A1 (en) * 1999-01-25 2000-08-03 Hewlett Packard Co Improved function testing for computer software by first stage filtering out of large bugs or defects in source code by insertion of large syntax errors into source code modules to be detected by the testing system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JEFFERSON OFFUTT A: "INVESTIGATIONS OF THE SOFTWARE TESTING COUPLING EFFECT", ACM TRANSACTIONS ON SOFTWARE ENGINEERING AND METHODOLOGY, ASSOCIATION FOR COMPUTING MACHINERY, NEW YORK, US, vol. 1, no. 1, January 1992 (1992-01-01), pages 5 - 20, XP000365048, ISSN: 1049-331X *
KING K N ET AL: "A FORTRAN LANGUAGE SYSTEM FOR MUTATIONBASED SOFTWARE TESTING*", SOFTWARE PRACTICE & EXPERIENCE, WILEY & SONS, BOGNOR REGIS, GB, vol. 21, no. 7, 1 July 1991 (1991-07-01), pages 685 - 718, XP000297324, ISSN: 0038-0644 *
VADO P ET AL: "A methodology for validating digital circuits with mutation testing", CIRCUITS AND SYSTEMS, 2000. PROCEEDINGS. ISCAS 2000 GENEVA. THE 2000 IEEE INTERNATIONAL SYMPOSIUM ON MAY 28-31, 2000, PISCATAWAY, NJ, USA,IEEE, vol. 1, May 2000 (2000-05-01), pages I343 - I346, XP010503205, ISBN: 0-7803-5482-6 *

Also Published As

Publication number Publication date
WO2006012875A2 (en) 2006-02-09
US8311793B2 (en) 2012-11-13
DE102004037402B4 (en) 2011-02-03
DE102004037402A1 (en) 2006-03-23
EP1771799B1 (en) 2008-12-17
DE502005006290D1 (en) 2009-01-29
EP1771799A2 (en) 2007-04-11
US20100057424A1 (en) 2010-03-04
ATE418108T1 (en) 2009-01-15

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